Diptiman Ray Chaudhuri Monojit Mitra

NonlinearInsights (OPC)Pvt. Ltd.

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by Diptiman Ray Chaudhuri Monojit Mitra
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Preface

The journey of digital systems started with the development of the mechanical adder in 1642 by Pascal and a lot of developments took place over the years till 1854 when Boole developed a special algebra for modern digital electronics and computer circuits. After that, the introduction of digital adder, subtracter, multiplexer, encoder, decoder, logic gates and their use in register as memory and counter have enriched the subject. All these topics are now divided into two broad categories as Combinational and Sequential circuits. From the above consideration, the present book is written to serve the need of a fundamental text, covering the complete range of the foundation materials in switching theory and digital design. The solved and unsolved problems of different chapters will make the subject easy to understand.

Though the book is primarily for the first level course for the students of B.E./ B.Tech courses in Electronics & Communication, Computer Science, Information Technology and Electrical Engineering of every Engineering Colleges and at the same time, the UG/PG general science students of any University will also be benefited after going through the book for their course on Electronic Science, Computer Science and Physics. This book is also helpful for the student appearing in different examinations like GATE, ISRO, DRDO etc.

Last but not least, there may be some printing errors which have escaped despite our alertness. Any such errors or shortcomings along with suggestions will be highly appreciated for further improvement of the book in the next edition.

Dr. Diptiman Ray Chaudhuri

Acknowledgment

My sincere acknowledgment goes to my beloved teacher and the legendary Professor, Late Prof. B. R. Nag, my Ph.D. guide, Prof. P.K. Basu and my colleagues at Calcutta University, Prof. Somenath Sarkar, Prof. Sanatan Chattopadhyay, Prof. Gautam Ghosh and Dr. Shyamal Mukherjee.

Dr. Diptiman Ray Chaudhuri

My first sincere acknowledgment goes to my beloved teacher and incidentally the first author of this book, Prof. Diptiman Ray Chaudhuri who taught us the subject ‘Digital Electronics’ at our college level and also helped us to build different projects based on this subject.

I thankfully acknowledge the contributions of various scientists and researchers who have enriched the subject with their vast knowledge and works.

I am also grateful to my wife Mrs. Chaitali Mitra and my two sons Sandipan and Sagnik for their constant inspiration from the very first day when I just started working on the book.

CONTENTS

CHAPTER 1 INTRODUCTION 1-4

CHAPTER 2 NUMBER SYSTEM AND COMPUTER CODES 5-64
2.1 Introduction 5
2.2 Number systems 6
2.3 Arithmetic Operation with Non-Decimal Numbers 22
2.4 Signed Number Representation 36
2.5 Signed Multiplication 39
Ascii Code 55
2. 6 Error Detecting and Correction Codes 56
Problems 63
CHAPTER 3 BASIC LOGIC GATES AND THEIR PROPERTIES 65-88
3.1 Introduction 65
3.2 Logic Gates Types 66
3.3 Enable and Inhibit Properties of Logic Gates 77
3.4 Active Levels of a Logic Signal 80
3.5 Logic Gate Duality 82
Problems
CHAPTER 4

85
BOOLEAN SWITCHING ALGEBRA AND ITS APPLICATIONS 89-108
4.1 Introduction 89
4.2 Postulates of Switching Algebra 89
4.3 Theorems of the Switching Algebra 91
4.4 Cannonical Forms of Switching Functions 102
Problems 107
CHAPTER 5 SIMPLIFICATION OF BOOLEAN EXPRESSION 109-160
5.1 Introduction 109
5.2 Formation of Karnaugh Map for Switching Functions 109
5.3 Simplification of Switching Functions using Karnaugh Maps 119
5.4 Some Definitions 127
5.5 Simplification of 4-Variable Function Using Fourth-order K-map 131
5.6 Uncompletely Specified Functions (Don’t cares) 133
5.7 Quine Mccluskey Method of Minimisation 138
5.8 Quine Mcclusky Simplification of Functions Containing
Don’t Care Terms 153

CHAPTER 6 IMPLEMENTATION OF COMBINATION LOGIC CIRCUIT WITH BASIC LOGIC GATES 161-186
6.1 Introduction 161
6.2 And-or (or-And) Implementation of LogicCircuit 162
6.3 2-Level Logic Circuit Implementation
Using only Nand Gates 168
6.4 2-Level Logic Circuit Implementation using
only Nor Gates 173
6.5 Map Factoring Method 176
6.6 Dual Property of the Circuit 181
6.7 Xor Implementation of the Logic Circuits 182
Problems 184
CHAPTER 7 LOGIC FAMILIES 187-214
7.1 Transistor as an Inverter 187
7.2 Basic TTL Nand Gate Circuit 189
7.3 Electrical Characteristics of Logic Gates 195
7.4 Open Collector Type Logic Gates 200
7.5 Tristate Logic Gates (TSL Gates) 203
7.6 Mos Logic Family 204
7.7 Nmos Inverter 207
7.8 Logic Gates Using N-Channel Mosfet (Nmos) 209
7.10 Complementary Mos Logic 212
Problems 214
CHAPTER 8 COMBINATIONAL LOGIC CIRCUIT
IMPLEMENTATION WITH SSI AND MSI 215-264
8.1 Multiplexers 215
8.2Decoder 219
8.3 Parity Generators and Checkers 229
8.4 4-Bit Magnitude Comparator 232
8.5 Code Converters 234
8.6 Display and Display Driver 244
8.7 Encoders and Priority Encoders 254
Problems CHAPTER 9
261

SEQUENTIAL LOGIC CIRCUIT
AND BISTABLE DEVICES 265-294
9.1 Basic Memory Devices - Latches and FlipFlops 265
9.2 Latch 265
9.3 Flip Flops 274
9.4 T FlipFlop 282
9.5 D-Latch 285

CHAPTER 10 REGISTERS AND SHIFT REGISTERS 295-312

10.1 Introduction 295
10.2 Parallel Registers 295
10.3 Shift Registers 300
Problems 311

CHAPTER 11 COUNTERS 313-362
11.1 Introduction 313
11.2 Asynchronous Counters 314
11.3 Synchronous Counters 339
Problems 356

CHAPTER 12 MEMORIES 363-400
12.1 Introduction 363
12.2 Organization of Static Read/Write Memory 366
12.3 Ram Cells 373
12.4 Semiconductor Read-Only Memory (Rom) 380
12.5 Address Decoding and Row Selection 385
12.6 Types of Programmable Roms 386
12.7 Electrically Erasable Programmable Read Only
Memory (EEPROM OR E2PROM) 391
12.8 Dynamic Ram (Dram) Cell 395

Index 401-406

The Latin word Digitus, meaning finger or toe, is the origin of the words Digital and Digit and the association of these words with computational activity is linked to the way early people relied on their fingers for the purpose of counting.

A digital circuit is an electronic circuit that processes information and the information are expressed using a new number system called binary number system. The radix (0 and 1) are used in this numbering system. Each of these two digit symbols is called a Bit, the short form for Binary Digit.

Since a digital circuit obeys a certain set of logic rules, it is also called a Logic Circuit. The foundation of the logic rules was laid by the famous English mathematician, George Boole in 1834. Later on E.V. Huntington in 1904, simplified the logic rules proposed by G. Boole and this simplified form is the basic foundation on which the modern science and technology of the digital world stands. The improvement we see today in this branch of science is due to the efforts of many scientists and engineers who worked in this field at different times.

The following paragraph gives the names of some such illustrious persons and the nature of their attempt towards the development of the logic systems.
The mathematical development of Pascal, Gottfried, Boole, DeMorgon, Babbage, Huntington and others laid the foundation of the digital system.
• B.Pascal (English Mathematician) designed a mechanical adder in 1642.
• Gottfried (German Mathematician) developed a machine to multiply and divide in 1671.
• Charles Babbage living in 1800s developed an automatic mechanical calculating machine. He developed this machine to compute values for navigation tables and is recognised as the founder of modern computer.
• George Boole (English Mathematician) developed a special algebra that we know today as the Boolean Algebra, published in 1854 is the core of mathematical tools used for modern digital computer design.
• Jacquard who developed an automatic loom for weaving cloth in 19th century applied mathematical logic in the machine for commercial use.
• Nakashima in Japan in 1937 and C.E. Shannon in 1938 working for Bell laboratory for telephone switching in U.S.A. applied the untouched work of G.Boole as the mathematical tool. This was the first real life application of the work of the Boolean Algebra.

1

• E.V. Huntington in 1904 developed a minimum set of postulates to define Boolean algebra. He defined six postulates (later on these postulates were known as Huntington postulates) which is a subset of the generalised Boolean Algebra. In case of Boolean Algebra each variable could be assigned with many discrete values but in case of switching algebra a variable can be assigned with two discrete values (0 and 1) only. Huntington’s six postulates are valid for this 2-valued switching algebra.

The first digital computing system based on the switching theory was ENIAC (Electronic Numerical Integrator and Computer). It was developed in 1946 and marked the beginning of the first generation of computers. Vaccum tubes and mechanical relays were used for designing this computer. The size was enormous, speed was very slow, power consumption was large and hardware components were expensive.

With the invention of transistor by W. Brattain, J.Bardeen and W.Schockley in 1947, the first transistorised computer TRADIC was built by Bell Telephone Laboratories in 1954. But, the invention of the transistor led to the development of integrated circuit in 1960. This caused the further advancement of digital logic and computer systems. The classical architecture of the computers was outlined in 1946 by Von Neumann, Elbert and Mauchly and the first microprocessor– “Computer on a chip” was designed by Intel Corporation, U.S.A in 1970. The fabrication of microprocessor integrated chip provided a reduction in component count and physical size of large computers in such a way that a computer can today be placed on a table or even on the lap of the user.

The development of computer technology and digital micro-electronics in particular has shown the way of designing different specialised digital systems replacing the classical analog systems. Some examples are digital watches, calculators, controllers, music recording, cameras, communication system, telephone etc. Also, in many cases this digital technology is making possible applications that did not previously exist. If we closely examine the existing digital system then we will observe that a digital system must perform the following tasks in most of the major cases.

(a) Translate information from our analog world into a binary language that can be understood by the digital network.
(b) Perform the required calculations and operations using only binary digits ‘0’ and ‘1’.
(c) Return an expression to us in an analog form that we understand.
A digital circuit which accomplishes these three processes may look very complex at first time but it has been shown in this book that a circuit for a large digital system can be broken down to a few smaller subsystems called cells or modules which are straight forward to design. By cascading these smaller modules one can characterise the circuit of large and complex digital systems. This approach is called “Hierarchical design”. There are many logical tools which are available for this Hierarchical design.
Different types of cells or modules are available commercially in the form of an Integrated Circuit (IC) chip and each module is represented by an unique graphical symbol. These graphical symbols are useful for drawing the complete circuit of the large digital system. The circuit diagram showing the interconnection between such graphical symbols is called the “Logic diagram” for the whole digital system. This logic diagram with interconnected symbols 3
of the modules provides a pictoral representation for the data flow in the system. Therefore, it becomes easy for analysis and for further synthesis.

Now-a-days digital systems are always preferred over analog systems because of three main reasons : (i) Flexibility, (ii) Reliability, (iii) Cost.
An analog system designed for a purpose with some design parameters will serve the user forever for that purpose only, but the same analog system generally are not flexible to be used for another purpose which is closely allied to the earlier but with design parameters changed completely. This drawback can be avoided in the modern digital system where the user can use the same system for many purpose with different parameters. The parameter can be changed through a keyboard attached to the system. Thus, the digital system can be made programmable or software based. It means that only by changing the software instead of disturbing the existing hardware of the system the user can reuse the same digital system, for several purposes. Clearly, it is very difficult to obtain this degree of flexibility in the analog system.
The second advantage of the digital system is the reliability. To get some idea of how reliable digital systems can be, we need to look at the way in which the analog input parameters is represented by the binary bits ‘1’ and ‘0’ which is understandable by the digital system. For illustration, if we consider the analog parameters to be the voltage then the bit ‘1’ and ‘0’ will represent the range of voltage not a fixed value. For example, in the digital IC chips fabricated using TTL (Transistor-Transistor logic) technology, the bit ‘I’ represents a voltage range lying between +2.0V to 5V and bit ‘0’ represents a voltage range lying between OV to +0.8V. Since these values are represented by a range of voltage and not by a fixed value, therefore, any, minor change in voltage level due to noise pick-up or other external events will not cause a level-0 (represented by bit ‘0’) to be misinterpreted as a level-1 (represented by bit ‘1’) or viceversa. It is also possible to design the digital system not very much sensitive to severe noise pick-up for which the voltage representation corresponding to a bit ‘1’may change to the range for a bit ‘0’ or viceversa. This can be done by increasing the resolution of the digitised form of the analog input to be processed or stored in the digital system. In case of high resolution a loss of one or two bits representing any information in a digital form will affect the information to very small extent. A very good example is a compact disk (CD) where the digital information, representing sound, is encoded in such a way that 1 mm hole could be drilled through the disk without the loss of a single note. For this reason the digital system is more attractive for any application requiring highly reliable operation.
The cost of IC chips used in the digital systems are comparatively lower than the analog ICs and therefore the cost of the digital systems which are widely used in our everyday life e.g. watches, calculators, computers etc. is decreasing drastically day by day. A similar reduction in cost has been observed for the microprocessor and memories. These rapid reductions in cost are due to the advances in the fabrication technology of the IC chips.
In today’s world the technological development which has the most note worthy impact on our daily life is the digital technology. We can not think of any instruments required for any branch of science or any bedside entertainment gadgets without any touch of the digital circuits. The modern digital instruments are so user friendly that the students of the primary schools use the calculators instead of their fingers even for their simple arithmetic calculations. For the high performance, reduced size and very low power consumption the digital IC chips have converted the table-top microcomputer of a few years back to palm top computer.

The ability of storing huge data base in CD ROM and retrieval information via CD ROM and internet are immensely helping the business people to do their business sitting comfortably at home. In Universities and even in school this data retrieval technology permits the access to specialised areas of literature, music, religion, geography, mathematics, medicine and physical science. Now-a-days a doctor sitting in his chamber may seek advice and suggestion from any other doctor sitting in the other corner of the world without much effort. All this is due to the use of digital circuits.
Computer graphics have become a very useful tool for the production of movies. Movies like the Jurassic Park and the Star War series are the first step in this area. This has established a new era in the art of movie making. People who are fond of music can listen to the clear and noise free sound from a CD which is digitally recorded. Photographer can use digital cameras and housewives can use the digitally controlled washing machine to make their life simple. These are a few examples out of a big list of the use of digital circuits.
Comparing with the huge and rapid technological growth and use in the field of the digital systems in the last 20 years, it is a very difficult task to extrapolate the future development in this field in the coming few decades. Following are some examples which are the future expectations of the technologists working in this field.
Mechanically operated magnetic storage systems (disk drive) used in a computer today will soon be replaced by MR(magneto resistive) technology. This technology will increase the storage capacity by more than 100 gigabytes /sq inch.
The OAWD (optically assisted winchestor drive) and MO (magneto-optical) technology are expected to push the upper limit of the storage capacity even further. Therefore, in future the size of the storage medium will be reduced but the capacity will be increased enormously.
The film cameras which we use today will be replaced by the digital cameras having megapixel resolution and huge audio storage capacity. These cameras will be able to store all the pictures of a complete movie in the memory and can be reviewed on a computer for editing and then can be projected on a screen.
The conventional CRT monitors of the present day computers will eventually be replaced by LCD monitors or by micropanel displays using DLP (digital light processing) or FED (field emission display) technologies. HDTV (digitised high defintion TV) will replace all the conventional TV sets. Therefore, larger, sharper and brighter pictures are expected on TVs and computers
With the advancement of optical recognition technologies the field of robotics is expected to improve to a large extent. For example, iris and retinal pattern recognition will eventually be used to limit access to certain protected places and may even replace the conventional manual locking system. Mass production jobs in an industry can be guided by these type of robots.
Present work on speech recognition, speech synthesis and handwriting pattern recognition will equip the future computer technology to build up ideas from a series of spoken words so that there will be no need of a keyboard.
Rapidly changing digital technology will have profound impact on every sphere of our daily life, therefore more pressure and responsibility have to be borne by the universities to offer quality training to the students so that they might keep pace with the rapid advancement in digital technology.

2. 1 INTRODUCTION

Numbers are used very often in our daily life to keep track of all sorts of quantities and computations but the number can’t be defined in a strictly rigorous manner. Numbers are nothing but symbolic representations and it provides the basis for conveying and quantifying informatiom. In the earlier days the human beings used to use the ten fingers for quantifying information and calculations. Later on ten symbols 0,1,2,3,4,5,6,7,8,9 were used for this purpose. Still today these symbols are popular for hard-copy of information. A computer may be called an information processing machine and this information may be either numeric or nonnumeric but, in both cases, the net effect is that all information appears in numbers. For this reason, the symbols to be used in the number system should be distinguishable and the computer should be able understand all the symbols seperately. The digital computers can recognise only two symbols identifying two information. It means that the computer needs a number system having two distinguishable states. The name of this number system is called Binary Number system. In this number high voltage and low voltage, high current and low current or switch-ON and OFF etc. are the states.

This chapter covers the binary number system in detail. The closely related number system will also be discussed briefly. Also, we shall study the different methods for converting a number from one number system to another.

Finally, it is known to us that when a person conveys some information to another, some codes are used to keep the conveyed information secret. But the codes are understandable by the two persons. The codes are nothing but an well defined mixture of the digit symbols. There may be different types of codes used for different field of application. Only a few widely used codes will be discussed in this chapter.

5
2.2 NUMBER SYSTEMS

Mainly, there are two types of number representations. One is symbolic and other is very much popular and normally used representation is called the Arabic number system. This number system is weighed and positional. The number system that evolve out of the position that the digits occupy relative to one another is known as the positional number system.

2.2.1 Weighted Positional Number System

A positional number system is characterised by the radix (or base). Each positional number system has its own radix and the number system is named after the radix. Also, the radix of a number system indicates the number of distinguished digit symbols which can be used in that number system. For example, for our daily used number system is the decimal number system whose radix is 10. Therefore, for this number system the number of digit symbols are 0,1,2,3,4,5,6,7,8,9. For the binary number system which the digital circuit can understand has the radix 2 and therefore there are two distinguished digit symbols 0 and 1. In general, for a number system with radix r the digit symbols will be 0,1,2,3,4.... (r–1).

For example, in hexadecimal number system the radix is 16 and therefore this number system has 16 distinguished digit symbols. But, we are familiar with only ten digit symbols 0 to 9 of the decimal number system and beyond 9 we don’t have any digit symbols which can be expressed using single digit. For this reason, beyond the ten digit symbols 0 to 9 some other six additional new symbols are chosen from the set of English alphabets to represent 10,11,12,13, 14 and 15 of the hexadecimal number system. These six alphabetic symbols are A, B, C, D, E and F to represent the values 10, 11,12, 13,14 and 15 of the hexadecimal number system.

In any number system, one number is written using a finite sequence of permissible digit symbols linked together. But in case of weighed positional number system we have to write digit symbols side-by-side carefully because the same digit symbol in a number has different value depending on its position in that number. For example, 222 in decimal number system 2 on the left most position has a value of 200, the digit 2 in the middle has a value of 20 and the digit 2 on the right most position has a value of 2 though the three digit symbols are same. The value of the digit symbol in a positional system depends on the weight of that position For each radix system, the value of the weight of a position has a fixed relationship with the radix of that number system and if we add up the weighed values of the string of digit symbols then we can get the equivalent decimal value of the number. For example, a number 123 in decimal has the positional weight 102 for the digit 1, 101 for the digit 2 and 100 for the digit 3. On the other hand if the same number 123 is in octal number system then the positional weights are 82 for the digit 1, 81 for the digit 2 and 80 for the digit 3.

In any number system of radix r, a number may contain an integer and a fractional part and a dot (•) is placed between these two parts. These dots indicates the end of the integer part and the begining of the fractional part of the number. This dot is called Radix Point. For example, the decimal number 456.78 consists of 456 as the integer part and 78 as the fractional part and the radix point (for decimal number this radix point is called the decimal point) is placed between them for seperation. For binary number system (radix 2), octal number system (r = 8) and hexadecimal number system (r = 16) this radix point is called as binary point, octal point and hexadecimal point respectively.

For an integer number the placement of the radix point at the end is optional and normally omitted. For example, in decimal number system the integer 4568• with dot is same as 4568 without dot. In general a number N with radix r i.e (N)rcan be written by linking the permisible digit symbols as follows (N) = (d-d- d ....d d ) • (d-d- d ....d d )
r ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐ ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐ ...(2.1)
Integer part of (N)r Radix Point Fractional part of (N)r = (NI)r· (NF)r
where (NI)r = Integer part of the number (N)r
(NF)r = Fractional part of the number (N)r
d = digit symbol available from the symbol set {0,1,2,....r–11}

The suffixes 0,1..... n–2, n–1 of digit d indicate the position of the digit symbol d in the integer part with reference to the radix point. From these values of suffixes we can calculate the weight of the digit symbols. For any digit di in the ith position on the left of radix point, the weight of this digit is ri where i may vary from 0 to n–1 in Eqn (2.1).

Similarly, the suffixes –1, –2...., – m indicate the position of the digit d in the fractional part (NF)r. The range of suffix –1 to –m means that there are m digits in the fractional part. For any digit di in the jth position on the right of the radix point the weight of this digit is r–j where j may vary from –1 to –m in Eqn (2.1).

From the Eqn(2.1) it is seen that for the integer part the digit d0, whose position is on the immediate left of the radix point has the minimum positional weight with value r0 as i = 0 and digit dn–1 whose position is furthest from the radix point for a n-digit integer number has the maximum positional weight rn–1. In number system the digit with the least positional weight is called the Least Significant Digit (LSD) and the digit with maximum positional weight is called the Most Significant Digit (MSD). Therefore, for the integer part of the number (N)r the digit d0 and dn–1 are called least significant and most significant digits respectively. Using the same arguments for the fractional part of (N)r the digit d–1 and d–m are called the most significant and least significant because the positional weight of d–1 is r–1 and that of d–m is r– m respectively.

The numerical value (M)10 in decimal for the number (N)r can be obtained by adding the weighted value of the digits of the number (N)r as follows :
(M)10 = dn–1rn–1 + dn–2rn–2 + ......d0r0 + d–1r –1 + d–2r –2 + dmr –m
n-1 -m
☐
d ri ☐ ☐ d ri
i i
=
i☐☐☐☐☐☐☐ ☐☐☐☐☐☐☐☐☐
decimal value decimal value of (N )i r of (NF)r
n-1 d ri= ☐
i =-mi
The TABLE 2.1 shows the digit symbols and the radix of different number systems and their name Radix Number system Digit Symbols
2 Binary 0,1
3 Ternary 0,1,2
4 Quaternary 0,1,2,3
5 Quinary 0,1,2,3,4
8 Octal 0,1,2,3,4,5,6,7 10 Decimal 0,1,2,3,4,5,6,7,8,9 12 Duodecimal 0,1,2,3,4,5,6,7,8,9, A,B 16 Hexadecimal 0,1,2,3,4,5,6,7,8,9, A,B,C,D,E,F Table 2.1 : Different number systems, digit symbols and name of the number systems.

2.2.2 Binary Number System

For binary number system the radix r is 2 and therefore for binary number systems we can use two digit symbol 0 and (r–1) =2-1 =1. It is a common practice not to use the term Binary Digit but to use the term Bit. The term bit is derived by taking “Bi” and “t” from the two words Binary Digit. Also, instead of using the symbol ‘d’to represent the digit in binary number system we shall use the symbol ‘b’ to represent the bit.

In natural binary system the number of bits in a unit of data may be called as follows

4 bits in a unit
8 bits in a unit
16 bits in a unit
32 bits in a unit
– Nibble (or half byte)
– Byte
– Two bytes (or half word)
– Double word The potential representation of a binary number is shown below.
•
b
n
b
n
b
.....b b☐ b b b .....b
☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐ ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐
Integer part of (N )I 2 of (N)2Binary Point Fractional part of (N )I 2 of (N)2 ...(2.2) where symbol for bit is bi which can have two values 0 and 1. This binary number (N)2 contains n bits on the integer part and m bits on the fractional part. For the integer part, b0 and bn–1 are least significant bit (LSB) and the most significant bit (MSB) and on the other hand for the fractional part b–1 and b–m are the MSB and LSB respectively. The positional weights for a few bit positions both for the integer and fractional parts of a binary number system is shown in TABLE 2.2.

Bits ...b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 • b–1 b–2 b–3 b–4 .... Weights 210 29 28 27 26 25 24 23 22 21 20 Binary 2–1 2–2 2–3 2–4 .... Weight point decimal ...1024 512 256 128 64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625

Table 2.2 : Positional weights of the bits in a binary number
2.2.2.1 Binary-to-Decimal Number Conversion (a) Weighted Sum Method : The simple way to convert a binary number (N)2 into its decimal equivalent value (M)10 is to find the weighted sum of bits. If a binary number (N)2 = (N1)2 + (NF)2 contains n bits on the integer part (N1)2 and m bits on the fractional part (NF)2 as shown in Eqn (2.2) then we may write (M)10= bn–12n–1 + bn–22n–2 + .....+ b121 + b020 + b–12–2 + .....+ b–m2–m
n- 1
=
☐ bi2i
i =m ... ...(2.3)
Find out the decimal value for the binary number 10111.0101.
For this binary number the integer part has 5 bits (n = 5) and the fractional part has 4 bits (m = 4). Therefore, the decimal value (M10) for this binary number is Decimal
Binary Number value 1 0 1 1 1 • 01 0 1

1 × 2–4 = 0.0625
0 × 2–3 = 0.0000
1 × 2–2 = 0.2500
0 × 2–1 = 0.0000
1 × 20 = 1.0000
1 × 21 = 2.0000
1 × 22 = 4.0000
0 × 23 = 0.0000
1 × 24 = 16.0000

Therefore, (10111.0101)2 = (23.2125)10
Find out the decimal value for the binary number 111011.10101
For this binary number the integer part has 6 bits (n = 6) and the fractional part has 5 bits (n = 5). Therefore, the decimal value (M)10 for this binary number is Decimal
Binary Number value 1 1 1 0 1 1 • 1 0 1 0 1

1 × 2–5 = 0.03125
0 × 2–4 = 0.00000
1 × 2–3 = 0.12500
0 × 2–2 = 0.00000
1 × 2–1 = 0.50000
1 × 20 = 1.00000
1 × 21 = 2.00000
0 × 22 = 0.00000
1 × 23 = 8.00000
1 × 24 = 16.00000
1 × 25 = 32.00000

Therefore, (111011.10101)2 = (59.65625)10 (59.65625)10
(i) Repeated Division Method for the conversion of a decimal integer into its binary The repeated division method can be applied efficiently to convert a decimal integer into its binary equivalent.

The steps to be followed for the repeated division method :
Step 1 : Divide the given decimal number (M)10 by 2.

Step 2 : The remainder (which may be either 0 or 1) out of the division in step 1 becomes the l.s.b (b0) of the equivalent binary number.
Step 3 : Divide the quotient of the previous division by 2 again.
Step 4 : The remainder (which may be either 0 or 1) out of the division in step 3 becomes the next higher significant bit of the equivalent binary number. Step 5 : Repeat step 3 and 4 until the quotient of division is 0. The remainder while the quotient is 0 is the m.s.b of the binary number.
Convert the decimal number (139)10 into its binary equivalent by the repeated division method.

Quotient Remainder
139/2 69 1 (LSB)b0

69/2 34 1
34/2 17 0
17/2 8 1
8/2 4 0
4/2 2 0
2/2 1 0
1/2 0 1 (MSB)b7
☐ (139)10= (10001011)2.

(ii) Repeated Multiplication Method for the conversion of a fractional decimal number into binary.
To convert a decimal fractional number into binary we have to use the repeated multiplication method. In this method the decimal fraction (MF)10 is multiplied by 2. This multiplication leads to a decimal number with integer and fraction. The integer part may be either 0 and 1. The integer part after this first multiplication gives the most significant bit b–1 of the equivalent binary fraction (NF)2 = b–1 b–2 ....b–m. The remaining fractional part of the decimal number again after multiplication by 2 leads to a new decimal number with integer (may be 0 or 1) and fraction. This integer gives b–2 of the desired fraction. In this way the integer part after each multiplication gives other consecutive binary bits b–3, b–4, ....., b–m. This process of multiplication by 2 has to be stopped when the fractional part of the decimal number after multiplication becomes zero.
Sometimes, we may not get the fractional part as zero after repeated multiplication. If the process of multiplication is stopped after a few repeated multiplication then we have to sacrifice the accuracy of conversion.

Convert (0.609375)10 into binary.

Integer Fraction
0.609375☐ 2 1 (MSB) .218750

0.218750 ☐ 2 0 .4375 0.4375☐ 2 0 .875 0.875☐ 2 1 .75

0.75 ☐ 2 1 .5
0.5☐ 2 1 (LSB) .0
☐ (.609375)10 = (.100111)2.

Convert (75.4375)10 into binary.
The integer and fraction part of the decimal number are 75 and 0.4375 respectively. For the integer and fraction we have to apply the repeated division and the repeated multiplication methods respectively to get the binary equivalent of (75.4375)10 number.

For the integer part
Quotient Remainder
75/2 37 1 (LSB)
37/2 18 1
18/2 9 0
9/2 4 1
4/2 2 0
2/2 1 0
1/2 0 1 (MSB) So, (75)10 = (1001011)2
and (75.4375)10 = (1001011.0111)2.

For the fraction part
Quotient Remainder 0.4375☐ 2 0 (MSB) .8750 0.8750☐ 2 1 .75

0.75☐ 2 1 .5 0.5☐ 2 1 (LSB) 0
(0.4375)10 = (0.0111)2
2.2.2.2 Upper Bound of Error Due to Truncation Let the decimal fraction (MF)10 when converted into a fractional number in another radix r either by the method of successive multiplication then the process of conversion may or may not terminate. Therefore, if the process is truncated after finite number of digits then an error will occur due to this termination. This error is called truncation error. In this section we will find the upper bound of this error when the conversion process is stopped after n digits.

Let in the nonterminating process we get
(MF)10 = (•d–1 d–2 d–3 .....d–n d–(n+1)d–(n+2) ......)r where d–1, d–2, d–3 .....d–n etc are the digits after the conversion of (MF)10 into another number system of radix r. If only n digits i.e. from d–1 to d–n are considered in the conversion then an error E will occur which can be written as E = (• d–1 d–2 d–3 .....d–n d–(n+1)d–(n+2) ......)r–(•d–1 d–2 d–3 .......d–n)r
= (.00 ......0 d–(n+1) d–(n+2).......)r
The value of this error E in decimal is
(E)10 = d–(n+1) r – (n+1)+d–(n+2)r –(n+2) ......
= r –(n+1) [d–(n+1) + d–(n+2)r – 1+ d–(n+3)r – 2 +......] ...(2.4) This error (E)10 will be maximum if all the digits d–(n+1) = d–(n+2) = d–(n+3) = ......= (r –1) because (r–1) is the maximum value of the digits in the number system with radix r. The upper bound of the error is found if we use (r–1) for all the digits in (E)10.

Therefore, (E)10 ☐ r – (n+1) [(r–1) + (r–1)r–1 + (r–1)r –2 +.....]
(r - 1)r☐ r – (n+1)· r - 1
☐ r – n ...(2.5) This is the maximum error when the digits after n digits from the radix point are dropped. For binary number system r = 2 and the upper bound of the error is 2–n.

Convert (0.431)10 into binary and drop out all the bits after nth bit position counting from the radix point. What will the value of n if 0.05% error is allowed due to the termination?

Integer Fraction
0.431 × 2 = 0 (MSB) .862

0.862 × 2 = 1 .724
0.724 × 2 = 1 .448
0.448 × 2 = 0 .896
0.896 × 2 = 1 .792
0.792 × 2 = 1 .584
0.584 × 2 = 1 .168
. . . . . . . . .

Therefore, (0.431)10 = (.0110111....)2.
If we keep only n bits to satisfy the error of 0.05% then 2–n < 0.0005
or, n < 11.
2.2.3 Octal Number System
Octal number system is another positional number systen with radix r = 8. The digit symbols used for this number system are 1 , 2 , 3 , 4 , 5 , 6 , 7

where all the digit symbols are taken from the decimal number system. The positional weight of the digit is a power of 8 and this power depends on the position either in the integer or in the fractional part. For an integer Octal number the positional weight of the Least Significant Digit (LSD) d0 is 80, for the next higher significant digit d1 the positional weight is 81 and in this way the power increases by 1 as we move towards left, from the radix point. Similarly, for the fractional octal number the positional weight is negative integer power of 8 i.e. 8–iwhere i indicates the position of the octal digit measured from the most significant digit position. The digit which is immediate right to the radix point (octal point) is the MostSignificant Digit (MSD) of the fractional part of the octal number with positional weight 8–1. For example, the octal fraction (NF)8

(NF)8 = •d–1 d–2 d–3 .....d–m containing m number of octal digits d–1, d–2,d–3 ....., d–m with positional weight 8–1, 8–2, 8–3,....., 8–m respectively. If the octal number contains n digits on the integer part and m digits on the fractional part then the representation of such an octal number is •
(N)
8
=
d
d
........d d ☐ d d ........d
☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐Octal ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐...(2.6)Integer point Fraction
2.2.3.1 Octal-to-Decimal Number Conversion The decimal equivalent value of any octal number can be obtained using the procedure similar to those followed in the conversion of binary to decimal.
Weighted Sum Method
In this method the weighted value of the octal digits are summed up to obtain the decimal value of an octal number containing both integer and fractional part.
Find the decimal value for the octal number (25720.056)8.
The decimal value of (25720.056)8 is (M)10 = 2☐ 84 + 5 ☐ 83 + 7 ☐ 82 + 2 ☐ 81 + 0 ☐ 80 + 0☐ 8–1 + 5 ☐ 8–2 + 6☐ 8–3 = 11216.089
2.2.3.2 Decimal-to-Octal Number Conversion
For octal integer we can follow the following method Repeated division by the radix (r = 8) to convert one decimal integer number into its octal equivalent.
Repeated Division Method for the conversion of Decimal Integer to Octal The repeated division was discussed earlier for the conversion of decimal to binary number. Using the identical approach we can convert a decimal to octal number. In this case of decimal to octal conversion we have to keep in mind that the radix is 8 and for this reason the repeated divisions are to be performed by 8. Following are a few examples.

Find the octal number for the decimal number (25670)10 by repeated division method.

Quotient Remainder 25670/8 3208 6 (LSD 3208/8 401 0
401/8 50 1
50/8 6 2
6/8 0 6 (MSD) Therefore, (25670)10 = (62106)8.
the following method
Repeated multiplication by the radix (r = 8). for fraction decimal number can be used
Repeated Multiplication Method for the Conversion of Decimal Fraction to Octal A decimal fraction can be converted to octal number by applying the repeated multiplication method as it was done in case of binary conversion. The multiplying factor for the conversion of decimal fraction to octal is 8 instead of 2. But sometimes the multiplication process does not have coverage. This non-convergent result will lead to an error when this process of multiplication is terminated keeping only n number of octal digits and dropping all the digits after nth digit in the fractional part of the converted octal number. It was shown earlier that the error arising out of this transaction will r–n when we drop the digits after the nth digit in the fraction part after the conversion of a decimal fraction.

Convert (0.8071297)10 into its octal number using repeated multiplication method. Find out the error in percent if all the octal digits after 4th position are dropped from the converted octal number.

Interger part Fraction part 0.8071297 ☐ 8 6 (MSD) .4570376
0.4570376☐ 8 3 .6563008
0.6563008☐ 8 5 .2504064
0.2504064☐ 8 2 .0032512
.0032512☐ 8 0 .0260096
.0260096☐ 8 0 .2080768
.2080768☐ 8 1 .6646144
.6646144☐ 8 5 .3169152
. . .
. . .
. . .

Therefore, (0.8071297)10 = (.63520015....)8.
If we keep only 4 octal digits in the result then the approximate result will be (.6325)8. To find out error we find the decimal equivalent value of (.6352)8.

The decimal value of (.6352)8
= 6 ☐ 8–1 + 3 ☐ 8–2 + 5 ☐ 8–3 + 2☐ 8–4
= (.80712890625)10

Error = (0.8071297)10 = (0.80712890625)10 = 0.79375 ☐ 10–6
%
Error
=
0.79375☐10-6 -4 0.8071297 ☐100 = 0.9834231☐10

when in a decimal number both integer and the fraction parts are present then for the conversion to an octal number the integer and fraction decimal parts are to be converted separately into octal then the two parts are to be written separated by the radix point.

2.2.4 Hexadecimal Number System

The hexadecimal number system is again a positional number system with radix 16 and therefore for this number system there are 16 digit symbols. The first ten digit symbols are identical to the decimal number system and the remaining 6 digits symbols are borrowed from the English capital alphabets. The complete set of digit symbols for the hexadecimal number system is {0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F}. The English alphabets represent the decimal values as follows A☐ 10, B☐ 11, C☐ 12, D☐ 13, E☐ 14 and F☐ 15. Following table (TABLE 2.3) shows the 16 decimal numbers and the corresponding hexadecimal numbers and the binary representation.

Decimal Hexadecimal Binary Equivalent

0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111

Table 2.3 : Hexadecimal numbers and their binary and decimal representation The positional weight for this number system is 16i for a digit di in the ith position of the integer part of the hexadecimal number counted left from the radix point.
•
(N)
16
= d
d ....d d d ☐ d d d ....d
☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐Radix ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐ ...(2.7) Integer part Point Fractional part
The positional weight of the hexadecimal digits both for the integer and fraction for the hexadecimal number shown in Equ (2.14) is shown in the TABLE 2.4.
16n-1 16n-2 .... 162 161 160 • 16-1 16-2 16-3 .... 16-m Positional Weight d n
-
1

d

n
-
2

....
d
2
d
1
d
☐
0 radix d-1 d-2 d-3 .... d-m Hexadecimal digitpoint
Table 2.4 : Positional weight for the hexadecimal digits of a number n integer digit and m digits on the fractional part.

The digital dn–1 which is furthest from the radix point on the integer part is called the most significant digit (MSD) and the digit d0 on the integer part which left-adjacent to the radix point is called the least significant digit (LSD) because their positional weight is largest and smallest respectively. Similarly, the digit d–1 and d–m on the fractional part are called the MSD and LSD respectively because of their positional weights are largest (16–1) and smallest (16–m) respectively.

All the methods applied to binary and octal number systems to compute the decimal equivalent value viceversa are also applicable to the hexadecimal number system.
2.2.4.1 Hexadecimal-to-Decimal Number Conversion
We can use following method to convert a hexadecimal number to its decimal equivalent value.
(i) Positional weighted sum of the hexadecimal digits : This method is equally applicable to both integer and fractional part.
Convert a hexadecimal number (B95C.A5)16 into its decimal equivalent value using weighted sum method.
The hexadecimal digits for the integer part are d0=C(=12), d1= 5, d2 = 9, d3=B(☐11) and for the fractional part the digits are d–1 = A(☐10), d–2 = 5.
Therefore, by summing the weighted value of the hex digits we get the decimal equivalent of the hex number as follows : (M)10 = d3 163 + d2162 + d1161 + d0160 + d–116–1 + d–216–2
☐163 + 9☐162 + 5☐161 + C☐160 + A☐16–1 + 5 ☐16–2= B
= (47452.644)10, substituting B = 11, C = 12, A = 10.

2.2.4.2 Decimal to Hexadecimal Number Conversion

For the conversion of decimal number to hexadecimal value we can follow the method of repeated division and multiplication as we did for the octal and binary numbers. Only difference is that in this case the division or the multiplication factor will be the radix of the hexadecimal number system which is 16. The repeated division and the repeated multiplication process is applied to the decimal integer and decimal fraction respectively. In this section we shall give some examples for illustrating the above two methods.

Convert a decimal number (51926)10 into its hexadecimal equivalent by repeated division method.

Quotient Remainder 51926/16 3245 6 (LSD) 3245/16 202 14 (E) 202/16 12 10 (A) 12/16 0 12 (B) (MSD) Therefore, (51926)10 = (BAE6)16
Convert (0.859)10 into its equivalent hexadecimal number using repeated multiplication method.

If the process is non terminating then what will be the minimum number of hexadecimal digits that are required in the converted hexadecimal number to allow maximum error of 0.002%?

Integer part Fraction part
0.859☐ 16 13(=D) MSD .744
0.744☐ 16 11(=B) .904
0.904☐ 16 14(=E) .464
0.464☐ 16 7(=E) .424
0.424☐ 16 6(=E) .784
0.784☐ 16 12(=C) .544
0.544☐ 16 8 (LSD) .704
. . .
. . .
. . .

Therefore, (0.859)10 = (0.DBE76C8...)16 and it is nonterminating. If 0.002% error is allowed in (0.859)10 then the amount of error is (0.00001718)10 Therefore, 16-n < 0.00001718 or, n☐4 Therefore, to allow 0.002% error in the converted number we may keep only 4 hexadecimal digits.
Thus, (0.859)10 = (0.DBE7)16 allows 0.002% error.

Note : If a number (N)r of the number system of radix r contains a block of identical digit ‘d’ either in the integer or fraction then we can follow the following method to calculate the decimal equivalent value (M)10 of (N)r without adding the weighted value of each digit of the block provided the digit position of the leading and trailing digit of the block is known irrespective of the length of the block.

Let the integer (NI)r containing a block of digit ‘d’ in the integer part is of the form p ......... q☐ digit position
(N
I
)
r
= 0 0 .....
d d d .......d 0 0 .....
☐☐☐☐☐☐☐☐☐☐☐☐☐
Block of
digit 'd'
The decimal value (MI)10 of this integer number (NI)r is (M
I
)
10
=
0 + 0 + .... d × r p–1 + ..... + d × rq + 0 + 0 + .....
☐
P + d × rp-1+ rp - rp-2+ .....+ rq + 1- rq☐
=
d
☐rp + 1 -rp + rp -r☐
☐ r-1 r-1 r-1 r-1 ☐ =
d☐
r-1☐rp + 1 - rq☐ ... ... (2.8)☐
=drp + 1 [1 – r–1] ; L = p – q + 1... ... (2.9)r-1
= Length of the block
Thus, the decimal value can be obtained by knowing the leading and trailing position of the block or the length L of the block and the repeating digit within the block. There may be more than one block of identical digit in (N)r. For this situation we have to apply the above rule for each block, separately.
Find out the decimal value of the octal number (N)8 = (05550066)8.
The digit position of the giver octal number is marked below : 7 6 5 4 3 2 1 0 ☐ digit position
(N)8 = 0 5 5 5 0 0 6 6 ☐ given number
Block-1 Block-2
For Block–1 : p1 = 6, q1 = 4, d1 = 5
Block–2 : p2 = 1, q2 = 0, d2 = 6
Therefore, the decimal value of (N)8 can be obtained using Eqm(2.15) as follows
d1 ☐ rp11 - rq1☐ ☐d 2 ☐rp21 - rq2☐(N)10 = ☐ ☐
☐ ☐ ☐ ☐
r - 1 ☐ ☐ r- 1 ☐ ☐
5
= ☐☐ 6 ☐82 - 80 ☐ = (1495094)107 ☐87 - 84 ☐ ☐7 ☐ ☐

Similar to the integer number if the fraction part (NF)rof any number (N)rof radix r contain a block of identical digit ‘d’ with digit position p and q for the leading and trailing position of the block as shown below.

P .... q ☐ digit position
(NF)r = 0.00.....Odd ... do
☐ given number
block
then the decimal value for this block can be found as follows
(MF)10 ☐d [r- -1) -r-q -r-L]... ...(2.10)r -1

Find the decimal value for the hexadecimal number
(NF)16 = (0.0AAA055)16
without using the addition of the weighted value of the individual digits.

The digit position of the given hexadecimal number is marked below.

1 2 3 4 5 6 7 ☐ digit position
.0 A A A 0 5 5 ☐ given hexadecimal digits
Block-1 Block-2

For Block–1 : p1 = 2, q1 = 4, d1 = A( =10)
Block–2 : p2 = 6, q2 = 7, d2 = 5
☐ The decimal value for the given hexadecimal fraction number is (M
F)10 = d1 ☐r-( p1 -1)- r-q1 ☐+ d2 [r-( p2 -1)- r-q
☐ ☐ 2 ]r -1 ☐ ☐ r -1
=10 [16-1 - 16-4 ] ☐5 [16-5 - 16-7 ]16 - 1 16 - 1
= 0.041658 + 85 ´ 10–7
= 0.046665.
Convert a binary number (110110011.01011)2 into octal number.
Make a group of 3 bits on the integer and the fractional part of the given binary number starting from the radix point and replace each 3-bit group by the corresponding octal digit. Additional leading os and trailing os are added to complete the 3 bit group.
(0–11) (011) (011) • (010) (110–) = (333.26)8
The added zeros have been underlined.
Convert a binary number (11011011010010101•1110000111)2 into its hexadecimal equivalent number.
Making the groups of 4 bits of the binary bits both on the integer and fractional part starting from radix point we get (0001)(1011) (0110) (1001) (0101) • (1110) (0001) (1100) ; extra 0s added to complete 4-Bit group are underlined.
Replacing each 4-bit group by its equivalent hexadigits we get (1B695.E1C)16
Find the equivalent binary number for the hexadecimal number (B25A.CD)16.
Replacing each hexadigit of the given number by their equivalent binary we get (B25A.CD)16 = (1011) (0010) (0101) (1010) ·(1100) (1101)
= (1011001001011010. 11001101)2

In general to convert a number N1 of radix r1 = 2n to another number N2 with radix r2 = 2m we have to replace each digit of the number N1 by its n bit binary code to get the binary equivalent of the number N1. After that make a group of m bits and replace each group by the digit symbol of the number system of radix r2 to get the number N2.

Convert the hexadecimal number (B2CF1)16 into an octal number.

(B2CF1)16
= [(1011)(0010) (1100) (1111)(0001)]2 ; the added 0 which is needed to = [(010) (110) (010) (110) (011) (110) (001)]2 ● make a group of 3 bits starting from least significant position.
= (2626361)8 ● underlined.

2.3 ARITHMETIC OPERATION WITH NON-DECIMAL NUMBERS

So far we have seen the Binary, Octal and Hexadecimal number system and their interrelationship. Now we shall see how the basic arithmetic operation like addition, subtraction and multiplication are performed using these numbers.

2.3.1 Binary Addition and Subtraction
(a) Binary Addition

In binary number system there

are only two digits ‘0’ and ‘I’ so

there may be four combinations

that may occur during addition.

These four combinations are

shown in Fig 2.1.

Fig 2.1: Addition of two1-bit numbersThe first three additions 0 + 0 =
0, 0 + 1 = 1, 1 + 0 = 1 are obvious. Here, ‘+’ symbol stands for the arithmetic addition but not the OR operation. The OR operations is a logical operation and it will be described later.

The arithmetic addition 1 + 1 generates 2 as the sum in decimal and in (10)2 in binary because 1 + 1 can’t be written using a single bit in binary but it requires two bits (10)2. The bit 1 of this sum (10)2 is called carry bit (c) and the bit 0 of (10)2 is the sum bit (s).

When we add more than 2 or more digits in any number system having radix r then in general the carry (c) after the addition of digits (assuming all the digits are decimal) means “How many times the sum of the digits has either become equal to the value of the radix r or has exceeded the value of the radix r during addition and the sum digit (s) in the difference between the added value of the digits in decimal and the carry(c) times the radix value r.

Another way of getting the carry(c) is to perform the integer division of the added value of the digits (assuming all the digits to be decimal) by the radix r of the number system. Thus, for d1, d2, d3 ....dn digits to be added.

Carry digit (c) = Int ☐(d1 ☐d2 + d3 ☐.....dn) ☐
☐r ☐
☐ ☐

Sum digit (s) = (d1 + d2 + d3 + ....+ dn) – (c).(r)
For binary number system r = 2 therefore,
for (i) 0 +0 we get d1 + d2 = 0

Carry bit (c) = Int [(0 + 0/2] = 0
Sum bit (s) = (0 + 0) – c.r. = 0
(ii) 0 + 1 we get d1 + d2 = 1
Carry bit (c) = Int[1/2] = 0
Sum bit (s) = 1 – c.r = 1
(iii) 1 + 0 we get d1 + d2 = 1
Carry bit (c) = Int[1/2] = 0
Sum bit (s) = 1 –c.r = 1
(iv) 1 + 1 we get d1 + d2 = 2
Carry bit (c) = Int [2/2] = 1
Sum bit (s) = 2 – c.r = 0
Another quick and simple way for finding the carry and sum bit for binary addition is as follows :
If there are n number of 1 bit present within the m bits to be added then the Sum bit(s) = 1 for n = odd
= 0 for n = even or n = 0

Carry(c) = For each pair of 1s within m bits one carry bit is generated i.e. total carry (in decimal) is equal to number of pair of 1s in the m bits. The decimal value of carry is to be written in binary on the left side of the sum-bit (s).

or
perform the integer division of sum of n bits by 2 to get the total carry (in decimal) generated out of this integer division.
Add the following
(i) (1 + 0 + 1 + 1 + 1 + 0 + 1)2
(ii) (1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1)2

(i) The total number of bits m = 7
The total number of 1-bit n = 5
Sum of n bits = 5
So, sum bits (S) = 1, as n is odd carry(C) = Int [n/2] = (2)D = (10)2
Therefore, (1 + 0 + 1 + 1 + 1 + 0 + 1)2 = CS = (101)2
Note : The numbers of pairs of 1-bit are 2
Therefore, C = (2)D = (10)2

(ii) The total number of bits m = 9
The total number of 1-bit n = 8
Sum of n bits = 8
So, Sum bit (S) = 0, as n is even Carry (C) = Int [n/2] = (4)D = (100)2
Therefore, (1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1)2 = CS = (1000)2.
Note : The numbers of pairs of 1-bit are 4
Therefore, C = (4)D = (100)2
Multibit Binary Addition Above rules of addition can also be applied when we add two or more binary numbers having more than one bit in each number i.e. i.e. bit binary numbers X = X2X1X0 and Y = Y2Y1Y0.

Fig 2.2 shows that when the bits X0 and Y0 having the same positional weight are added following the rules of addition of two one bit numbers (as shown in Fig 2.1), there will be a sum bit S0 (may be 0 or 1) and a carry bit C0 (may be 0 or 1). The sum bit S0 is written below the horizontal line. The positional weight of the sum bit S0 in 20. But the carry bit C0 produced due to this sum has positional weight of 21.

This carry bit C0 is written at the top of the next column

containing the bits X1 and Y1 with the positional weight 1
. We add C0 with X1 and Y1 in this column to produce
2

a sum S1(= C0 + X1 + Y1) and carry bit C1 which may be

either 0 or 1 but with positional weight 22. This carry bit

C1 is written at the top of the column containing the bits Fig 2.2: Addition of two 3-bit numbers X2 and Y2 for further addition with them to produce a sum bit S2 in this column and carry bit C2. The positional weight of S2 and C2 are 22 and 23. As there is no other bits in this leftmost column therefore, the carry bit C2 is treated as the most significant sum-bit S3 for this addition of two 3-bit numbers. This type of addition is called the Ripple Carry Addition as the carry generated in any column may ripple through the columns upto the last in worst case.

From the above example of addition of two multibit numbers it is observed that ith column containing two bits Xi and Yi may receive a carry coming from Ci–1 from the (i–1)th column for addition except the column i = 0 containing the bits X0 and Y0. The adder which has the facility to add three bits (Augend, Addend and the carry-input) is called a FullAdder (FA) and the adder which can add only two bits (Augend and Addend) is called a HalfAdder (HA). The truth table for the half-adder and a Full-adder is shown in the TABLE 2.5 (a) and 2.5 (b) respectively.

The algorithm for the addition of two n-bit binary numbers X and Y can be described as follows
Xi Yi Ci Si Xi Yi Ci –1 Ci Si 0 + 0 0 0 0 0 0 0 0
0 + 1 0 1 0 0 1 0 1
1 + 0 0 1 0 1 0 0 1
1 + 1 1 0 0 1 1 1 0
Table : 2.5(a) : Truth 1 0 0 0 1
table for Half-adder 1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Table : 2.5(b) : Truth table for Full-adder

Algorithm for binary addition using FullAdder i = 0, C–1 = 0
If Xi + Yi + Ci–1 < (2)D or (10)2 then Si = Xi + Yi + Ci –1

Ci = 0
else
Si = (Xi + Yi + Ci–1) – (2)D or (10)2
C1= 1
i = i + 1
Repeat until i = n –1
Cn–1 = Sn
Stop.

Above algorithm will be slightly modified if the two binary numbers contain fractional part also. If the two binary numbers contain n integer bits and m bits on the fractional part then the first line of the above algorithm should be replaced by i = –m, C–(m + 1)= 0 and replace the line Repeat until i = n –1 by Repeat until i = –1 keeping all other steps same.
Add (10011.111)2 with (11110.101)2

The arrowhead lines indicate a carry generated from one column after addition towards next column. This carry is placed at the top of the next column before addition of the next column. Assume C– 4 = 0.

Thus, (10011.111)2 + (11110.101)2 = (110010.100)2
Add (1010.11)2, (101.01)2, (1100.011)2 and (11101.101)2.
1 1 1 1 1
Carry bits generated from the 1 1 1 1 1 1 1 1 0 pair of 1s from the earlier columns X1 = 1 0 1 0 • 1 1

X2 = 1 0 1 • 0 1
Bits of the four numbersX3 = 1 1 0 0 •0 1 1
X4 = 1 1 1 0 1 • 1 0 1
S = 1 1 1 0 1 0 • 0 0 0

For each pair of 1s (including the carry bits and the bits of the number) in a column one carry is generated for the next column and for even and odd number of 1s (including the carry bits and the bits of the number in a column) the sum bit is 0 and 1 respectively in that column.

(b) Binary Subtraction

We can follow the same rule of decimal subtraction for binary subtraction. The subtraction of a binary bit Yi (subtrahend) from another bit Xi (minuend) results in a difference bit Di and a borrow bit Bi. The borrow bit is 0 if Xi ☐ Yi and the borrow bit is 1 when Xi < Yi. The TABLE 2.6 shows the four cases which may occur when we subtract a single bit from another single bit.

Difference
Xi Yi Di = Xi – Yi Borrow (Bi) 0 – 0 0 0
0 – 1 1 1
1 – 0 1 0
1 – 1 0 0
Table 2.6 : Rules for single bit subtraction Consider the case of subtraction of two 3-bit numbers Yi+2Yi+1Yi from Xi+2Xi+1Xi. In order to subtract Yi from Xi when Yi > Xi we need a borrow bit 1 from the minuend bit Xi +1of the adjacent higher significant column. Borrowing a bit 1 from Xi+1to Xiis equivalent to borrowing of a value 2i+1 because the positional weight of Xi+ 1 is 2i+1. This borrowed value of 2i+1 is added to the value of 2i Xi. Thus, the current value of the minuend Xi changes to 1 ☐ 2i+ 1 + Xi2i = (1Xi)2 as the modified minuend. We may now cancel the previous Xiand write (1Xi)2 for Xi after borrowing of 1. We know that this borrow is required when Xi = 0 and Yi= 1 and for this reason after borrowing, the bit Xi+1 is reduced by 1 and Xi changes to (10)2 from 0. Before borrowing the minuend bit Xi+1 may be 1 or 0.

(i) X i +1 = 1 before borrowing
For this situation Xi+1 becomes 0 after supplying a borrow bit 1 to Xi. The Xi becomes (10)2 from its initial value 0. Following is an example for such a case.
0 (10)2 ☐Modified minuend
X2X1X0 = 1 0 1☐ 1 0 1 ☐Initial minuend
☐
–Y2Y1Y0 = 0 1 0 0 1 0 ☐Subtrahend
D2D1D0 0 1 1 ☐ Difference For the above example, the least significant minuend bit X0 is greater than the least significant subtrahend bit Y0 and therefore no need of borrowing for X0 and the difference bit D0 = X0 – Y0 = 1 – 0 = 1.

For the next higher column X1= 0 and Y1= 1 and therefore X1 needs a borrow from X2= 1. This makes X1 = (10)2 and X2=0. We write modified minuends cancelling the initial minuend bits. The difference bits D1 and D2 are obtained as 1 and 0 respectively by subtracting the subtrahend from the modified minuend bits.

Sometimes we may need two level modification of the minuend bits as illustrated below. 0 10 ☐ 2ndlevel modification of minuend 1 0 10 ☐ 1st level of modification of minuend X3X2X1X0 = 1 1 0 1☐ 1 1 0 1 ☐ Initial minuend
–Y3Y2Y1Y0 = 0 1 1 0 0 1 1 0 ☐ Subtrahend
D3D2D1D0 = 0 1 1 1 ☐ Difference During first level of modification, the bit X2 becomes 0 from 1 as it supplies a borrow to X1. But this modified X2 is less than Y2. Therefore, a further borrowing is necessary for the modified X2 from the bit X3 which makes X3 = 0 and the X2 = (10)2 in the second level.

(ii) Xi+1= 0 before borrowing In this case the minuend Xi+1 itself needs a borrow of 1 from the position of Xi+2 when Xi+1 supplies a borrow to Xi. Therefore, after receiving a borrow from Xi+2, the minuend Xi+1becomes (10)2 and supplying a borrow to Xi it becomes (10)2 –1 = 1. Thus, we may use it as a rule that if any minuend bit is initially 0 then it will be changed to 1 provided it supplies 1 as a borrow to the next lower significant bit Xi. Similarly, if Xi+2 = 0 initially and supplies a borrow of 1 to Xi+1 then Xi+2 will be modified to 1 and also may modify Xi+3 etc. These changes of the minuend will progress to the left and stop in a column where if we find X = 0 and Y = 1 in a column next.

Following are some examples to illustrate the above rule. Like earlier case there may be multi level modification of the minuend bits.
Subtract (1011)2 from (10100)2.
0 10 0 1 10 ☐ modified minuend X4X3X2X1X0 = 1 0 1 0 0☐ 1 0 1 0 0 ☐ minuend
–Y3Y2Y1Y0 = 1 0 1 1 1 0 1 1 ☐ Subtrahend D3D2D1D0 = 1 0 0 1 ☐ Difference
Subtract (111010.101)2 from (1010101.010)2.

1 10
0 1/0 0/ 10 0 10 0 10 0 10 X6X5X4 X3 X2X1X0 • X–1X–2X–3 = 1 0 1 0 1 0 1 • 0 1 0 ☐ 1 0 1 0 1 0 1/ • 0 1 0
–Y5Y4 Y3 Y2Y1Y0 • Y–1Y–2Y–3 = 1 1 1 0 1 0 • 1 0 1 1 1 1 0 1 0 • 1 0 1 d6d5d4d3d2d1d0 • d–1d–2d–3 0 0 1 1 0 1 0 • 1 0 1

For this example we need second level of modification of the minuend because the minuend bit X4 in the first level changes to 0 from 1. But this modified X4 = 0 is less than subtrahend bit Y4 = 1 and therefore, it needs a borrow from X5. This borrowing changes X5 to 1 from 0 and X6 to 0 from 1.

2.3.2 Octal Addition and Subtraction
(a) Octal Addition

For octal number system the value of radix is 8. When the octal digits are added then the sum in decimal may exceed the value of the radix or may be equal to 8. This leads to an octal carry. The value of the octal carry digit may vary from 0 to 7. For example, if we add the octal digits 7,6,5 and 4 then the decimal sum will be 7 + 6 + 5 + 4 = (22)10. This sum has crossed the radix r = 8 twice. We know that the carry after addition in any radix system indicates how many times sum has become equal to the value of the radix or crossed the value of the radix. Therefore, for this particular example the carry digit C=2 and the sum digit S is equal to the balance of 6 which is obtained by subtracting 2 times of 8 i.e. 16 from the total sum 22. Thus, (7 + 6 + 5 + 4) = CS = (22)10 = (26)8. The easy way to find the carry is to find the integer value after dividing the total sum N of the octal numbers by 8 i.e. carry = Int(N/8) = n and the sum digit is S = N–n8.

Add the two numbers (3676)8 with (4762)8 and explain each step of addition.

C3 = 1 C2 = 1 C1 = 0 C0 = 1 C-1 = 0 X3X2X1X0 = 3 6 7 6 Y3Y2Y1Y0 = 4 7 6 2 S4S3S2S1S0 (1 0 6 6 0)8

Assume carry C–1 = 0 for the last significant column. (i) X0 + Y0 + C–1= 6 + 2 + 0 = 8
C0 = Int (8/8) = 1
S0= 8 – 8 ☐ 1 = 0
(ii) X1 + Y1 + C0 = 7 + 6 + 1 = 14
C1 = Int(14/8) = 1
S1 = 14 – 8 ☐ 1 = 16
(iii) X2 + Y2 + C1 = 6 + 7 + 1 = 14
C2 = Int(14/8) = 1
S2 = 14 – 8 ☐1= 6
(iv) X3 + Y3 + C2 = 3 + 4 + 1 = 8
C3 = Int(8/8) = 1
S3 = 8 – 8 ☐ 1 = 0
(v) S4 = C3 = 1

Add (5610.56)8, (2345.07)8 and (23.64)8.

1 1 1 1 2 0 ☐ carry generated from the lower
5 6 1 0 • 5 6 significant column assuming
2 3 4 5 • 0 7 the carry for the least significant 2 3 • 6 4 column to be 0. All the carries (1 0 2 0 1 • 5 1)8 are underlined.

(b) Octal Subtraction
The subtraction of one octal digit from another follows the same rule of binary subtraction. Only difference is that the radix in 8 instead of 2.
There may be following 3 cases during subtraction. If X and Y are the minuend and subtrahend in any column then Case (i) The minuend (X) > the subtrahend (Y)
Case (ii) The minuend (X) = the subtrahend (Y)
Case (iii) The minuend (X) < the subtrahend (Y) For the case (i) and (ii) no borrow digit is required. The difference is computed just like two decimal numbers.

X = X2 X1 X0
Y = Y2 Y1 Y0
d2 d1 d0

But for case (iii) a borrow digit is needed. To explain the action of borrowing we consider two 3-digit octal numbers X and Y for subtraction. When X0 < Y0 then borrow digit 1 is required for X0 with positional weight 80 from next higher significant column containing the octal digit X1 with positional 81. Thus, the borrow digit from X1 mean a valued 1 ☐ 81 and this borrow is added with a value X0 80 to become 1☐ 81 + X0 = (1X0)8. This is the modified octal minuend replacing the initial digit X0. But the octal digit X1 is reduced by 1. The difference digit d0 = (1 X0)8 – Y0. If X1 is initially 0, then X1 can’t supply a borrow to X0. Therefore, needs a borrow digit of 1 for itself from X2 which reduces X2 by 1 but X1 is modified to (10)8 before supplying a borrow to X0 and finally it X1 is reduced to (10)8 – (1)8 = 7 after supplying a borrow to X0 and X0 is changed (1X0)8.

The above process is continued upto the last digit of the minuend whenever X1 < Y1 is found in any ith column. Sometimes, the 2nd level of modification is also required if the modified minuend is found to be smaller than subtrahend digit in any column.

Add (615)8, (2345.07)8 from (704).

6 7 (14)8 ☐ modified minuend X2X1X0 = 7 0 4 ☐ minuend Y2Y1Y0 = 6 1 5 ☐ subtrahend d2d1d0 = 0 6 7 ☐ difference in octal In this example X0 < Y0. So, X0 is modified to (1 X0) = (14)8 and X1 is changed to (7)8. The difference digit d0 = (14)8–(5)8= (12 – 5)10= 7

As X1 was initially 0 therefore it need a borrow digit from X2 before supplying a borrow of 1 to X0. Therefore, X1 is changed to 7 and X2 is reduced by 1. The difference digits d1 and d2 are 7 – 1 = 6 and 6 – 6 = 0 respectively.

Subtract (546.12)8 from (633.01)8

5 (13)8 2 7 (11)8 (12)8 (12)8 ☐ modified minuend X2X1X0•X–1X–2 = 6 3 3/ • 0 1☐ 5 (1/3)8 2 • 7 (11)8 ☐ minuend Y2Y1Y0•Y–1Y–2 = 5 4 6 • 1 2 5 4 6 • 1 2 ☐ subtrahend d2d1d0 • d–1d–2 0 6 4 • 6 7 ☐ difference in octal Here (11)8 = (9)10 ; (12)8 = (10)10.

In this example we need two level of modification of the minuend. In the first level of modification the minuend X0 is reduced to 2 from 3 as it supplies, a borrow to X–1. But this modified X0 is still less than Y0 = 6 and for this reason it needs further borrowing from the first level modified X1 = (13)8 which reduces X1 by 1 and the new value become (12)n.

2.3.3 Hexadecimal Addition and Subtraction
(a) Hexadecimal Addition

For the addition of hex digits we can follow the same steps as we followed in case of octal and binary numbers. To get the sum and carry digit after the addition of the hex digits one has to add the decimal equivalent value and then has to divide the added value (N) of the hex digits by the radix r = 16 using integer division. Thus, the carry (C) = Int [d1 + d2 + ....dn)/16] = Int (N/ 16). The sum digit (S) = N – 16.C where d1, d2,.....dn are the hex digits.

Add the hexadecimal numbers E8E5, EFAB and 5F7A.
The above addition process can be explained as follows (i) C0= Int[(5 + B + A)/16] = Int (26/16) = 1

S0 = 26 – C0 16 = 10 = A
(ii) C1= Int [(E + A + 7 + C0)/16] = Int (32/16) = 2
S1 = 32 – C1 16 = 32 – 32 = 0
(iii) C2= Int [(8 + F + F + C1)/16] = Int (40/16) = 2
S2 = 40 – C2 16 = 40 – 32 = 8
(iv) C3= Int [(E + E + 5 + C2)/16] = Int (35/16) = 2
S3 = 35 – C3 16 = 35 – 32 = 3
(v) S4 = C3 = 2

(b) Hexadecimal Subtraction

Like the binary and octal number system three cases may arise while we subtract one hex number Y from another hex number X. During subtraction in the ith column the following three cases may occur.

Case (i) Xi > Yi
Case (ii) Xi = Yi
Case (iii) Xi < Yi For the first two cases no borrow is required and we can get the difference digit di = Xi–Yi assuming the decimal equivalent of the hex digits. But for the case (iii) a borrow digit is required. To understand the effect of borrowing we consider only three columns of two n bit hexadecimal numbers X and Y as shown. If Xi < Yi

then we need a borrow digit 1 from the minuend digit Xi+ 1.

This borrowing of 1 from the (i + 1)th column is equivalent to

borrowing of 16i+1. Thus, when this borrow is added with Xi

then the modified value of Xi becomes 16i+1☐1 + 16i Xi = (1Xi)16

and the value of Xi+1 digit will be reduced by 1 from its initial value.

If the initial value of Xi+ 1 is 1 then it becomes 0 after supplying borrow digit to Xi. But for initial value of Xi+1 = 0, the Xi+1 needs a borrow digit from Xi+2 to increase its value to (10)16 before it supplies a borrow digit to Xi from Xi+1. Therefore, the value of Xi+1 will be modified again from (10)2 to (10)2 – (1)16 = 15 = F. We can see that if any minuend digit Xi+1 with initial value 0 needs to supply a borrow digit to the next adjacent lower significant digit then the modified value of Xi+1 will be F (in general it becomes r – 1). The process of modification of minuend may require to be continued to the last column of the minuend whenever in any column Xi < Yi is found. This is the 1st level of modification of the minuend. Even after the 1st level of modification of the minuend digits if in any column Xi < Yi is found then 2nd level of modification of minuend digits have to be done.

Subtract (6 ABC. 5D)16 from (701A. 6A).

6 (10)16 0 (1A)16 5 (1A)16 F (10)16
7 0 1 A • 6 A☐ 6 (1/0)16 0 (1/A)16 • 5 (1A)16
6 A B C • 5 D 6 A B C • 5 D 0 5 5 E • 0 D This example needs two level modifications of the minuend digit. After first level of modification it is found that the minuend digit 0 is less than the subtrahend digit B therefore the 2nd level modification is required.
2.3.4 Multiplication of Unsigned Binary Numbers
Multiplication of two 1 bit binary numbers follows the rule of ANDing of two 1-bit number as it is evidend from the TABLE 2.7.

Next consider the two 2-bit binary number A =

aia0and B = b1b0 as multiplicand and the multiplier

respectively. The bits a1, a0, b1 and b0 can have

values either 0 or 1.

The product A☐B after multiplication can be written as

P = A ☐ B = (a1a0)2☐(b1b0)2
= (21a1 + 20a0)☐(21b1 + 20b0) = 22a1b1 + 21(a1b0 + a0b1) + 20a0b0

= 22p11+ 21(p10 + p01) + 20p00
= (P3 P2 P1 P0)2

where p00= a0b0, p01= a0b1, p10= a1b0 and p11= a1b1 are called the partial product bits and P3
P2, P1 and P0 are bits of the final product P. The product bit P0= p00, P1= sum of p10 and p01, P2
is the sum of p11 and a carry generated, if any, due to the sum of p10 and p01 and P3 = the carry bit generated due to the sum of p11 and the carry bit due to the addition of p10 and p01. The product bits P0, P1, P2 and P3 have the positional weight 20, 21, 22 and 23 respectively. The result of the multiplication p = (a1a0)☐ (b1b0) can be obtained using the procedure which we learned in our school to multiply the multi digit number. This method is commonly called paper and pencil method.

The multiplication by paper and pencil method can be used for binary numbers in two ways.
(i) starting with least significant bit of the multiplier.
(ii) starting with the most significant bit of the multiplier.

(i) Multiplication starting with L.S.B of the multiplier bits

Let us consider two 2-bit binary numbers A = (a1a0) and B = (b1b0)2 for mutliplication using the paper and pencil method. The bit a1 and b1 both have the positional weight of 21 and a0 and b0 both have the positional weight of 20.

The final product bits P0, P1, P2 and P3 of P = A☐B are
P0 = a0b0 with positional weight of 20
P1 = sum of a1b0 and a0b1, both with positional weight 21.
P2 = sum of a1b1 and any carry Ci generated when a1b0 and a0b1 are added.

P3= Any carry bit C2 generated while computing p2= Ci + a1b1. The positional weight of C2 is 23.

If there are m bits in multiplier and n bits in the multiplicand then the total number of partial product will be equal to m and the maximum number of bits in the final product will be (m + n). As we are dealing with the binary numbers therefore the bits of the partial product will be either all zero if the multiplier bit is zero or will be identical to multiplicand if the multiplier bit is 1.

Multiply (10111)2 by (1011)2 using paper and pencil method.
A = a4a3a2a1a0 = 1 0 1 1 1
B = b3 b2 b1 b0 = 1 0 1 1

1 0 1 1 1 ☐ 1st p.p.
1 0 1 1 1 ☐ 2nd p.p.
0 0 0 0 0 ☐ 3rd p.p.
1 0 1 1 1 ☐ 4thp.p.
P = 1 1 1 1 1 1 0 1 ☐ (p7 p6 p5 p4 p3 p2 p1 p0) In this example there are 4 partial products p.p and there are 4 bits in the multiplier and 8 bits in the final product bits p0 to p7.
Multiply (101.01)2 by (111.10)2.

In this multiplication the partial products will be found ignoring the binary points of the multiplier and multiplicand. The binary point is placed in the final product P at

a position counting from l.s.b equal to the sum of the number bits present on the right side of the binary point in multiplier and multiplicand. In this case this sum is 2 + 2 = 4.

A = 1 0 1 • 0 1
B = 1 1 1 • 1 0
0 0 0 0 0
1 0 1 0 1
1 0 1 0 1
1 0 1 0 1
1 0 1 0 1
P = A☐ B = 1 0 0 1 1 1• 0 1 1 0
(ii) Multiplication starting with M.S.B of the multiplier bits
Example for the multiplication with MSB of the multiplied bits:

Multiply 10111 by 1011. A = 10111 and B = 1011

A = 1 0 1 1 1 = a4a3a2a1a0
B = 1 0 1 1 = b3 b2 b1 b0 =

1 0 1 1 1 ☐p3 = Ab3
0 0 0 0 ☐p2 = Ab2
1 0 1 1 1 ☐p1 = Ab1
1 0 1 1 1 ☐p2 = Ab0
P =A☐B = 1 1 1 1 1 1 1 0 1

2.4 SIGNED NUMBER REPRESENTATION

So far we have seen only the positive numbers in the different number system and the different arithmetic operations with those positive numbers. In this section we shall see how to represent to negative number in different number systems. In our everyday business when we do the arithmetic operations, we put a negative sign(–) preceding the most significant digit to represent a negative number and a plus sign (+) preceding the most significant digit to represent a positive number. But this symbolic representation is not possible in computer but we need a code for the symbols of two sings (+) and (–). As there are two symbols therefore we need a single digit code. There are other methods also to represent a negative number.

2.4.1 Sign-Magnitude Representation

In this representation an independent single digit is used along with true magnitude of the number to indicate the sign of the number. The sign code is appended at the front of the magnitude of the number. This representation is known as Sign Magnitude Representation. The digit code “0” is used for positive sign (+) and (“r –1”) is used for the negative sign(–) where r is the radix of the number system.

Let [Nr]Sm is the sign magnitude representation of a negative number whose magnitude is (Nr) then the sign magnitude representation
[Nr]Sm = (r–1) (N)r
= (r–1) [dn–2 dn–3 ....d0 • d–1 d–2 ....d–m]r ...(2.12) In the Eqn. 2.12, the extra digit of value (r–1) in the most significant positions represents the negative sign(–). Therefore, including this extra sign digit the total number of digits of the integer part of the number is n. Out of the n digits of the integer part, the digit d0 through dn– 2 represent the magnitude of the integer part and the digits d–1 through d–m represent the fractional part of the number (N)r.

For a positive number, the sign digit is 0 and is used on the left of the most significant magnitude digit and the remaining digits represents the magnitude of the number. Thus,the sign magnitude representation [Nr]Sm for a positive number Nr is [Nr]Sm = 0 (N)r
= 0 [dn–2 dn–3 ....d1 d0 • d–1 d–2 ....d–m] ...(2.13) From Eqn.2.12 and 2.13 it appears that the largest value of magnitude part can be obtained whenall the digit dn–2 = dn–3 = .... = d0 = d–1 = ....d–n are (r–1). On the otherhand when all the digits are all 0s then the sign magnitude representation gives +0 from Eqn 2.13 and –0 from Eqn.2.12. Thus we have two representations of the digit 0 which is a drawback of the sign magnitude form. For example, in case of 8 bit binary number (one sign bit and 7 magnitude bits) the largest positive and negative representation are (0) [1111111] and (1) [1111 111] respectively. The decimal equivalent values of these two largest number are + (28–1–1) = + 127 and – (28–1–1) = – 127 respectively. In general for an n-bit binary number (one sign bit and (n– 1) magnitude bits) the upper bound in the positive direction is + (2n–1 –1) and in the negative direction the upper bound is –(2–n–1 –1).

Write the 8 bit sign magnitude representation of a binary number whose magnitude is 110 1101.
(i) The positive sign magnitude representation is
(ii) The negative sign magnitude representation is
Write the positive and negative representation of an octal number whose magnitude is (562)8.
(i) The positive sign magnitude representation is
(ii) The negative sign magnitude representation is
Write the positive and negative representation of hexadecimal number whose magnitude is (AB2C)16.

(i) The positive sign-magnitude representation is
(0) (AB2C)16 = (0AB2C)16
(ii) The negative sign magnitude representation is
(r–1) (AB2C)16 = (FAB2C)16

Write the following numbers using 6-bit sign magnitude form in binary. (a) (25)10 (b) (–25)10 (c) (12)10 (d) (–8)10
Translate the magnitudes of each number into 5 bit binary, writing extra leading zeros as required, and set the sign bit to 0 for a positive number and 1 for a negative number. (a) (0) (11001)2 (b) (1) (11001)2 (c) (0) (01100)2 (d) (1) (01000)2 = (011001)2 = (111001)2 = (001100)2 = (101000)22
2.5 SIGNED MULTIPLICATION

The simple scheme for multiplication of two unsigned numbers can’t be applied to multiply two signed numbers. For example consider two binary numbers A = (1110)2 and B = (0110)2. If these two numbers are considered to be insigned then the product A☐B will be A☐B = (1110)2☐ (0110)2
= (14☐ 6)D = (84)D = (1010100)2
On the otherhand if the two numbers are considered in sign-magnitude from then the two numbers become
A = (1 110)2 = –6 and B = (0 110)2 = + 6; sign-digit underlined and P = A☐ B = (1 110)2☐ (0 110)2
= (–6)☐ (+6) = (–36)D = (1 100100)2

The multiplication of two binary numbers with negative sign should be treated in a different way. The process will be described below. The multiplication of two binary numbers (the numbers may be either both positive or negative or one of them may be positive and the other may be negative) becomes much more easier and less time consuming if the multiplier contains a block of 1s. This is explained below.

Let the multiplicand A and the multiplier B contains n and m number of digits as shown below (assuming they are integers) A = an–1 an–2 .... a1 a0
B = bm–1 bm–2 .... b1 b0

and they are assumed to be positive. To illustrate the effect of presence of block of 1s we assume a specific value 011 .....110....0011 for the mutliplier B as shown
B = bm–1 bm–2 bm–3 .... bi+1 bi bi–1 .... b2 b1 b0 0 1 1 .... 1 1 0 .... 0 1 1
This multiplier has two blocks of 1s (underlined) starting from bit position bito bm–2 and at b0 and b1. The product P = A☐ B can be evaluated as follows
P = A☐ B
= A[(0☐ 2m–1 + 1 ☐ 2m–2 + 1 = 2m–3+ ....1 ☐ 2i+1 + 1 ☐ 2i) + ....

+ (0 ☐ 2i–1 + .....+ 0 ☐ 22) + (1 ☐ 21 + 1☐ 20)]
= A[(2m–2 + 2m–3 +......+ 2i) + (21 + 20)]
= A (2m+1 – 2i) + A(22 – 20) In general, if the multiplier has a block of 1s of length L starting from bit position p to q where p > q and the remaining bits as 0s then
P = A☐ B = A (2p+1 – 2q) ignoring all 0s of the multiplier. Therefore, one block of 1s can be replaced by a single subtraction of A2q and one addition of A2p+1. Thus, each block of 1s of length L leads to two partial products instead of L number of partial products (one partial product per 1 of the multiplier) as we did in case of Left-shift and Add or Right-shift-and-Add method. The subtraction of A2q can be avoided by replacing the subtraction operation by the addition of 2s complement of the multiplicand A after a left shift by q number of bit positions. The multiplicand A and the 2’s complement of A should be sign-extended upto operation by (m+n) bits where m and n are the number of bits of the multiplicand and the multiplier.

The above stated process is also valid for situations when there are more than one block of 1s in the multiplier B. The beginning and the end of a block of 1s in the string block of 1s. For example, the multiplier 12 11 10 9 8 7 6 5 4 3 2 1 0 ☐ Bit position
B = 0 0 1 1 1 1 0 1 1 0 0 1 0 ☐ multiplier

has three blocks of 1s (shown underlined) of different length L1= 1, L2= 2 and L3 = 4 with different bit position p and q as stated below (i) L1 = 1, p1 = q1 = 1 ; block 1
(ii) L2 = 2, p2 = 5, q2 = 4 ; block 2
(iii) L3 = 4, p3 = 10, q3 = 7 ; block 3
Therefore, the product P = A☐B equals to
P = A☐B = A [(2p3+1 – 2q3) + (2p2+ 1 – 2q2) + (2p1+ 1 – 2q1)]
= A(211 – 27) + A(26 – 24) + A(22 – 21) This process of the multiplication A ☐ B needs only 3 additions and 3 subtractions (or there 2s complement additions) instead of one addition per 1 of the multiplier. Therefore, the number of additions and subtractions decreases as the number of block of 1s and the number of 1s per block increases.

It will be shown using a few examples. In the final product P we have to consider only (m+n) number of bits discarding all other higher order bits. The (m + n)th bit of the product determines the sign of the product P. If the (m + n) th bit is 1, then the product P = A☐B is negative and to get the magnitude of the product for this case we have to find the 2’s complement on the product bits. If the total number of bits of the partial product is less than (m+n) then the partial product should be sign extended up to (m+n) number of bits.

Find the product P = 29 ☐ 23

The multiplicand A = +29 = 0 11101 ;n = 6 including sign digit 0 The multiplier B = +23 = 0 10111 ; m = 6 including sign digit 0. 2’s complement representaion of (–A) = –29 = 1 00011

P = A ☐ B = 29 ☐ 23 = (0 11101)☐ (0 1 0 111); block of 1s of B underlined = (0 11101) [(25–24) + (23 – 20)
= p1 + p2 + p3 + p4

where p1 = A25, p2 = –A24, p3 = A23 and p4 = –A20.

For the partial products p1, p2, p3 and p4 we shall always try to keep only (m+n) = 6+6 = 12 bits discarding all higher order bits in the partial products and in the sum of the partial products to get the final product P = A☐ B.

p1 = A25 = 0 (0 1 1 1 0 1) 0 0 0 0 0
p2 = –A24 = 1 1 (1 0 0 0 1 1) 0 0 0 0
p3 = A23 = 0 0 0 (0 1 1 1 0 1) 0 0 0
p4 = –A20 = 1 1 1 1 1 1 (1 0 0 0 1 1) p1 + p2 + p3 + p4 = 0 0 1 0 1 0 0 1 1 0 1 1 = + 667 in decimal. ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐
12 bits In each of the above partial products the multiplicand and the 2s complement of the multicand are kept within brackets, the shifted-in 0 bits are underlined and the sign-extended bits are shown without any underlines.

Multiply 15 by 14

The multiplicand A = +15 = 0 1111 ; n = 5 including sign digit 0 (underlined) The multiplier B = +14 = 0 1110 ; m = 5 including sign digit 0 (underlined) The 2s complement representation of (–A) = 1 0001
P = A☐ B = 15 ☐14 = (0 1 1 1 1) ☐ (0 1110) = (0 1 1 1 1) ☐ (24 - 21) = p1 + p2
where p1 = A24 and p2 = –A21.

For the partial product p1 we shall always try to keep m + n = 10 bits discarding the higher order bits in the partial products and also in the sum of the partial products to get the final product P = A☐ B.

p1 = A24 = 0 (0 1 1 1 1) 0 0 0 0
p2 = –A21 = 1 1 1 1 (1 0 0 0 1) 0
p = p1 + p2 = 0 0 1 1 0 1 0 0 1 0 = +210 in decimal ☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐☐
10 bits In the above examples we considered positive sign both for multiplier and multiplicand. But the multiplicand and multiplier may be both negative or one may be negative and the other may be positive. The negative number is to be expressed in the 2’s complement form. For the 2’s complement form of the negative multiplier there may be 2 cases.

Case (i) : There may be a block of 1s from bit position q to p (p > q) and the bit position p is not equal to the bit position of the m.s.b. of the 2’s complemented form of the negative multiplier i.e. there is at least one 0 between the m.s.b. and the bit position p. The m.s.b of the 2s complemented form is always 1 with positional weight –2n–1 if there are n digits in the 2s complemented form.

For example, if the 2s complement of the negative multiplier is of the form. p2 .........q2 p1 .....q1☐ bit position B = Xn–10 0 .... 0 1 1 ...1 1 0 0 .... 0 1 .... 1 1 were Xn–1 = 1 then we may write for the value of B as (Xn–1 = 1)
B = –2n–1☐ 1 + 2n–2☐ 0 + ......+ 2p2+1☐ 0 + (2p2☐ 1 + 2p2–1☐ 1 + ....+ 2q2☐ 1) + 2q2–1☐ 0 ..... + 2p1+ 1☐ 0 + (2p1☐ 1 + 2p1–1☐ 1 + .....+ 2q1☐ 1)
= –2n–1 + (2p2 + .....+ 2q2) + (2p1 +......+2q1)
= –2n–1 + (2p2+ 1 – 2q2) + (2p1+ 1 – 2q1)
For example, 2s complement
(i) B = (–25)10 ________☐
2s complement
(ii)B = (–79)10 ________☐

5 4 3 2 1 0 ☐ Bit position
1 0 0 1 1 1 = –25 + (23 – 20)
7 6 5 4 3 2 1 0☐ Bit position
1 0 1 1 1 0 1 0 = –27 + (26 – 23) + (22–21) Case (ii) : The block of 1s in the 2’s complemented form is from the bit position q to p (p>q) but the block of 1s starts from the bit position next to the m.s.b. Xn–1 which is also 1 i.e. p = n–2. In general if the 2’s complement of the negative multiplier is of the form p2 = n–2 .....q2 = i p1 q1 ☐ Bit position B = Xn–1 1 1 ....1 1 0 0 .... 0 1 1... 1 0 .... ; Xn–1 = 1
which can be evaluated as follows B = –2n–1 + (1☐2n–2 + 1 ☐ 2n–1 + ....+ 1☐2i +1 + 1☐2i) + 0 ☐ 2i+1 + ....+ 0 ☐ 2p1+1 + (1☐2p + ....+ 1☐2q1) +
= –2n–1 + (2n–1 – 2i) + (2p1+1 – 2q1)
= –2i + (2p1+1 – 2q1) Thus, the block of 1s from the position Xi+1 to Xn–1 do not contribute anything for the evaluation of the value of B. The bit at the ith position is 1 which determines the sign. Therefore, the bits Xi+1 to Xn–1 may be called the sign extension bits. For example, 7 6 5 4 3 2 1 0 ☐ Bit position
2s complement

(i) B = (–99)10________☐ 1 0 0 1 1 1 0 1 ; bit 7 is the sign bit = –27 + (25– 22) + (21 – 20)
If B is written using sign extended bits as B = 1 1 1 (1 0 0 1 1 1 0 1) then we may write
= –210 + (210–27) + (25–22) + (21– 20)
= –27 + (25– 22) + (21–20) = (1) 0 0 1 1 1 0 1

Thus, we may write
B = –99 = (10011101)2 = (11110011101)2
5 4 3 2 1 0☐ Bit position
2s complement
(ii) B = (–18)10 ________☐ 1 0 1 1 1 0 ; bit 5 is the sign bit = –25 + (24–21)
Sign extended form of (–18)10 using four sign extension bits may be written as 9 8 7 6 5 4 3 2 1 0 ☐ Bit position
B = 1 1 1 1 1 0 1 1 1 0 ; bit 9 is the sign bit = –29 + (29– 25) + (24 – 21)
= –25 + (24– 21) = (1) 0 1 1 1 0
Thus, B = (–18)10 = (101110)2 = (1111101110)2

Multiply (i) 12 ☐ (–7) (ii) (–12)☐ 7 and (iii) (–12)☐ (–7)
(i) P = 12 ☐ (–7)
The multiplier B = (–7) in 2s complement form = 1 0 0 1 ; m = 4

☐ B = –23 + (21 – 20)
The multiplicand A = +12 = 0 1 1 0 0 ; n = 5
Sign extended (upto m + n = 9 bits) multiplicand A and –A are A = +12 = 0 0 0 0 (0 1 1 0 0) ; sign extended form of (+A)
–A = –12 = 1 1 1 1 (1 0 1 0 0) ; sign extended 2’s complemented form of (–A) Therefore, P = 12 ☐ (–7) = 12 (–23 + 21 – 20)
= –12 ☐ 23 + 12 ☐ 21 – 12 ☐ 20
= p1 + p2 + p3

where p1= –12☐ 23, p2 = 12 ☐ 21 and p3 = –12 ☐ 20
p1= –12☐ 23= 1 (1 0 1 0 0) 0 0 0 ; shifted-in underlined due to multiplication of 23 p2= 12 ☐ 21 = 0 0 0 (0 1 1 0 0) 0 ; shifted in underlined due to multiplication of 21 p3= –12 ☐ 20= 1 1 1 1 (1 0 1 0 0 ; no shifted in bits due to multiplication of 20 P = p1 + p2 + p3 = 1 1 0 1 0 1 1 0 0

9 bits
The 9th bit is 1 which indicates that P = A☐ B is negative. Find 2’s complement of P again to get the magnitude of P.
2s complement 1 1 0 1 0 1 1 0 0 ________☐ 0 0 1 0 1 0 1 0 0 = (84)10 Thus, P = 12 ☐ (–7) = (–84)10
(ii) P = (–12)☐ 7
The multiplier B = +7= 01 1 1= 23 – 20 ; m = 4
The multiplicand A = –12 in 2’s complement form 10 1 0 0 ; n = 5

Sign extended (upto m + n = 9 bits) multiplicand A and –A are
A = +12 = 0 0 0 0(0 1 1 0 0)
–A = –12 =1 1 1 1 (10 1 0 0)
Therefore, P = (–12)☐ (7) = –12 ☐ (23 – 20)
= –12 ☐ 23 + 12 ☐ 20 = p1 + p2 where p1 = –12 ☐ 23 and p2 = 12 ☐ 20
p1 = –12 ☐ 23 = 1 (1 0 1 0 0) 0 0 0 ; shifted-in bits underlined due to the multiplication by 23
p0 = 00 0 0 (0 1 1 0 0) ; no shifted-in bits due to multiplication by2 = +12 ☐ 2
20.
P = p1 + p2 = 1 1 0 1 0 1 1 0 0

9 bits
The m.s.b of P is 1. This indicates that P is negative. To get the magnitude of P find 2’s complement of P.2s complement P = 1 1 0 1 0 1 1 0 0 ________☐ 0 0 1 0 1 0 1 0 0 = 84 Thus, P = (–12) ☐ 7 = – 84 in decimal.
(iii) P = (–12)☐ (–7)
The multiplier B = –7 in 2s complement form = 1 0 0 1(= –23 + 21 –20); m = 4 The multiplier A = –12 in 2s complement form = 1 0 1 0 0 ; n = 5 Sign extended (upto m + n = 9 bits) multiplicand A and –A are A = +12 = 0 0 0 0 (0 1 1 0 0)
–A= –12 = 1 1 1 1 (1 0 1 0 0)

Therefore, P = (–12) ☐ (–7) = –12☐ (–23 + 21– 20)
= +12 ☐ 23 – 12 ☐ 21 + 12 ☐ 20 = p1 + p2 + p3
where p1 = 12 ☐ 23 , p2 = –12 ☐ 21 and p3 = 12 ☐ 20.
p1 = –12 ☐ 23 = 0 (0 1 1 0 0) 0 0 0 ; shifted-in bits underlined p2 = –12 ☐ 21 = 11 1 (1 0 1 0 0) 0 ; shifted-in bits underlined p3 = –12 ☐ 20 = 00 0 0 (0 1 1 0 0) ; no shifted-in bits
0 0 1 0 1 0 1 0 0 = 84 ; The m.s.b is 0. This indicates positive product P.
9 bits
Thus, P = (–12)☐ (–7) = + 84 in decimal.
2.5.1 Computer Codes Coding of information is a process of specifying numberic, alphabetic and different symbols used in the program instruction other symbols understandable by the logic circuits. As the logic circuits can understand only the binary bits 1 to 0, therefore the binary bits are generally used for any coding purpose. Various types of codes are used to represent information

(including both data and programmes) in binary form for the purpose of storage in memory, processing and communications. In this section we shall see some of the most popular and widely used codes.

BCD Additions of two Negative BCD numbers
To add two negative numbers X and Y using BCD notation, the 10s complement of the two negative numbers are computed in the first step. The sign digit is assumed to be 1 to indicate the negative sign. These two 10s complemented numbers are added using binary rules in the second step. After the addition if any 4-Bit group from the right end is found to be greater than 1001 or produces a carry to the next higher 4-Bit group then BCD correction is applied to that 4-Bit group in the third step. After the BCD correction if EC☐ C = 0 is satisfied with sign-bit = 1 then the BCD sum is correct and negative. In the last step a further 10s complement operation is to be performed to get the magnitude of the negative sum.

If underflow occurs i.e. if EC☐C=1 then the sign of the BCD sum of two negative numbers becomes positive. It means that the sum of two N-digit BCD numbers can’t be expressed using only N digit BCD. Therefore, to avoid this problem of underflow an additional digit 0 is to be placed at the most significant position of each negative number before finding the 10s complement.

Add –2 with –3 using BCD notation.
10s complement
X = –2 ________☐ (1) 1 010s complement
Y = –3 ________☐ (1) 0 1 1 (0) 1 1 0 1 1 (1) 0 1
EC =1 C = 1 0 1

Therefore, –2 +(–3) = –(0101)BCD = –5

0 0
1 1
1 1
1 0
0 1 ; Sum > 9
; BCD correction
; no-overflow (EC☐C = 0) ; sign negative

0 1
Add –6 with –8 using BCD notation.
10s complement X = –6 ________☐ (1) 0 110s complement
Y = –8 ________☐ (1) 0 0
0 1

EC = 1 C = 0
0 0
1 0
1 0 ; 10s complement of 0101

; Sum < 9 but positive
; due to underflow (EC☐C=1) To avoid this underflow, we have to use –06 and –08 for –6 and –8 before the 10s complement operation.
10s complement
X = –06________☐ (1) 1001 0100
10s complement
Y = –08________☐ (1) 1001 0010
(1) (1) 0010 0110 ; Sum is negative, a carry is produced from ; the upper nibble to the sign-bit. So this EC= 1 C = 1 ; nibble needs BCD correction.

0110
(1) (1) 1000 0110 ; no underflow EC☐C =0. Sign is negative
0001 0100 ; 10s complement to get the magnitude. Therefore, –06 + (–08) = –(00010100)BCD = –(14)D.

Add –432.01 with –524.98 using BCD notation.
10s complement X = –432.01 ________☐ (1)10s complement Y = –524.98 ________☐ (1) 1 (0)

1 (0)

1 (1)

0101 0110 0111 • 1001 1001
0100 0111 0101 • 0000 0010
1001 1101 1100 • 1001 1011
0110 0110 0110 ; BCD correction 1010 0100 0010 • 1010 0001

1 1 1
0110 0110 ; BCD correction 0000 0100 0011 • 0000 0001 ; no-underflow

;(EC☐C = 0)
EC = 1 C = 1 1 ; sign is negative 1001 0101 1100 • 1001 1001 ; 10s complement Therefore, –432.01 + (–524.98) = –(1001 0101 0110 • 1001 1001)BCD = –(956.99)D.
Add –967.89 with –78.9
10s complement
X = –967.89________☐ (1) 0000 0011 0010 • 0001 000110s complement
Y = –078.9________☐ (1) 1001 0010 0001 • 0001
–1046.79 (1) (0) 1001 0101 0011 • 0010 0001 ; all nibbles are ; valid in BCD

EC = 1 C = 0 ; sign has become positive but there is underflow EC☐C = 1. The result is not correct.

To avoid this underflow we have to use –0967.89 and –0078.9 instead of –967.89 and
–078.9 before 10s complement operation.
BCD Subtraction
BCD subtraction is exactly similar to the addition of one positive number with negative number.
Subtract 569.28 from 690.15 using BCD notation.
BCD
X = 690.15___☐ (0) 0110 1001 0000 • 0001 0101
10s complement
Y = 569.28 ________☐ (1) 0100 0011 0000 • 0111 0010of 569.28 (1) 1010 1100 0000 • 1000 0111
0110 0110
(1) (0) 0001 0010 0000 • 1000 0111

EC = 1 C = 1 AC = 1 ; BCD
; correction ; Difference is

positive.
; No overflow
because
EC☐C = 0. Therefore, 690.15 – 569.28 = (0001 0010 0000 • 1000 0111)BCD.

Subtract 690.15 from 569.28 using BCD notation.
BCD
X = 569.28___☐ (0) 0101 0110 1001 • 0010 1000
10s complement
Y = 690.15________☐ (1) 0011 0000 1001 • 1000 0101of 690.15
X – Y = 120.87 (1) 1000 0111 0010 • 1010 1101
AC = 1 0110 0110 0110 ; BCD correction (1) 1000 0111 1001 • 0001 0011 ; no-overflow (EC☐ C = 0) ; sign negative ; 10s complement

EC = 0 C = 0
0001 0010 0000 • 1000 0111 Therefore, X – Y = –(0001 0010 0000 • 1000 0111)BCD = –(120.87)D. 2.5.2 Gray Code This is reflected unit distance and non weighted code because this code satisfies the unit distance property (adjacent two codes differ in 1 bit only) and reflected property (pair members symmetrically placed about the line of symmetry differ in 1 bit only).As the individual bit does not have any positional weight so this code is not used for any arithmetic operations. The best use of the code is to encode the angular or linear displacement of any moving object. The 4-bit Gray codes are shown in TABLE 2.8. The corresponding decimal and the 4-bit binary codes are also shown in the two left columns of the table.

It may be noted from the TABLE 2.8 that the least significant Gray code bits (g2g1g0) of Decimal Binary codes Gray Code
digit b3b2b1b0 g3g2g1g0

0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100

Line of Sym met ry

8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

Table 2.8 : Gray Code

(8)10 through (15)10 are mirror images of those for (7)10 through (0)10. For upper half of the codes, the MSBs (g3) are all 0’s and for the lower half the MSBs are all 1s.

To illustrate the need for the Gray Code let us consider a problem of linear motion of a moving platform. Suppose the distance between the minimum and the maximum positions of the linear motion is divided into 16 equally spaced points and for each position there are four switches D,C,B and A. These 16 positions are sensed by mechanical switches positions are sensed by mechanical switches 1111. The switch generates logic-1 when it is closed and logic-0 when it is open. So, for position 0, all the switches are open and produce a code 0000, for position 1, only switch A is closed to produce a binary code 0001, for position-2, only switch B is closed and all other switches are open to give a code 0010. The progression would continue upto 1111 where all the switches are closed.

In this encoding problems four mechanical switches are used and all these switches may or may not operate with the same speed. This leads to some erroneous codes which do not conform to the actual motion of the platform. As a particular case assume that the speed of the switches are as follows (speed of Sw A > speed of Sw C > speed of Sw D > speed of Sw B and the platform changes it position from the stable position-7 (equivalent output code 0111) to the next stable position 8 (equivalent output code 1000). In position-7, the switch d is open and C, B and A are closed, and in the position 8, D is closed C, B and A are open. The closing and opening of the switches should be simultaneous when the change over from 0111 to 1000 occurs. Otherwise due to the uneven speed as assumed here we may get the faulty intermediate codes between 0111 and 1000 as shown below : 0111A 0110C 0010D 1010B 1000 7
_____☐6 _____☐2 _____☐10 _____☐
changes changes changes changes 8

Here, we have 0110, 0010 and 1010 as the faulty output codes. Besides these speed combinations of the four switches we may have other 23 combinations depending upon the different degrees of fastness of the switches D,C,B and A. The faulty outputs occur when many switches are required to change their states simultaneously.

In case of Gray Codes there is a change of one bit between two consecutive codes and hence one switch changes its state when the moving platform moves from one position to the next. This eliminates the intermediate erroneous outputs that were present in stepping from position 7 to 8 using binary codes.

2.5.3 Binary-to-Gray Code Conversion
An n-bit binary code can be converted to the equivalent Gray code using the following steps. 1. Starting from the left (MSB), copy the bits of the binary code upto the first 1 bit of the given binary code.

2. The next Gray-code bit gi of position i can be obtained by using exclusive-OR (MOD-2) operation of the binary bit bi with the next adjacent higher significant binary bit bi+1.

Convert the following binary numbers into their corresponding Gray Code. (i) 0101 (ii) 1010
(iii) 01101010 (iv) 00110101

(i) Binary : 0 1 ☐ 0 ☐ 1
☐ ☐ ☐ ☐
Gray Code : 0 0 1 1
(ii) Binary 1 ☐ 0 ☐ 1 ☐ 0
☐ ☐ ☐ ☐
Gray Code : 1 1 1 1
(iii) Binary : 0 1 ☐ 1 ☐ 0 ☐ 1 ☐ 0 ☐ 1 ☐ 0 ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ Gray Code : 0 1 0 1 1 1 1 1 (iv) Binary : 0 0 1 ☐ 1 ☐ 0 ☐ 1 0 ☐ 1
☐ ☐ ☐ ☐ ☐
Gray Code : 0 0 1 0 1 1 1 1
In general for the conversion of binary code bn–1 bn–2 bn–3 ....b2b1b0 to the equivalent Gray code gn–1 gn–2 gn–3..... g2g1g0, we may follow the undermentioned rule : gn–1 = bn–1, gn–2 = bn–1☐ bn–2, gn–3 = bn–2☐ bn–3 ,...., g2 = b3☐ b2, g1= b2☐ b1, g0 = b1☐ b0 The following method can also be implemented for the conversion of binary code, to the Gray Code.

Step 1 : Write the given binary code.
Step 2 : Write the same binary code under the given binary code after shifting one bit position to the left and filling up the vacant right most position of the shifted code by 0.
Step 3 : Perform the mod-2 sum of the bits of the given code and the shifted code.
Step 4 : Neglect the right most bit. The rest of the bits give the Gray code for the given binary number.

Repeat the Example-88 using this algorithm.

(i) 0 1 0 1 ; given binary code (Step 1)
0 1 0 1 0 ; given binary number shifted one bit left (Step 2)
0 1 1 1 1 ; mod-2 sum (Step 3)
0 1 1 1 ; the right-hand bit neglected (Step 4)
Therefore, the Gray Code is 0111.

(ii) 1 0 1 0 ; given binary code (Step 1)
1 0 1 0 0 ; given binary number shifted one bit left (Step 2) 1 1 1 1 0 ; mod-2 sum (Step 3)
1 1 1 1 ; the right-hand bit neglected (Step 4)
Therefore, the Gray Code is 1111.

(iii) 0 1 1 0 1 0 1 0 ; given binary number (Step 1)
0 1 1 0 1 0 1 0 0 ; given binary number shifted one bit left (Step 2) 0 1 0 1 1 1 1 1 0 ; mod-2 sum (Step 3)
0 1 0 1 1 1 1 1 ; the right-hand bit neglected (Step 4)
Therefore, the Gray Code is 01011111.

(iv) 0 0 1 1 0 1 0 1 ; given binary number (Step 1)
0 0 1 1 0 1 0 1 0 ; given binary number shifted one bit left (Step 2) 0 0 1 0 1 1 1 1 1 ; mod-2 sum (Step 3)
0 0 1 0 1 1 1 1 ; the right-hand bit neglected (Step 4)
Therefore, the Gray Code is 00101111.
2.5.4 Gray-to-Binary code conversion
In this case the code conversion is started from MSB of the Gray code and the undermentioned steps are followed.
Step 1 : Starting from the MSB of the Gray code, copy down the bits from the Gray code bits upto the first 1 of the Gray code.
Step 2 : (a) If the next Gray code bit is 0 then repeat the binary bit obtained just earlier to get the next binary bit.
Step 3 : Repeat the step-2 until the LSB of Gray code is used for this conversion.
Convert the following Gray codes into the Binary (i) 0111
(i) Gray codes (ii) 1111 (iii) 0101 1111

0
☐
0
1

☐
1
1
1 ☐
1 0 1
1 1
1
1
0 1 0 0
1
1 0 1
1 Binary code (ii) Gray codes
Binary code (iii) Gray codes
Binary code 0 1
☐ ☐ 1 1 1
0 1
1 1
0 In general we may follow the following equations to convert n-Bit Gray code into n-Bit binary code.
bn–1 = gn–1, bn–2 = gn–2☐ bn–1, bn–3 = gn–3☐ bn–2,...., b2 = g2☐ b3, b1 = g1☐ b2, b0 = g0☐ b1

The following method can also be applied for the conversion of Gray code to binary : Step 1 : Write the Gray code.
Step 2 : Write the same Gray code underneath the given code written in Step 1 but shifting one bit to the left and fill-up the vaccant bit position on the right by 0.

Step 3 : The process of writing after shifting is repeated (n–1) times if the number of bits in the Gray code are n.
Step 4 : Add each column ingoring the carry (MOD-2 addition).

Step 5 : Ignore the number of bits from the right-hand end of the added result, one less than the number of bits present in the given Gray code number i.e. for a given n bit Gray code we have to ignore n–1 bits from right-hand side.

Step 6 : Remaining bits give the equivalent binary code for the given Gray code.
Convert the Gray codes (i) 0111 (ii) 1111 and (iii) 01011111 into binary code following the algorithm of shifting and adding.
(i) 0 1 1 1
; Step 1

0 1 1 1 0
0 1 1 1 0 0 ; Step 2 and Step 3
0 1 1 1 0 0 0
0 1 0 1 1 0 1 ; Step 4

neglect 3 bits;Step 5
as n = 4
0 1 0 1 ; Binary code
Thus, the binary code is 0101 for the Gray code 0111.
(ii) 1 1 1 1
; Step 1

1 1 1 1 0
1 1 1 1 0 0 ; Step 2 and Step 3
1 1 1 1 0 0 0
1 0 1 0 1 0 1 ; Step 4

neglect 3 bits; Step 5
as n = 4
1 0 1 0 ; Binary code
Hence, the binary code is 1010 for the Gray code 1111.
(iii) 0 1 0 1 1 1 1 1 ; Step 1
0 1 0 1 1 1 1 1 0

0 1 0 1 1 1 1 1 0 0
0 1 0 1 1 1 1 1 0 0 0

0 1 0 1 1 1 1 1 0 0 0 0
; Step 2 and Step 3

0 1 0 1 1 1 1 1 0 0 0 0 0
0 1 0 1 1 1 1 1 0 0 0 0 0 0
0 1 0 1 1 1 1 1 0 0 0 0 0 0 0
0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 ; Step 4

neglect 7 bits as n = 8 ; Step 5Line of symmetry Hence, the binary code is 01101010 for the Gray code 01011111.
2.5.5 Excess-3 Gray Code If the Gray codes are examined in TABLE 2.8 for the BCD codes of the decimal number 0 to
9 then it is observed that the unit distance property gets lost because the Gray code 910 is
1101 and that of 010 is 0000. If we compare the Gray codes 1101 and 0000 we find that the change of bits occur in three positions instead of in only one. To overcome this situation, one may use the Gray codes developed from the XS -3 code of 0 to 9. These codes are called XS-3 Gray codes. XS-3 Gray codes are shown in the TABLE 2.9.

Decimal X3-3 XS-3 Decimal X3-3 XS-3
codes Gray Code Codes Gray code
0 0111 0100 6 1001 1101
1 0100 0110 7 1010 1111
2 0101 0111 8 1011 1110
3 0110 0101 9 1100 1010
4 0111 0100
5 1000 1100
Table 2.9 : XS-3 Gray Code 2.5.6 ASCII Code

ASCII is the abbreviation of AMERICAN STANDARD CODE FOR INFORMATION INTERCHANGE. This code was defined by American National Institute in 1968. The ASCII is pronounced as “AS-KEE”. This is a 7-Bit code and is provided for coding 128 different alphanumeric characters. Besides communication applications, the ASCII code is widely used in personal computers as the prime character codes. An eighth bit is frequently appended as parity bit. If the parity bit is not used then the eighth bit position is filled with 0. The ASCII codes for common alphanumeric characters and symbols are given in TABLE 2.10. It should be noted that each 7-Bit code can be represented conveniently by two hexadecimal digits because hexadecimal form is more compact and easy to remember. Notice that the ASCII also has lowercase letters. The code corresponding to the lowercase letter has 1 in the sixth bit. This makes it easy for the machines to handle the shift-key on a keyboard.

ASCII Codes Alphanumeric 7-Bit Binary Codes expressed Character code in HEX Alphanumeric 7 Bit Binary Code expressed character code in HEX

A 1000001 41
B 1000010 42
C 1000011 43
D 1000100 44
E 1000101 45
F 1000110 46
G 1000111 47
H 1001000 48
I 1001001 49
J 1001010 4A K 1001011 4B L 1001100 4C M 1001101 4D N 1001110 4E O 1001111 4F P 1010000 50
Q 1010001 51
R 1010010 52
S 1010011 53
T 1010100 54
U 1010101 55
V 1010110 56
W 1010111 57
X 1011000 58
Y 1011001 59
Z 1011010 5A 0 0110000 30
1 0110001 31
2 0110010 32
3 0110011 33
4 0110100 34
5 0110101 35
6 0110110 36
7 0110111 37
8 0111000 38

a 1100001 61
b 1100010 62
c 1100011 63
d 1100100 64
e 1100101 65
f 1100110 66
g 1100111 67
h 1101000 68
i 1101001 69
j 1101010 6A k 1101011 6B l 1101100 6C m 1101101 6D n 1101110 6E o 1101111 6F p 1110000 70
q 1110001 71
r 1110010 72
s 1110011 73
t 1110100 74
u 1110101 75
v 1110110 76
w 1110111 77
x 1111000 78
y 1111001 79
z 1111010 7A { 1111011 7B } 1111101 7D Blank 0100000 20
! 0100001 21
“ 0100010 22
# 0100011 23
$ 0100100 24
% 0100101 25
/ 0101111 2F

Alphanumeric 7-Bit Binary Codes expressed Alphanumeric 7 Bit Binary Code expressed Character code in HEX character code in HEX

9 0111001 39 ( 0101000 28
: 0111010 3A ) 0101001 29
; 0111011 3B * 0101010 2A < 0111100 3C + 0101011 2B = 0111101 3D , 0101100 2C > 0111110 3E – 0101101 2D ? 0111111 3F . 0101110 2E Table : 2.10 ASCII Code Translate the following ASCII code into characters and symbols. Assume that the eighth bit of each code is 0.
(a) 01000111 01101111 01101111 01100100
(b) 00110010 00110011 00101110 00111000
(a) 01000111 01101111 01101111 01100100= Good(G) (o) (o) (d)
upper lower lower lower
case case case case
(b) 00110010 00110011 00101110 00111000= 23.82 3 • 8
2. 6 ERROR DETECTING AND CORRECTION CODES

When a digital information is transmitted over a long distance or when the different subcircuits of a computing system communicate with each other, it is possible that the errors is introduced during the transmission due to the pickup of noise, crosstalk and other malfunction of the circuit. Owing to these undesired effects a few of the transmitted 0s inadvertently become 1s or a few of the transmitted 1s may become 0s on the way and received at the receiving end. For the purpose of system reliability and error-free transmission we need to detect such errors. Suppose a BCD 0110 is transmitted and due to some noise pickup this code is changed to 1110 or 0111 and received by the receiver. Obviously, 1110 i s not a valid code in BCD and indicates an error, 0111 however will be accepted as decimal 7 and the error will not be detected because it is a valid BCD code.

There are several ways for detecting these transmission errors. There is one scheme called 2-out- of 5 coding scheme : In this case exactly 2 bits within 5-bit code group are 1s. Thus, if a single 0 should become 1 or a single 1 should become a 0 (but not both), there will no longer be exactly two 1s within the received code group. In this way, the determination of the number of 1s in a received code group can be used as a means for detecting the occurance of single error transmission.

There are several ways for detection of the transmission errors. In the following section discussions will be made for a few important codes and the error detection procedure using those codes.

(a) Forbidden Combination Check Code : In this coding scheme 4 binary bits with 8 –4
– 2 – 1 weight are used and out of 16 possible codes, using these 4 bits, only 10 combinations are used to represent the ten decimal digits 0 to 9 and the remaining six combinations are treated as invalid codes. Presence of any of these six invalid combinations on the way of transmission indicates an error. As mentioned at the beginning of this section that an error or multiple errors may enter into the coded message of decimal digits but the receiver cannot declare any error if the received message including the error bits remain within the group of ten valid codes. It can be shown that this coding scheme can detect about only 25% of the total possible errors.

(b) M-out-of-N codes : In this coding, N bits are used to represent a message. Out of N bits, M number of ‘1’ bits are used along with the (N–M) number of ‘0’ bits. So, there may be N! possible coding. One such popular scheme is 2-out-of 5 code which is used toM!(N-M)!
represent5! = 10 possible decimal digits. In each combination of 2-out-of-5 code there are2!3!

two 1s and three 0s. These codes are shown in the TABLE 2.11. From this table it may be noted that these codes are unweighted. Appearance of no 1, single 1 or more than two 1s during the transmission using this code indicate an error.

Decimal 2-out-of-5 63210 74210
digit code code code

0 00011 00110 11000
1 00101 00011 00011
2 00110 00101 00101
3 01001 00110 00110
4 01010 01010 01001
5 01100 01100 01010
6 10001 10001 01100
7 10010 10010 10001
8 10100 10100 10010
9 11000 11000 10100

Table 2.11 : M-out-of-N Codes
Other varieties of codes like 63210 and 74210 are also shown in TABLE 2.11. But these two codes are weighted codes. The combinations 00110 and 11000 in 63210 and 74210 represent zero (decimal) and do not bear the correct weightage. This has been specially done to make the binary group for decimal zero only.

(c) Biquinary Code : It is a 7-bit weighted code. Here, ‘Bi’ means 2 and ‘quinary’ means 5. This 7 bit code is the concaranation of two groups of codes : (i) 1-out-of-2 meaning only one
‘I’ bit out of 2 bits. (ii) 1-out-of-5 meaning onlyDecimal Biquinary one ‘1’ bit out of 5 bits. The weights of the 7 bitsdigit code are 5,0,4,3,2,1,0. There are only ten possible50 43210 combinations to represents ten decimal digits. 0 01 00001 The codes are shown in TABLE 2.12.
1 01 00010 Notice the construction of the codes words :2 01 00100 The 01 under the most significant weights (5,0)3 01 01000 indicates that the decimal digit is in the range4 01 10000 from 0 to 4, whereas a 10 under (5,0) indicates5 10 00001 the range from 5 to 9. For example, 1 under the6 10 00010 weight ‘0’ i.e. under the 1st column under the7 10 00100 weight (43210) with 01 under the weight (5,0)8 10 01000 means that the decimal digit ‘0’ which is the9 10 10000 1st member in the sub-range 0 to 4 ; 1 under the Table 2.12 : Biquinary Code weight ‘4’ i.e. under the 5th column with 01 under (5,0) indicates that the decimal digit ‘4’ which is the 5th member of the sub-range 0 to 4. Similarly, 1 under the weight ‘2’ i.e. in the 3rd column with 10 under (5,0) indicates that the position of the decimal digit ‘7’ which is third in the sub-range 5 to 9.

In the Biquinary code, more than single 1 in the left 2-bit group or in the right 5-bit group indicates an error.
(d) Parity : Another popular way of detecting a single error is by appending an extra 1 with the coded message so as to make the total number of 1s either even or odd in the transmitted coded message. This additional bit is called Parity bit. If the appended bit makes the total number of 1s in the string to be odd, then this scheme of addition of the extra bit is called Odd-parity scheme. Similarly, if the total number of 1s in the bit string becomes even after appending the parity bit then this scheme is called the Even-parity scheme. The parity bit in both the cases is appended as the MSB of the string.
The testing for an even or odd number of 1s within a string of bits can be easily done by digital circuit. If the receiver and transimitter is designed for the even parity scheme then the transmitter will always try to send the coded message making the total number of 1s in the message even by appending one 1 (if the total number of 1s in the message is already even then 0 will be appended) and the receiver will also expect any message with even number of 1s including the even parity bit. If at any time the number of 1’s in the coded message becomes odd and detected at the receiving end then an error is declared by the receiver and a request will be done by the receiver to the transmitter for retransmission. Similarly, for odd parity scheme the transmitter will send the coded message with odd number of 1s including the parity bit and the receiver expects the message with the odd number of 1s in the message. If this is not satisfied, an error is declared by receiver and retransmission is requested.
It should be noted that although the parity scheme detects the occurance of single error in the message code, however, it does detect any odd number of errors.
The parity-bit is a form of redundancy that is part of the coded message. However, the redundancy has a price. If we use this parity scheme with 7-bit ASCII code then the total number of bits per code becomes 8, an overhead of 14% is incurred. The overhead of any error detection code is a measure of its efficiency.

Find out the parity bits both under even or odd parity schemes when the following characters are transmitted using ASCII codes.
(i) A (ii) 9 (iii) I (iv) y
(i) ASCII code of A is 1000001. The total number of 1s in this code is even. Therefore, the even parity bit to be added is 0 and the odd parity bit to be added is 1. (ii) ASCII code of 9 is 0111001. The total number of 1s in this code is even. Therefore, the even parity bit to be added is 0 and the odd parity bit to be added is 1.

(iii) ASCII code of I is 1001001. The total number of 1s in this code is odd. Therefore, the even parity bit to be added is 1 and the odd parity bit to be added is 0.
(iv) ASCII code of y is 1111001. The total number of 1s in this code is odd. Therefore, the even parity bit to be added is 1 and the odd parity bit to be added is 0. (e) Checksum : When data is to be tranmitted over a long distance, the single parity bit is less effective. This is because the data is subject to burst noise source that may persist for several milliseconds, changing the bits of many data in the process. This may happen due to the lightning. For this type of noise, data is often protected by a checksum code following the transmission of a large block of character codes, (typically 512 or 1024). The carryover due to this addition is ignored. This process is also repeated at the receiver end. If a match is found between the checksum code generated at the transmitter and the receiver ends then there is a high probability that the transmission is free of error, and any mismatch indicates an error. Like parity, this method can be easily implemented. But the agreement of the checksum code does not predict a cent-percent error free transmission because there may be some compensating errors in the block of data of the message, that is the error in the one code of a message may be compensated by the error or errors in the other code or codes so that the net sum of the block of transmitted codes is same.

What is the checksum code for a block of 5 messages defined by codes 48H, 65H, 6CH, 70H and 21H?
The sum of 48H, 65H, 6CH, 70H and 21H is AAH, ignoring the carry from MSB position. Hence, the checksum code is AAH.

In the above transmission, the message codes are affected by noise and are changed to 47H, 66H, 70H, and 21H at the receiver end. Find out whether the receiver can detect any error using the checksum code.

48H = 01001000 47H = 01000111
65H = 01100101 66H = 01100110
6CH = 0110110 6CH = 01101100
70H = 01110000 70H = 01110000
21H = 00100001 21H = 00100001
Checksum Code = AAH = 10101010 AAH = 10101010 = Checksum Code at the at the transmitter receiver(Ignoring Carry) (Ignoring Carry)
From the checksum code at the transmitter and receiver ends no transmission error can be detected, but errors have occured in the codes 48H and 65H, keeping the net sum same. These errors are compensating type.
(f) Block Parity : Using the Block Parity code we may detect more than one error but may correct a single error in a block of message codes. In this scheme either an odd or even parity bit is appended to each row and column in a block of data. To illustrate the action of the block parity code we consider an example with a block of 8 ASCII codes as shown in TABLE 2.13(a). This block represents the 7-bit ASCII codes for the characters A,B,C,D,E,F,G and H. The odd parity bit has been appended to the most significant position of each code row-wise and a new row has been generated which consists of the odd parity bit for each column (including the odd parity bit column). This is shown in TABLE 2.13(a).
Odd Parity bit ☐
Bit position☐ 8 7 6 5 4 3 2 1
Character A 1 1 0 0 0 0 0 1
“ B 1 1 0 0 0 0 1 0
“ C 0 1 0 0 0 0 1 1
“ D 1 1 0 0 0 1 0 0
“ E 0 1 0 0 0 1 0 1
“ F 0 1 0 0 0 1 1 0
“ G 1 1 0 0 1 0 0 0
“ H 1 1 0 0 1 0 0 0
Odd parity bits for
the eight columns☐ 0 1 1 1 0 1 1 1

Table 2.13(a) : odd parity bits are appended to each row and column to a block of 7 ´ 8 block of data bits.
Odd Parity bit ☐

Bit position ☐ 8 7 6 5 4 3 2 1
Character A 1 1 0 0 0 0 0 1
“ B 1 1 0 0 0 0 1 0
“ C 0 1 0 0 0 0 1 1
“ D 0 1 0 0 1 1 0 0
“ E 0 1 0 0 0 1 0 1
“ F 0 1 0 0 0 1 1 0
“ G 1 1 0 0 0 1 1 1
“ H 1 1 0 0 1 0 0 0
Odd parity bits for the eight columns☐ 0 0 1 1 1 1 1 1
Table 2.13(b) : An error 0 ® 1 has occured in the bit position of column 4 of character D.

Suppose, the bit in the 4th column position of character D has changed to 1 from 0 due to some transmission error. This is shown in TABLE 2.13(b). If we generate the parity bits at the receiving end for each row and column of the data block and compare the same with those of transmitter end, we can detect mismatch in the row and the column of the parity bits. The mismatch in TABLE 2.13(b) indicates that an error has occured at the crossing point of column number 4 and row number 4 i.e. in the bit position 4 of character D. If error occur in two columns then we can understand that two errors are present. This block parity is widely used for data stored on magnetic tape.

(g) Hamming Code : Hamming code was developed in 1950 by R.W. Hamming. In this coding, the number of parity bits are more than one. The relationship between the n information bits and p parity bits 2p = n + p + 1. Thus, for 4 information bits there will be 3 parity bits, for 11 information bits there will be 4 parity bits and for 26 information bits the number of parity bits will be 5 etc. In the Hamming code the parity bits are placed in the bit positions of 1,2,4,8 and 16 etc. and the information bits in the position of 3,5,6,7,9-15 etc. Following is a format of 7-bit Hamming code where n = 4 and p = 3.

Bit position : 7 6 5 4 3 2 1
x7 x6 x5 p4 x3 p2 p1
In this format the 4-bit information is x7x6x5x3 and the 3-bit parity is p4p2p1. These parity bits are all even parity bits. The parity bit p1 is the even parity bit and depends on bits 1,3,5 and 7
p2 is the even parity bit and depends on bits 2,3,6 and 7
and p4 is the even parity bit and depends on bits 4,5,6 and 7.
We illustrate the parity bit generation technique with the help of the following example : Let the four message bits are 1101 (= X7X6X5X3). Then we may write the message bits and the parity bits together as Bit position : 7 6 5 4 3 2 1
1 1 0 p4 1 p2 p1
We know that p1 bit is used to obtain an even parity depending on bit positions 1,3,5 and 7.

This bit pattern is p1101. To make the parity even the bit p1 should be 0. The parity bit p2 establishes even parity for bits 2,3,6 and 7. This bit pattern is p2111. To maintain the parity as even, p2 should be 1. Similarly, to maintain even parity for the bits 4,5,6 and 7 the p4 should be 0. Thus, the transmitted 7-bit Hamming code for the message bits 1101 is 1100110.

The even parity bits p1, p2 and p4 can be generated using Exclusive -OR operations p1 which depends on bits of positions in the following way : For even-parity of bits 1,3,5 and 7 we may write
p1☐ X3☐ X5☐ X7 = 0
or, p1☐ (p1☐ X3☐ X5☐ X7) = p1☐ 0 = p1
or, X3☐ X5☐ X7 = p1

Similarly, for even parity of bit p2 which depends on bits of positions 2,3,6 and 7 p2☐ X3☐ X6☐ X7 = 0
or, X3☐ X6☐ X7 = p2
and for even parity of bits p4 which depends on bits of positions 4,5,6 and 7 p4☐ X5☐ X6☐ X7 = 0
or, X5☐ X6☐ X7 = p4

Using the expressions of p1, p2 and p4 we may easily generate the even parity bits for any four bit message. For example, if the 4-Bit message is 1101 then X3 = 1, X5 = 0, X6 = 1 and X7 = 1

p1 = X3☐ X5☐ X7 p2 = X3☐ X6☐ X7 and p4 = X5☐ X6☐ X7 = 1 ☐ 0 ☐ 1 = 1 ☐ 0 ☐ 1 = 1 ☐ 0 ☐ 1 = 0 = 1 = 0

Checking of error and determination of the position of the error bit in the message can be done by generating the check bits at the receiver end using the transmitted Hamming code. The check bits are nothing but the even-parity bits using the transmitted message and parity bits. Thus the check bits can be generated using the following expressions parity bits. Thus the check bits can be generated using the following expressions: C1 = p1☐ X3☐ X5☐ X7, C2 = p2☐ X3☐ X6☐ X7, C4 = p4☐ X5☐ X6☐ X7

If C1 = C2 = C4 = 0, then no errors has occured. If C1 = 1, C2 = C4 = 0, then we may conclude that one of the bits of position 1,3,5 and 7 is in error but the bits of position 2,3,6 and 7 and 4,5,6 and 7 are correct. Therefore, bit of position 1 must be in error. In this way we may get the position of bit where the error has occured. The C4 C2 C1 gives the binary code for the position of bit where error occurs.

Let us assume that a 4-bit message 1010 is transmitted using Hamming code as

Bit position : 7 6 5 4 3 2 1
x7 x6 x5 p4 x3 p2 p1
Hamming Code : 1 0 1 0 0 1 0

and assume that this transmitted Hamming code reaches the receiver with a single error at positions 5 i.e. the receiver receives the code as 1000010. The check bits C1,C2 and C4 generated at by the receiver from this faulty message are C1 = p1☐ X3☐ X5☐ X7 = 0 ☐ 0 ☐ 0 ☐ 1 = 1
C2 = p2☐ X3☐ X6☐ X7 = 1 ☐ 0 ☐ 0 ☐ 1 = 0
C4 = p4☐ X5☐ X6☐ X7 = 0 ☐ 0 ☐ 0 ☐ 1 = 1

these three check bits gives us a code C4 C2 C1 = 101. This indicates that there is an error in bit position 101 = 510 i.e. the bit X5 is in error. This bit can be corrected by inverting this bit.
1. Decimal 43 in hexadecimal and BCD number system is respectively (a) B2, 0100 0011, (b) 2B, 0100 0011, (c) 2B, 0011 0100, (d) B2, 0100 0100

2. A new Binary Coded Pentary (BCP) number is proposed in which every digit of base 5 number is represented by its 3 bit binary code. For example the base 5 number 24 will be represented by its BCP code as 010 100. In this numbering system, the BCP code 10001001101 corresponds to the following number in base 5 system (a) 423, (b) 1324, (c) 2201, (d) 4231

3. Conversion of the decimal number 427.5 into base 6 and base 8 will be (a) 1551.3, 653.4 (b) 1551.3, 255.3 (c) 2555.3, 653.4 (d) 2555.3, 255.3

4. A digital system is required to amplify a binary encoded audio signal. The used should be able to control the gain of the amplifier from a minimum to maximum in 100 increments. The minimum number of bits required to encode in straight binary is (a) 8, (b) 6, (c) 5, (d) 7 5. Binary number (10111.101)2 when converted to base 4
(a) 221.13, (b) 132.12, (c) 113.22, (d) 123.12

6. The value for x and y of the following set of simultaneous equations (40)x = (50)y ; (x1)y = (111)x will be
(a) x = 6, y = 5, (b) x = 6.5, y = 7.5, (c) x = 5, y = 6, (d) x = 5.6, y = 5.7

7. The Gray code for (A5)16 is equivalent to [ISRO 2017} (a) 10010101, (b) 11010101, (c) 11011111, (d) 11011011 8. If (146)x + (313)x-2 = (246)8 , then the value of base x is [ISRO 2012] (a) 5; (b) 6; (c) 7; (d) 9

9. The two numbers represented in signed 2’s complement form are P = 11101101 and Q = 11100110. If Q is subtracted from P, the value obtained in signed 2’s complement is [ISRO 2013]

(a) 1000001111; (b) 00000111; (c) 11111001; (d) 111111001 10. The range of signed decimal numbers that can be represented by 6 bits 1’s complement number is [GATE 2004] (a) – 31 to + 31; (b) - 63 to +64; (c) - 64 to + 63; (d) – 32 to + 31 11. The correct BCD sums for the following positive decimal numbers using BCD notation 526 + 692 is
(a) 0001 0010 0001 1000; (b) 0010 0000 0001 1000;
(c) 0001 0010 0001 0101; (d) 0010 0011 0001 0101
12. Which of the following binary number is equal to octal number 66.3 [ISRO 2007] (a) 101101.100; (b) 1101111.111;
(c) 111111.1111; (d) 110110.011
13. 4-bit 2’s complement representation of a decimal number is 1000. The number is (a) + 8; (b) 0; (c) – 7; (d) – 8
3.1 INTRODUCTION

The basic elements of digital circuits are the logic-gates. The most basic type of electronic circuit designed with active devices and passive components which consists of two or more inputs and one output performing basic logic operation are called the logic gates. Each gate is given several input signals to act upon. Its output may be High (logic-1) or low (logic-0) with respect to the voltage levels. The output depends upon the combination of HIGH and LOW inputs and the types of gate used. Since gates have the ability to make logic decisions by producing a particular output under certain input conditions, they are commonly called Logic-gates. The interconnections of gates to achieve a prescribed outcome is called “Logicdesign”.

A gate can be used alone to perform a basic logic function. The output of one gate can also be connected to the inputs of several other gates to form a big logic network. In a network, one gate contributes its decision again. This way, a complex function can be performed on the basis of a few simple individual ‘yes’ and ‘no’ decisions. In these cases, the inputs and outputs of all gates are accessible, in the sense that external connections can be made to them. Because of their accessibility, logic circuits constructed by the interconnections of logic gates are said to be designed with discrete logic gates.

3.1.1 Functional Behaviour of Logic Gates

Without going to the electronic circuits which are internal to the logic gates one can draw, analyse and synthesize the digital circuits of the symbols and the functional behaviour (input/output behaviour) of the indivdual gate is known. The functional behaviour of a logic gate can be described by (i) the truth table (ii) logic equation and (iii) timing diagram. Before going to the description of the basic gates we introduce the term Truth Table and the concept of Timing Diagram.

65
3.2 LOGIC GATES TYPES

Using modern semiconductor technology, the functional behaviour of these electrical logic circuits are incorporated into a single Integrated Circuit (IC).Some standard basic logic elements i.e. gates are available. Those are AND gate, OR gate, NOT gate, NAND gate, NOR gate, EX-OR gate. In the next subsection we shall study the functional behavior and logic symbols of these logic gates.

3.2.1 AND gate

The AND gate is made up of two or more inputs and one output. The inputs and the outputs may have logical states either ‘0’ or ‘1’. Keeping in mind that the practical gates operate with two voltage levels for the two states. The property of this gate is – “Output is logic-1 if an only if its inputs are all at logic-1 and the output is logic-0 if any one of the inputs is at logic-0”.

Inputs Output

B A X

0 0 0

0 1 0

1 0 0
Fig: 3.1 (b) Equivalent1 1 1
logic circuit
Table 3.1 : Truth table of a 2-input AND gate The logic symbol of twoinput AND gate is shown in the Fig 3.1(a) and the truth table is shown in TABLE 3.1. The equivalent electrical network designed with simple switches is shown in figure 3.1(b). Here, A and B are two inputs to the gate and X is the output.

The truth table shows the different possible combinations of the digital inputs A and B for a 2-input AND gate with X as the output. The logic level of the output of ANDgate is ‘1’ only when both the inputs are logic-1. Therefore, this AND operation may be called the logical multiplication and the logical AND function of the variables A and B is written as X = A.B (called X equals A AND B) or simply X = AB. The inputs to the AND gate may be more than two. The logic symbol for the three-input ANDgate may be drawn as in Fig 3.2 and the corresponding truth table is shown in TABLE 3.2.

For Fig 3.2, the output, X may be written as X = A.B.C.

Inputs Output C B A X 0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0
1 1 0 0
1 1 1 1

Table 3.2 : Truth table of 3-input AND gate.

The behaviour of the AND gate can further be explained using time varying logic-input signals. Fig 3.3 shows two time varying inputs, applied to the two inputs A and B of a twoinput AND gate of the and X shows the output of the AND gate. The pulse output can be explained using the properties truth table (TABLE 3.1) of the ANDgate.

A
B
X
During (0 to t1) : During (t1 to t2): Both inputs are high output X is high according to the fourth line of TABLE 3.1.

Input A is high and input-B is low, output X is low according to the second line of TABLE 3.1.
During (t2 to t3) : Input A is low and input B is low, output X is low according to the first line of the TABLE 3.1.
During (t3 to t4) : Input A is high input B is high, output X is high according to the fourth line of TABLE 3.1.
3.2.2 OR-gate Another basic gate logic gate is the OR gate. It is made up of two or more inputs and one output. The input/output property of this gate is as follows : “The output of the OR-gate is logic-1 (i.e. High) if any one of the inputs or all the inputs of this gate is at logic-1 (i.e. High). The output is low only when all inputs are at logic-0 (i.e. low).

The logic symbol of a two input OR-gate is shown in Fig 3.4(a) and the truth table is shown in TABLE 3.3. In this table A and B are the inputs and X is the output. This table shows different combinations of the inputs and the output in form of the logic levels. The output X can be written by the logic-equation, X = A+ B(called X equals A or B).

Inputs Output B A X

0 0 0

0 1 1

1 0 1
1 1 1
Table 3.3 Truth Table of or gateFig: 3.4 (b) Equivalent circuit

In this equation the symbol (+) does not stand for the arithmetic addition but it stands for logical OR-operator (details of this operator will be discussed in the next chapter) defined by the truth table, TABLE 3.3. The equivalent electrical network designed with simple switches is shown in Fig 3.4(b) The state of the lamp is ON(equivalent to logic-1) if any one of the two switches is closed (equivalent to logic-1) or both switches are closed.

The operation of the OR gate can further be explained using time varying digital signals to the OR-gate inputs and observing the gate output X. For explanation, we consider a twoinput OR gate with inputs A and B and the output X. The time varying signals are applied to the inputs and the output waveform is drawn according to the OR-gate truth table TABLE 3.3. Output waveform at X is shown in Fig 3.5.

During (0 to t1) : Both inputs are low, output X is low according to the first row of TABLE 3.3.
During (t1 to t2) : Both inputs are high, output X according to the last row of TABLE 3.3.
During (t3 to t4) : Input A is low and input B is high, output is high according to the third row of the TABLE 3.3.
During (t4 to t5) : Input A is high and the input B is low, output X is high according to the second row of TABLE 3.3.
After t3 : Both inputs are low, the output X is low according to the first row of TABLE 3.3.
3.2.3 NOT-gate This is a single input and single output gate. The purpose of this gate is to produce the complemented or inverted output. If the input is at logic-1, the output will be at logic-0 and

viceversa. The logic symbol and the equivalent

electrical network is

shown in Fig 3.6(a) and

3.6(b) respectively and the

truth table is shown in

TABLE 3.4.

Input Output

A X

0 1

1 0

Table 3.4 Truth table of a NOT gate

The small circle (also called bubble) is attached to the triangular symbol to identify the symbol as inverter in digital logic circuit. In general, in logic symbol, a bubble means the inversion in digital logic circuit. The input and the output of this logic gate is written as –
X = A (called X equals NOT A). This overbar (–) symbol means that input A is complemented at the output X.

The equivalent electrical network for the NOT operation is shown in Fig 3.6(b). When the switch SW is closed (equivalent to logic-1 state), the lamp will be OFF (equivalent to

logic-0 state) because all the currents will be bypassed by the closed switch SW. The resistance R is connected to limit the current otherwise the power supply will be shortcircuited when the switch is closed. When the switch is open(equivalent to logic - 0), the lamp will be ON (equivalent to logic-1). Thus operation of this electrical network follows the truth table of the NOT gate. The response of this gate to any time varying digital waveform is shown in Fig 3.7.

The output waveform is explained below : During (0 to t1) : Input is logic-0, the output is logic-1 according to the first row of TABLE 3.4.
During (t1 to t2) : Input is logic-1, the output is logic-0 according to the second row of TABLE 3.4.
During (t3 to t4) : Input is logic-0, the output is logic-1 according to the first row of TABLE 3.4.
During (t4 to t5) : Input is logic-0, the output is logic-1 according to the first row of TABLE 3.4.
3.2.4 NANDgate The NAND function is equivalent to the AND function followed by the NOT function i.e. inversion. The logic symbol equivalent circuit and the truth table of a two input NAND gate is shown in Fig 3.8(a), 3.8(b) and TABLE 3.5 respectively.

“ A logic-0 is produced at the output only when all inputs are at logic-1 and logic-1 is produced at the output when any of the inputs is at logic-0.”

Inputs Output

B A X

0 0 1

0 1 1

1 0 1

1 1 0

Table 3.5 : Truth table of a 2-input
NAND gate

The truth table (TABLE 3.5) shows that only for the fourth combination i.e. when both the inputs are high the output X becomes low otherwise for all other combinations the output is high. If we compare the truth table of the AND gate (Table 3.1) with that of NAND then it is seen that the output column of NAND gate is the inverse that of the AND gate. The input and the output of the two input NAND gate can be represented by the logic equation X = A.B (called X equals NOT of a A AND B).

For more than two inputs (say for 4 inputs) we have to AND all the inputs and put an overbar symbol (–) over this AND term A.B.C.D. So, for a four input NAND gate the output X and can be written using the following logic equation.

X = A.B.C.D or simply as X = ABCD
t
t
t

The equivalent electric network whose behavior is similar to the 2-input NAND gate is shown in Fig 3.8(b). In this equivalent electrical network, when both the switches are closed(equivalent to logic-1) the current will be bypassed and the lamp will be OFF (equivalent to logic-0). If any of the two switches or both are open (equivalent to logic-0), the whole lamp and it will be ON(equivalent to logic-1).

The response of a 2-input NAND gate to the time varying waveform is shown Fig 3.9. The output waveform of Fig 3.9 is explained below : During (0 to t1) : Input A is 1 and input B is 0, the output X is 1 according to the second row of TABLE 3.5.
During (t1 to t2) : Input A is 0 and input B is 0, the output X is 1 according to the first row of TABLE 3.5.
During (t2 to t3) : Input A is 1 and input B is 1, the output X is 0 according to the last row of TABLE 3.5.
During (t3 to t4) : Input A is 1 and input B is 0, the output X is 1 according to the second row of TABLE 3.5.
During (t4 to t5) : Input A is 0 and input B is 0, the output X is 1 according to the first row of TABLE 3.5.

3.2.5 NOR-gate
A NOR gate is another basic logic gate with two or more inputs and one output with the following input/output properties :
“ A logic-1 output is produced only when all inputs are logic-0. A logic-0 output is produced if any of the inputs is logic-1”.

The term NOR is derived from NOT-OR and implies an OR function followed by an inversion. The logic symbol and the truth table for a two input NOR gate is shown in Fig 3.10(a) and TABLE 3.6 respectively.

Inputs Output
B A X

0 0 1

0 1 0

1 0 0

1 1 0

Table 3.6 : Truth table of 2-input NOR gate
If we compare the output of the NOR gate with the output of OR-gate it can be observed that the output of the NOR-gate is the inverse that of the OR gate. This is also reflected in the symbol of the NOR-gate where a small circle or a bubble has been placed at the outputs the symbol of the NOR-gate where a small circle or a bubble has been placed at the outputs input NOR gate is X = A+B (called X equals NOT of A OR B). Similarly, for three inputs, we have to OR all the inputs and have to put an overbar (–) over this, i.e. the output X for a 3-input OR-gate can be represented by the following logic equation :
X = A+B+C
The equivalent electrical network whose behavior is similar to a 3-input NOR-gate is shown in Fig 3.10(b).

From this figure it can be observed that the lamp will be ON (equivalent to logic-1 output) only when all the switches (SW1, SW2, SW3) are open (equivalent to logic-0 input) and will be OFF (equivalent to logic-0 output) if any one of the three switches are closed (equivalent to logic-1 input) because any closed switch bypasses all the currents. The resistance R is used to limit the current when any one switch or all the switches are closed.

The response of NOR gate can be studied using the time varying digital waveform as inputs. This is shown in Fig 3.11. The waveform at the output X is explained below : During (0 to t1) : The input A is 0 and input B is 1, the output X is 0, according to the third row of TABLE 3.6.
During (t1 to t2) : The input A is 1 and the input B is 1, the output X is 0, according to the fourth row of TABLE 3.6.
During (t2 to t3) : Both inputs are 0, the output X is 1 according to the first row TABLE 3.6.

t
t
t

During (t3 to t4) : Input A is 1 and input B is 0, the output X is 0, according to the second row of TABLE 3.6.
During (t4 to t5) : The input A is 0 and the input B is 1, the output X is 0, according to the third row of TABLE 3.6.
During (t5 to t6) : Both the inputs are 0, the output is 1, according to the first row TABLE 3.6.

3.2.6 Exclusive-OR gate (EX-OR or XOR-gate)

The 2-input OR-gate described in the section 3.2.2 may be called an inclusive -OR gate because it produces a high output when either one or all inputs are high. An exclusive OR gate operates differently in that, the output is high when any one input is high, but not when all inputs are high. Since the logic function of this gate excludes the “all inputs high” condition for producing an output 1, the term exclusive - OR is derived. The logic symbol and the truth table of the input and single output XOR gate is shown in Fig 3.12(a) and TABLE 3.7 respectively.

Inputs Output
B A X

0 0 0

0 1 1

1 0 1

1 1 0
Table : 3.7 Truth table of EX-OR gate
Comparing the truth table of EX-OR gate with that of the OR-gate we see that they are similar upto third row but differs in the fourth row. For an EX-OR gate the truth table can also be remembered in the following way : With dissimilar inputs (i.e. for A = 1, B = 0 or for A = 0, B = 1) the output becomes High and for similar inputs (i.e. A = B = 0 or A = B = 1) the output becomes Low.

For exclusive ORing of many inputs the following rule may be remembered. “For even number of logic-1 inputs and also for all Logic-0 inputs the output is Low and for odd number of logic-1 inputs the output will be High”.

– –

The logic equation for the EX-OR gate can be written as X = A B + AB. The derivation of this equation will be given in the next chapter. There is a special symbol ‘☐’ to represent the exclusive OR operation. Using this symbol we may write the output of the EX-OR gate as C = A☐B with inputs A and B.

The equivalent electrical network explaining the EX-OR function is shown in Fig 3.12(b).

If the two switches SW1 and SW2 are placed in the positions according to Fig 3.12(b). SW1 = 1 and SW2 = 0 then the current will pass through the lamp and it will glow (equivalent to logic-1 output). Similarly, the lamp will glow if the switches are placed in the opposite direction (i.e. SW1 = 0 and SW2 = 1). However, if the positions of the switches SW1 and SW2 are either in 1,1 or 0,0 position then the lamp will not glow which is equivalent to the logic-0 output.

Response of the 2-input EX-OR gate to the time varying digital signal is shown in Fig
3.13 and the output signal is derived following the truth table of the EX-OR gate TABLE
3.7.

During (0 to t1) : Input A is 1 and input B is 0, output X is 1, according to the second row of TABLE 3.7.
During (t1 to t2) : Input A is 0 and input B is 1, output X is 1, according to the third row of TABLE 3.7.
During (t2 to t3) : Input A is 1 and input B is 1, output X is 0, according to the fourth row of TABLE 3.7.
During (t3 to t4) : Input A is 1 and input B is 0, output X is 1, according to the second row of TABLE 3.7.
During (t4 to t5) : Input A is 0 and input B is 1, the output X is 1, according to the third row of TABLE 3.7.
During (t5 to t6) : Input A is 1 and input B is 0, the output X is 1, according to the second row of TABLE 3.7.

3.2.7 Exclusive -NOR gate (EX-NOR or XNOR gate)

Similar to the XOR gate, this gate has two inputs and one output. For the logic symbol of this gate a bubble is put at the output of XOR gate showing that the XNOR gate output is inverse of the XOR output. The logic symbol and the truth table is shown in Fig 3.14(a) and TABLE 3.8 respectively.

Inputs Output B A X

0 0 1

0 1 0

1 0 0

1 1 1
Table 3.8 : Truth table of Exclusive NOR gate If we compare the truth table of XOR and XNOR gates, we can see that the output column of the XNOR is inverse that of XOR gate. The truth table for XNOR gate can be remembered in the following way : “With similar inputs (i.e. B = 0, A = 0 or B = 1, A = 1) the output of an EX-NOR gate is 1 and with dissimilar inputs (i.e. B = 1, A = 0 or B = 0, A = 1) the output is 0”.

The logic equation relating the output and the two inputs of an EX-NOR gate can be written as (the derivation of this equation will be given in the next chapter) X = AB + A–B– = A☐B = A • B.

The symbol • is used for EX-NOR operation between two variables A and B.

The equivalent electrical network realising the EX-NOR function is shown in Fig 3.14(b) by two SPDT switches. In this network, the open position (position 0) and the closed position (position 1) of the two switches SW1 and SW2 are connected as shown in Fig 3.14(b). When the two switch arms are connected either to (0,0) or to (1,1) then the current will be able to pass through the lamp and the lamp will glow (equivalent to the logic-1 output). The lamp will not glow if the switch arms of SW1 and SW2 are connected in the opposite directions. The response of this gate to the time varying digital inputs is shown in Fig 3.15. The output waveform can be obtained following the four rows of the truth table (TABLE 3.8) of this gate.

t
t

t

From the Fig.3.15 we can see that
During (0 to t1) : Input A is 0 and input B is 1, output X is 0, according to the third row of TABLE 3.8.

During (t1 to t2) : Input A is 1 and input B is 0, output X is 0, according to the third row of TABLE 3.8.
During (t3 to t4) : Both the inputs are 0, the output X is 1, according to the first row of TABLE 3.8.
During (t4 to t5) : Both the inputs are 1, the output X is 1, according to the last row of TABLE 3.8.
During (t5 to t6) : Input A is 1 and input B is 0, the output is 0, according to the second row of TABLE 3.8.

3.3 ENABLE AND INHIBIT PROPERTIES OF LOGIC GATES

Digital signal is nothing but a string of binary 1’s and 0’s overtime. The digital circuit which is the interconnections of several types of logic gates as discussed in the earlier section can be used to control the flow of this digital signal. When a logic gate does not allow the flow of the digital signal from its input to its output either in true form or in complemented form then the gate is said to be in inhibit State and when the gate allows the signal either in true or in complemented form to its output from the input then the gate is said to be in Enabled State. All the basic logic gates except the EXOR and EXNOR logic gates so far discussed has the property to enable or to inhibit the digital signals. In the following section these two properties of the basic logic gates will be discussed.

3.3.1 AND and OR Gate

We know from the truth table of AND gate (TABLE 3.9) that the output Y of the AND gate is always 0 if any one of the inputs of the AND gate is 0. Therefore, for a 2-input AND gate with inputs A and B if the input B is connected to the digital signal and the input A is connected to logic-0 then the output will be 0 and no signal will be available at Y i.e., the signal is inhibited as shown in Fig 3.16. On the other hand for the input A at logic-1, the output Y of the AND gate allow the digital signal from the input B to the output Y. This means that the AND gate is enabled if A = 1. This truth table (TABLE 3.9) is rearranged in TABLE 3.9 showing the condition of Inhibit and Enable for a 2-input AND gate.

Digital Control Outputat input - B
signal input

B A Y

0 0 0} Inhibit condition

1 0 0 Y = 0

0 1 0} Enable condition

1 1 1 Y = B

Table 3.9 Truth table of AND gate

For a 2-input OR gate if one input is connected to logic-1 then the output Y of the OR gate will always be at logic-1 and therefore any digital signal connected to the other input B will not be available at the output Y so long input a is at logic-1. This condition is the Inhibit Condition for the OR-gate. But the digital signal will be passed to the output Y when the input A is at logic-0. This condition is the Enable condition for the OR-gate. This is shown in Fig 3.17. The truth table of 2-input OR-gate (TABLE 3.3) is rearranged in TABLE 3.10 showing the Inhibit and Enable condition.

Digital Control Output signal input
B A Y 0 0 0 Enable Condition

1 0 1 (Y = B)

0 1 1 Inhibit Condition

1 1 1 (Y = 1)

Table 3.10 Rearrangement truth table of 2-input OR-gate
3.3.2 NAND and NOR Gate For a 2-input NAND gate if one input B is connected to a digital signal then this signal will be available in the complemented form at the output when the other input A of this NAND gate is at logic-1. This input condition is the Enabled condition of this NAND gate. When the input A is at logic-0 the output Y of this 2-input NAND gate will always be logic-1 and no signal will be allowed to pass to the output. This is the Inhibit condition for the 2-input NAND gate. This is shown in Fig 3.18 and TABLE 3.11.

Output Digital Control

signal input

B A

0 0

1 0

0 1

1 1

Ttable 3.11 Inhibit/Enable condition of NAND gate
Y

1} Inhibit Condition
1 (Y = 1)
1} Enable Condition
0 (Y = B)

We know that for a 2-input NOR gate if one input A is at logic-1 then the output Y will be always at logic-0 and ignore any variation at the other input B i.e. the digital signal if connected to the input B then this signal will be blocked if the input A is at logic-1. This is the Inhibit Condition of the 2-input NOR gate. On the otherhand, the digital signal at B will be complemented and will be passed to the output Y if the input A is of the 2-input NOR gate is at logic-0. This is called the Enabled condition of the NOR gate. This is shown in Fig 3.19 and the TABLE 3.12.

Digital Control Output

signal input

B A Y

0 0 1} Enable Condition

–

1 0 0 (Y = B)

0 1 0} Inhibit Condition

1 1 0 (Y = 0)

Table 3.12 Represents Enable/Inhibit condition of NAND Gate
3.3.3 EXOR and XNOR Gate Neither EXOR nor XNOR gate has an Inhibit Condition. The control input for both the gates acts only to determined whether the output waveform will be in or out of phase with the input signal. The truth table (TABLE 3.7) of XOR gate is rearranged in TABLE 3.13. This table shows two sections. The upper section of this table containing two rows indicate that the output Y is same as the input at B when A is at logic-0. The lower half of this table shows that the output is the complement of the input at B if the input A is at logic-1. Thus, this XOR gate can’t inhibit the signal connected input B but the output is true or complement of the input and this is controlled by the input A. Therefore XOR gate can be used as a controlled inverter. The action of the control input A on the digital signal at B is shown in Fig 3.20 for XOR gate.

Digital Control Output signal input
B A Y

0 0 0} Y = B

1 0 1_Enable condition

0 1 1} Y = B 1 1 0 Inhibit condition Table 3.13 Represents truth table of rearranged XOR gate Similar to the XOR gate the XNOR has no Inhibit property. It simply passes the digital signal connected to the input B without any inversion (i.e. without any phase change) if the other input A is at logic-1 then this XNOR gate will pass the signal with inversion if the other input A is at logic-0.

Summary of the Enable/Inhibit property of the logic gates is shown in the TABLE 3.14. Control AND OR NAND NOR XOR XNOR Input Gate Gate
– –
A = 0 Y = 0 Y = B Y = 1 Y = B Y = B Y = B
– –
A = 1 Y = B Y = 1 Y = B Y = 0 Y = B Y = B Table 3.14 Summary of the Enable/inhibit property of the logic gates.
3.4 ACTIVE LEVELS OF A LOGIC SIGNAL

We can observe from the previous discussions that all the logic gates follow a specific set of rules that define the outputs for different input combinations. The digital signals which are allowed at the inputs and the outputs have two states. Those logic states are represented by the symbols like “ON”or “OFF”, “TRUE” or “FALSE”, “HIGH” or “LOW” and “I” or “0”. It is a common practice to call the “ON” or “TRUE”, “HIGH” or “I” state as ACTIVE state and the “OFF” or “FALSE” or “LOW” or “0” state as INACTIVE state. Note that the active state does not necessarily mean the high voltage level nor does inactive state mean the low voltage level. The next two simple examples shall illustrate this point.

Explain the operation of the following two circuits shown in Fig 3.21(a) and Fig 3.21(b).

(a) If the switch SW for the circuit in Fig 3.21(a) is open, the output Y remains at 0V and the output jumps to +5V when the switch is closed and remains at +5V so long the switch is kept pressed. The output waveform for this circuit is shown in Fig 3.21(c). As the output Y for this circuit is high (+5V) when the switch is made active (pressed), therefore the output may be called active high.

(b) For the circuit in Fig 3.21(b), the output Y is normally high (+5V) when the switch SW is not pressed but the output is shorted to ground when the switch is pressed. As the output of this circuit goes low when the switch is made active (pressed), its output is said to be active low. The output waveform of this circuit is shown in Fig 3.21(d).

Comparing the actions of the two circuits of Example-1 we may summerize the following : 1. The output of the circuit in Fig 3.21(a) is normally low because of the normal open position of the switch but goes high when the switch is pressed i.e. is made active. It produces an activehigh output signal. The output signal is labelled as simply T i.e. without putting an overbar (–) on Y.

2. The output of the circuit in fig 3.21(b) is normally high and goes low when the switch is pressed i.e. is made active. The output signal is labelled as Y– i.e. with an overbar (–) on Y.

When the active state of a logic circuit corresponds to the most positive voltage in the system, Positive logic is indicated. This is the case for Fig 3.21(a). The circuit in Fig 3.21(b) employs Negative logic. In negative logic circuit the active state corresponds to the lowest voltage in the system. In common practice, the terms logic-1, logic-0 or the terms “HIGH” “LOW” are very much popular and not the terms “active” and “inactive”. When the signal Y is active, we say that it is in the logic-1(HIGH) state. On the other hand when Y– is active, we say that this signal is in the logic-0 (LOW) state. The logic levels and the nature of the output signals are summerised in the Fig 3.22.

In a digital circuit both positive and negativelogic signals are used. This means that some signals are activehigh but others may be activelow. This mixture of positive and negative logic leads to a term mixed logic.

The circuit designers follow one convention to identify the activehigh or the activelow inputs or outputs for a logic circuit. In the positive-logic convention, the activehigh connections are shown without any special symbol, however, the activelow inputs or outputs are indicated with a small circle or “bubble”. The bubble indicates that a particular input is “looking for” an activelow signal, or that particular output is activelow. This convention is shown in Fig 3.23(a) Fig 3.23(b) shows the polarity convention for conveying the same information. In this case a small triangle-called a polarity indicator is used to identify activelow inputs and outputs. Positive logic convention is the most popular. Therefore, in this book, we shall follow the positive-logic schemes.

3.5 LOGIC GATE DUALITY

Consider a truth table of a logic gate in terms of voltage levels of the signals applied to the gate inputs and measured at the outputs. This voltagelevel truth table may be interpreted using the positive-logic and negativelogic convention. These are tabulated in TABLE 3.15(b) and TABLE 3.15(c) respectively. For positive-logic the higher out of two voltage levels is considered to be logic-1 and on the contrary, in case of negativelogic the smaller out of the two voltage levels is considered to be the logic-1. The TABLE 3.9(b) is developed by putting ‘I’ for +5V and ‘0’ for 0V. So, this table represents a positive-logic. The TABLE 3.15(c) is developed by putting ‘1’ for 0V and ‘0’ for +5V. This table is for negative logic. From the TABLE 3.15(b) and TABLE 3.15(c) we may say that in view of the positive-logic, the voltagelevel truth table TABLE 3.15(a) indicates an AND gate (i.e. X = A.B) and in negativelogic, the same voltage-level truth table represents an OR-gate (i.e. X– = A– + B– with two active low inputs and an activelow output. X– = A– + B– can be proved to be equal to X = AB using a Theorem called De Morgan’s theorem (to be discussed in chapter 4). The logic symbols are shown besides the positive and negativelogic truth table. As a second example, consider a 3-input/1-output voltagelevel truth table as shown in TABLE 3.16(a). This table is translated into logic-level tables as shown in TABLE 3.16. (b) and (c) using positive-logic and negativelogic convention respectively.

Inputs Output Inputs Output Inputs Output
– – –
A B X A B X A B X
0V 0V 0V 0 0 0
1 1 1
0V +5V 0V 0 1 0
1 0 1

+5V 0V 0V 1 0 0 0 1 1

+5V +5V +5V 1 1 1 0 0 0

(a) (b) (c)

Table 3.15 (a) Voltagelevel truth table of a 2-input AND; (b) Positive logic truth table for Table (a); (c) Negativelogic truth table for Table (a)
Inputs Output Inputs Output Inputs– Output
– – – A B C X A B C X A B C X
0V 0V 0V 0V 0 0 0 0 1 1 1 1
0V 0V +5V +5V 0 0 1 1 1 1 0 0

0V +5V 0V +5V 0 1 0 1
1 0 1 0
0V +5V +5V +5V 0 1 1 1
1 0 0 0

+5V 0V 0V +5V 1 0 0 1 0 1 1 0

+5V 0V +5V +5V 1 0 1 1 0 1 0 0

+5V+5V 0V +5V 1 1 0 1 0 0 1 0
+5V+5V +5V +5V 1 1 1 1 0 0 0 0

(a) (b) (c)
Table 3.16 (a) Voltagelevel truth table of a 3-input AND; (b) Positive logic truth table for TABLE (a); (c) Negativelogic truth table for TABLE (a) The positive-logic table [TABLE 3.16(b)] can be implemented using a 3-input OR-gate (X=A+ B + C) and the negativelogic table [TABLE 3.16(c)] can be implemented by 3-input AND gate with inputs A
– – and C– and output X– = A– – – , B .B.C. This can be proved to be X = A + B + C by using DeMorgan’s theorem (to be discussed in chapter-4). So, we may say that the function realised in negativelogic is the dual of the function realised using positive logic and viceversa. Following this procedure we may say that each logic gate in a positive-logic has its dual in the negativelogic.

There are two simple rules that

will allow us to draw the logic gate

symbols in positive logic and

negativelogic.

1. Redraw the gate using the

opposite logic symbols. This

means AND gates become OR

gate, and OR gates become

AND gate.

2. Change the active sense of all

inputs and outputs to the

opposite type. This means that

activelow inputs and outputs

become activehigh and vice

versa.

3. For an inverter, change the position of the bubble from the output to the input and vice versa.

Fig 3.24 shows the equivalent logic representation for five logic gates in two logic systems. If a gate function causes some action when its output is 1, a gate without the bubble at the output is used. For example, the output of gate No.8 of Fig 3.24 goes to an activehigh state (no bubble), when both the inputs of this gate are at their activelow states (with bubble). Likewise, the gate representation that use OR logic will produce an active output level if any input is at its active state.

1. The output equivalent circuit of the following circuit is
[ISRO 2016]
(a) INVERTER, (b) AND, (c) OR, (d) NOR
2. The MOSFET circuit shown below is
(a) positive NAND, (b) negative NAND, (c) positive NOR, (d) negative NOR

3. A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON or OFF by any one of the switches irrespective of the state of other switch. The logic of switching of the bulb resembles, [GATE 2013] (a) an ANDgate, (b) an OR gate, (c) an XOR gate, (d) a NAND gate.

4. Which of the statement is true for the following circuit
(a) f is independent of x (b) f is independent of y (c) f is independent of z (d) None of x, y, z is redundant.

5. In the figure x1 = 1, and x2 = 1, the output Q remains
[GATE 2005] (a) at 1, (b) at 0, (c) at its initial state, (d) unstable
6. If x1 and x2 are inputs to the circuit shown in the following figure, the output Q is
[GATE 2005] (a)
x
1
☐
x
2
,
(b)
x x
1 2 , (c) x1.x2, (d) x1.x2
7. What will be the output of the following circuit, if point ‘P’ is stuck at ‘1’? [ISRO 2014]
(a) A+B+C, (b) A☐ ☐C (c) A.B.C (d) 0.
B
8. If input to the digital circuit shown below consisting of a cascade of 20 XOR gates is X, then the output Y is equal to
[GATE 2002]
(a) 0, (b) 1, (c) X , (d) X
9. In the following circuit the LED

(a) emits light when both S1 and S2 are closed,
(b) emits light when both S1 and S2 are open,
(c) emits light when only S1 or S2 is closed,
(d) does not emit light irrespective of the switch position.

10. The circuit shown in the figure converts

[ISRO 2017] (a) BCD to Binary code, (b) Binary to excess-3 code, (c) Excess-3 to Gray code, (d) Gray to Binary code.

11. The logic gate realizes the function
[GATE 2010]
(a) XOR; (b) XNOR; (c) Half adder; (d) Full adder
12. The CMOS circuit shown below implements the function
[ISRO 2017]
(a) (A + B)C; (b) (AB + C)+D ; (c) (A + B)C + D; (d) (AB + C)D
4.1 INTRODUCTION

The root of logical thinking with the concept of TRUE and FALSE dates back to the period of 384 to 322 B.C.- the life period of Greek philosopher Aristotle. The ideas of the subject of Aristotle were studied for many countries by many mathematicians to give a shape to these logic theories by using the conventional algebra. However, it was the English philosopher and mathematician George Boole in 1854 who solved Aristotle’s work and developed a strong mathematical logic. He published his famous work in a paper “An Investigation of the law of thought”. Now-a-days, this work is known as Boolean algebra, named after him, which is the actual foundation stone of the logic circuits used in computers and the digital systems. Though, George Boole developed the famous Boolean algebra in 1854 but until late 1930 no practical applications were made of it. In 1937 Nakashima in Japan and in the following year C.E. Shannon at Masschusetts Institute of Technology, used this algebra for the systematic analysis of relay switching circuits for meeting the large volume of relay circuit requirements to satisfy the rapidly growing telephone usage during that period. After that, the applications of Boolean algebra have expanded dramatically over the following years as digital systems have grown and finds more and more application in our world.

In this text we shall use the switching algebra which is most appropriate to the digital logic circuits because in switching algebra, a variable can be assigned with only two values, more commonly known as “0” or “1” but in actual Boolean algebra the variables had many values. Thus the switching algebra is actually a subset of Boolean algebra. Henceforth, we shall use the term “Boolean Switching Algebra”or in short “Switching Algebra ”instead of Boolean Algebra.

4.2 POSTULATES OF SWITCHING ALGEBRA

Some sets of self evident mathematical statements or propositions states without proof are called the postulates or the axioms. In 1904, E.V. Huntington [1874-1952] developed a set of postulates to define the Boolean Algebra and later on, it was seen that only six postulates of 8 9
Huntington were sufficient to define the two valued Boolean Algebra or the Switching Algebra.

For these six postulates we need only a set S = {X,+, ., –} where X is a two values variable or a constant of the algebra, the symbols (+) and (.) are binary operators and overbar (–) is a unary operator. The properties of these operators will be described later.– – A Boolean variable with or without overbar is called a literal. Thus X,Y X , Y and so on, are literals. Two or more literals connected by the operator, is called a term. For example X.Y.Z is a term, X + Y– is a term etc.

Now, we will give the list of postulates and will study the properties of these operators. Postulates • P1 For all elements X and Y in the set S
(a) X + Y is an element of S and (b) X.Y. is an element of S.
The above two parts of the postulates describe the closure property with respect to the operators “+” and “.”

P2 (a) There exists a constant 0 in S such that for every element X in S, X + 0 = X. This is zero axiom.
(b) There exists a constant 1 in S such that for every element X in S, X.1 = X. This is unit axiom.

P3 For all elements X and Y in the set S
(a) X + Y = Y + X and (b) X.Y. = Y.X
These two describe the communicative property with respect to the operators “+” and “.”

P4 For all elements X,Y and Z in the set S
(a) X. (Y+Z) = X.Y. +X.Z and (b) X + (Y.Z) = (X + Y) . (X+Z) These two describe the distributive property “.” over “+” and “+” over “.”

P5 For every element X in the set S, There exists an element X in the same set such that
(a) X +

–
X = 1 and (b) X. X– = 0
These two describes the Inverse property.
P6 There exist alteast two distinct elements in the set S.
Comparing the conventional algebra and the switching algebra, we find the following differences : 1. Huntington’s postulates do not include the associative law, but this law holds true for the switching algebra.
2. Postulates P4(b) is valid for switching algebra but not valid for the conventional algebra.

3. There is no additive or multiplicative inverses in the switching algebra, so there is no subtraction or division operation in switching algebra.

4. The concept of complement (postulates P5) is not available in conventional algebra.

5. Switching algebra is defined with two constants 0 and 1 which can be assigned to the switching variables but in the conventional algebra a variable can be assigned with infinite number of constants without restriction. Duality From the list of Huntington’s postulates, it is seen that each postulates has two parts (a) and (b) and we can go from one part to the other by interchanging (•) by (+) and 1 by 0. This property is called the duality property i.e. one part of the postulate is dual to other.

Let us formally define the dual of a logic function. If F(X1, X2,......XN, +, •, –, 1,0) is a logic function involving the variables X1, X2, ......XN, the operators +, • and –, and the constants 1 and 0 then the dual of F, written as FD, is the function with + and ‘ 1 and 0 swapped : FD (X1, X2 ...... XN, +, •, –, 1,0) = G (X1, X2,......XN, + •, –, 0,1) where the function G is the dual of F.
4.3 THEOREMS OF THE SWITCHING ALGEBRA
Let us use the postulates (P1 – P6) to prove some basic theorems which will be useful later. 4.3.1 Idempotent Theorem
For all element X in the set S,
(a) X + X = X and (b) X.X = X

Proof : (a) X + X = (X + X).1 ; using P1(a) (b) X.X = X.X + 0 ; using and P1 (b)
– and P2(b)– and P2(a) = (X + X).(X + X) ; using P5(a) = X.X+X.X ; using P5(b) = X + X.X– ; using P4(b) = X.(X + X–); using P4(a) = X + 0 ; using P5(b) = X.1 = X ; using P2(a) = X ; using P5(a) ; using P2(b) Here we can see that the two parts of the Idempotent theorem are dual to each other. 4.3.2 Boundaries Theorem or Closure of Identity Elements For all elements X in the set S,
(a) X + 1 = 1 and (b) X.0 = 0

Proof : (a) X + 1 = (X +1).1 ; using P2(b) (b) X.0 = X.0 + 0 ; using and P1(b)
– and P2(b)
= (X + 1). (X + X) ; using P5(a)
= X + 1. X– ; using P4(b)
= X + X– ; using P2(b)
= 1 ; using P5(a)
– and P2(a) = X.0 + X. X ; using P5(b) = X.(0 + X–) ; using P4(a) = X. X– ; using P2(a) = 0 ; using P5(b) 4.3.3 Equality Theorem For all elements X,Y and Z of set S, if X + Y = X + Z and X.Y = X.Z, then Y = Z

Proof : Y = 1.Y– ; using P2(b) = (X + X ).Y ; using P5(a) = X.Y + X–.Y ; using P4(a)–
= X.Z + X.Y ; since X.Y = X.Z = X.Z + X–.Y + 0 ; using P2(a)–
= X.Z + X.Y + X–.X ; using P5(b) = X.Z + X–.(Y + X) ; using P4(a)–
= X.Z + X.(X + Y) ; using P3(a) = X.Z + X–.(X + Z) ; since X + Y = X + Z = X.Z. + X–.X + X–.Z ; using P4(a) = X.Z + 0 + X–.Z ; using P5(b) = X.Z + X–.Z ; using P2(a) = Z. (X + X– ) ; using P4(a) = Z.1 ; using P5(a) = Z ; using P2(a) 4.3.4 Complement Theorem
(a) For all elements X and Y of set S
If X + Y = 1 and X.Y = 0, then X = Y
(b) If X be an element of set S, the complement of X, i.e. X
– and Y = X–.– is unique.

Proof : (a) X + Y = 1 = X + X–, using P5(a)
and X.Y = 0 = X.X–, using P5(b)
So, we have X+Y= X+ X– and X.Y = X. X
Using the Equality theorem we may now write Y = X–.

–
Similarly, if we start with X + Y = 1 = Y + Y, using P5(a)
–
and X.Y = 0 = Y. Y, using P5(b)
then we may write
–
X + Y = Y + Y
–
or, Y + X = Y + Y, using P3(a)– ... ... (4.1) and X.Y = Y. Y– or, Y.X = Y.Y, using P3(b) ... ... (4.2)
–
From Eqn(4.1) and (4.2) we may write using the Equality theorem X = Y. (b) Let us assume that the complement of X is not unique and has two complements, X– and Y. Then using postulates P5 we may write
X + Y = 1, X.Y = 0 ; assuming the complement of X to be Y.
and X+ X– = 1, X. X– = 0 ; assuming the complement of X to be X–.
We may write
X– = X–.1 ; using P2(b)
= X–.(X+Y) ; using P5(a) as X + Y = 1
= X–.X+ X–.Y ; using P4(a) = 0 + X –.Y ; using P5(b)
= X–.Y ; using P2(a) ... ... (4.3) Next, we may also write
Y = Y.1 ; using P2(b)

= Y. (X + X–) ; using P5(b)
–
= Y.X+Y. X ; using P4(a)
– = 0 + Y. X ; using P5(b) as xY = Y.X = 0
= X–.Y ; using P2(a) ... ... (4.4) Therefore, from Eqn (4.3) and (4.4) we may conclude that X– = X–.Y = Y
or, X– = Y
which contradicts the assumption that two complements of X are not unique. Hence, the complement of X is unique and it is X–.
4.3.5 Involution Theorem
It is also known as Double Negation Theorem. It is stated as follows : For any element X of set S, ( X–) = X,
Proof : Let X– = Y. Then ( X–) = Y–.
Using postulates P5 andP3 we may write
Y– + Y = 1 and Y–.Y = 0 = Y. Y–. ... ... (4.5) Also, we may write
X + X– = 1 and X.X– = 0 ... ... (4.6)
Using Eqn(4.5) and (4.6) we may write X + X – = Y + Y– and X.X– = Y. Y
or, X + Y = Y + Y– and X.X= Y. Y– since X– = Y... ... (4.6a) or, X + Y– = Y + Y and X.Y = Y–.Y

Using the Equality theorem to Eqn (4.6a) we get
–
X = Y
or, X = ( X–) since Y = X–.
4.3.6 Adsorption Theorem For all elements X and Y of set S
(a) X + X.Y = X and (b) X.(X+Y) = X
Proof : (a) X + X.Y = X.1 + X.Y ; using P2(b) (b) X.(X+Y) = X.X+X.Y ; using P4(a) = X.(1+Y) ; using P4(a) = X.1 ; using Boundness = X ; using P2(b)

= X + X.Y ; using Indempotent theorem
= X.(1+Y) ; using P4(a)
= X.1 ; using Boundness theorem
= X ; using P2(b)
4.3.7 Consensus Theorem For all elements X and Y and Z of set S
(a) X.Y + X–.Z + Y.Z = X.Y + X–.Z and (b) (X+Y). (X–+Z). (Y+Z) = (X +Y). (X– +Z) Proof : (a) X.Y + X–. Z + Y.Z
= X.Y + X–. Z + Y.Z.1 ; using P2(b)
= X.Y + X–. Z + Y.Z.(X–. X) ; using P5(a)
= X.Y + X–. Z + X–. Y.Z + X.Y.Z ; using P4(a)
= X.Y(1+Z) + X–. Z. (1+Y) ; using P4(a)
= X.Y.1 + X–. Z.1 ; using Boundness theorem = X.Y + X–. Z ; using P2(a) (b) (X + Y). (X–.Z). (Y+Z)
= (X+Y). (X–. Z). (Y+Z+0) ; using P2(a)
= (X+Y).(X–. Z).(Y+ Z +X.X–) ; using P5(b) = (X+Y).(X–. Z).(Y+ Z +X–). (Y+Z+X); using P4(b)
= (X+Y).(X+Y+Z).(X–. Z).(X–+Z +Y) ; using the terms and literals within the
= (X+Y).(X
– + Z)
terms.
; using Absorption theorem 4.3.8 Adjacency Theorem
For elements X and Y in set S
(a) X.Y + X.Y– = X and (b) (X+Y).(X+Y–) = X
–
Proof : (a) X.Y + X.Y (b) (X+Y) (X+Y
–
–) = X.(Y+Y –) ; using P4(a) = X + Y. Y ; using P4(b)

= X.1 ; using P5(a) = X + 0 = X ; using P2(a) = X ; using P5(b) ; using P2(a)

4.3.9 Simplification theorem or Elimination Theorem
For all elements X and Y in set S
(a) X.X–.Y = X+Y and(b) X.(X–+Y) = X.Y
Proof : (a) X.X–.Y
= (X+X–)(X+Y) ; using P4(b) = X+X (b) X.(X–+Y)– +X.Y
= 1. (X+Y) ; using P5(a) = 0 + X.Y = X + Y ; using P2(b) = X.Y 4.3.10 Associative Theorem For all elements X,Y and Z of the set (S)
(a) (X.Y).Z = X.(Y.Z)–AND form
(b) (X + Y) + Z = X + (Y + Z) –OR form The two parts of this theorem are dual to each other. Proof :
(a) (X.Y).Z

= (X.Y).Z + 0 ; using P2(a)
= (X.Y).Z + X + X–; using P5(b)
= [(X.Y).Z+X].[(X.Y).Z+X–] ; using P4(b)

= [X + (X.Y).Z] . [X– + (X.Y).Z] ; using P3(b) = [(X+X.Y).(X+Z)].[(X–+X.Y).(X–+Z)]; using P4(b) ; using P4(b) ; using P5(b) ; using P2(a)

= [(X.(X+Z)].[(X–+X).(X–+Y).(X–+Z) ; using P4(b) and Absorption theorem. X+XY = X
[X.(X+Z)] . [1.(X+Y).(X+Z)]
=☐☐☐☐☐ ☐☐☐☐☐☐☐ – + XY = (X– + X) (X–+ Y)X X +YZ ; using P5(a) and X
– + Y.Z) ; using Absorption theorem and P4(b)
= X. (X
= (X.X–) + X.(Y.Z); using P4(a) = 0 + X. (Y.Z) ; using P2(a) (b) (X+Y)+ Z
= [(X+Y) + Z].1 ; using P2(b)

= [(X+Y)+Z].(X+X–); using P5(a)
–

= [(X+Y)+Z].X+[(X+Y)+Z].X = [(X+Y).X+Z.X] + [(X+Y).X– +Z.X–] ; using P4(a) ; using P4(a)

= [(X+X.Y)+Z.X]+[X.X– +X–.Y+Z. X–] ; using P4(a)
= [X+Z.X] + [0 + X–.(Y+Z)] ; using P5(b) and Absorption theorem = X+ X–.(Y+Z) ; using Absorption theorem and P2(a) = X+X–.(Y+Z) + (Y+Z) ; using Concensus theorem
= X+(Y+Z).[X–+1] ; using P4(a)
= X+(Y+Z).1 ; using Boundness theorem
= X+(Y+Z) ; using P2(b) Prove the following identities algebraically.
(a) B+A– C = (A+B+C) (A–+B+C) (A–+B+C–)
(b) A– D + C–D +AB– = A–C–D +AC–D + AB–C– + AB–C + A–CD
where A,B, C and D are switching variables.

– – –
(a) RHS=(A+B+C).(A+B+C).(A+B+C)
– –
= (B+C) (A+B+C) ; using P4(b).(X+Y)(X+Z) = X+Y.Z
–
here X☐ B+C, Y☐ A and Z☐A
– – – –
= B+C.(A+ C) ; using P4(b); here X☐B, Y☐C,Z = A+ C.
– –
= B + C.A+ C + C ; using P4(a)
–
= B+C.A+ 0 ; using P5(b)
–
= B+C.A ; using P2(a)
–
= B+AC ; using P3(b)
= LHS
– – – – – – –
(b) RHS = ACD +ACD +ABC + ABC + ACD
– – – – –
= CD(A+A)+AB(C+C)+ACD ; using P4.
– – – – –
= CD + AB +ACD ; using P5; A+A = C+C = 1
– – – – –
= CD + AB + ACD + (AD) ; AD is Consensus term out of two terms
– –
CD & ACD
– – –
= CD + AB + AD(C+1) ; using P4(a)
– – –
= CD + AB + AD ; using Boundness theorem = LHS.
4.3.11 DeMorgan’s Theorem
For all elements X and Y of the set S
(a) (X.Y) = X +Y and (b) X+Y = X .Y
– –
Proof : (a) X.Y + (X + Y)
– – – –
= [X+(X+Y)].[Y+(X+Y)] ; using P4(b)
– – – –
= [(X+X)+Y)].[(Y+Y)+X] ; using Associative theorem (OR form)
– – = (1+Y ).(1+X) ; using P5(a)
= 1.1 ; using Boundness theorem = 1 ; using Idempotent theorem

–
Hence, X.Y = X + Y ; using P5(a) A+A=1
– –
(a) (X+Y).(X.Y)
– – – –
= X.(X.Y)]+Y.(X.Y)] ; using P4(a)
– – – –
= (X.X).Y+(Y.Y.X ; using Associative theorem (AND form)
– – = 0 +Y + 0.X ; using P5(b)
= 0 + 0 ; using Boundness theorem = 0 ; using Idempotent theorem

–
Hence, X+Y = X . Y ; using P5(b) A.A =0.
The generalised forms for DeMorgan’s theorem for N variables X1, X2,.....XN can be written as
(a)1X +X2☐X3☐....XN 1 2 3= X . X .X .....XN (b)
X .X .X
1 2 3☐....XN = X1+ X2☐X3☐ .....☐XN

These two parts can be proved using the two-step method called the finite induction– first, proving the theorem to be true for two variables (which has already been proved) and second proving that if the theorem is true for number of variables N = i, then it is true for N = i + 1 (the induction step). The above two parts of the Nvariable De Morgan’s theorem can be written as follows for a function F : – – – –
F(X ,X
1
2
, X
3
,...., X
N
,
☐,) = F(X1, X2, X3,...., XN,.,+)
– This states that, given any Nvariable logic function F, its complement F can be obtained by swapping (+) and (.) and complementing all variables. For example, suppose that we have a function – – F(X,Y,Z) = X .Y+ X.Y then by applying the generalised form of De Morgan’s theorem we get– –
F(X,Y,Z) = (X+Y).(X+Y)
by swapping all (+) by (.) and complementing all variables of F.

The generalised form of De Morgan’s theorem can be proved in the following way Proof : (a) Let F1 and F2 be the two partial functions of F. Then F can be expressed as F– F1 + F2 so,
F(X ,X
1
2
,....X
N
,
☐,.) = F (X , X1 2,....XN,☐ ☐2F (X , X2,..., XN,☐
,.) ,.) 1 1
Using De Morgan’s theorem to the right hand side we may write
F(X ,X1 2,....XN,☐,.) = F (X ,X1 2,....XN,☐2,.).F (X ,X2,...,XN,☐,.)
1 1
(b) Similarly, if the function F can be written as F = F1·F2 i.e.
F(X ,X
1
2
,....X
N
,
☐
,.) = F (X ,X ,....XN,☐ ,.) .F (X ,X

2 1 2,...,XN,☐,.)1 1 2
Using De Morgan’s theorem to the right hand side we may write F(X ,X1 2,....XN,☐,.) = F (X , X1 2,....XN,☐,.) ☐2F (X , X2,..., XN,☐,.) 1 1

Repeating the same procedure for F1 and F2 i.e. expanding F1 and F2 again into two partial functions until the complement of F is found by replacing each variable of the partial function (subpartial function) by its complements and at the same time, by interchanging the AND by OR operation. After De Morgan’s theorem is applied to every variable, the final result will be F(X ,X1 2,....XN ,☐,.) = F (X X ,...., XN,.,☐)1 1 2
Given A = B–.C+B.C– then show that
(i) A– = B.C + B–.C(ii) B = A–.C +A.C– (iii) C = A–.B+A.B

– –
(i) Given, A = B .C+ B.C
☐ A = B·C + B·C
=

☐
☐ ☐
B.C · B·C☐

– –
= (B + C). (B + C)
– –
= B.C + B.C
– –
(ii) Given A = B. C+ B . C
–
ANDing with C on both sides we get
– – – – –
A.C = B.C.C + B.C.C
– –
= B. 0 + B.C
–
= 0 +B.C
–
= B.C
We have proved in part(i) that
– – –
A = B.C + B .C
ANDing with C on both sides
– – –
A.C = B.C.C + B .C.C
–
= B.C + B.0
= B.C + 0 = B.C– –
OR A.C and AC we get
– – –
AC + AC = BC + BC
–
= B(C+ C)
= B.1 = B– –
☐ B = AC + AC
– –
(iii) Given A = BC + BC
ANDing both sides with B
– – – – –
A.B = B.C.B + B.C.B
– – – –
= B. B.C + B.B.C
– –
= B.C + 0.C
– –
= B.C + 0 = BC
Also, we have shown in part (i)
– – –
A = B.C + B.C
ANDing both sides with B
– – –
A.B = B.C.B + B.C.B
–
= B.C + 0.C
= B.C + 0 = B.C
– –
ORing AB and AB we get
– – –
AB + AB = B.C + B.C
–
= C.(B+ B)
= C.1 = C
– –
C = A.B + A.B
Find the complement of the following Boolean functions and reduce them with minimum number of literals.
(i)(B.C– + A–.D).(A B– + CD–)(ii) B–.D + A–.B.C– + A.C.D + A–.B.C
(i) (B.C + A.D).(AB + CD)
= (B.C + A.D) + (AB + CD)
= (B.C . A.D)+ (AB . CD)
– – – –
= (B + C). (A+ D ) + (A+ B).(C + D)
– – – – – – –
= AB + AC + B D + C D + A C + B C + A D + BD
– – – – – – –
= AB + A C + (B C) + BC + AC + AD + (CD) + CD + B D + BD ; using Concensus theorem– – – – (Concensus term from the terms AB, AC) (Concensus term from the terms AC, A D)
– – – – – – – – –
= AB + AC + C (B + B) + AC + AD + C(D + D) + B D + BD
– – – – – – –
= AB + A C + C + AC + AD + C + B D + BD
– – – – – – –
= AB + (C + C) + A C + AC + AD + B D + BD
– – – – – –
= AB + 1 + A C + AC + AD + B D + BD = 1
(ii) BD + ABC + ACD + ABC
= BD + AB(C + C) + ACD
–
= BD + AB + ACD; C + C = 1
– – – – –
= (B + D). (A+ B).(A + C+ D ), using DeMorgan’s theorem– – ...(4.7) =
(A+B
–). [D– + B(A–+ C–)], using P4(b). There are 6 literals (A,A,B,B– –
,C,D).
From Eqn(4.7) we may also write
– – – – – –
(AB + AD + BD) (A + C + D)
– – – – – – – –– –– – –– – ––
= AB A + ABC + ABD + AD A + AD C + ADD + BDA + BD C + BD
– – – – ––– – – – ––
= 0 + ABC + ABD + 0 + ACD + AD + ABD + BC D + BD
– – – – – – –
= B D (A + C + 1) A D (B + C + 1) ABC
– – – –
= B D .1 + A D . 1 + AB C
– – – –
= B D + A D + A B C
– – – – – –
= D (A + B) + ABC, there are 5 literals (A,B,B,C,D).
Reduce the following functions using De Morgan’s theorem.
(i) X = [(AB).A] . [(AB).B]
(ii) X = (A+B+C) (AB +CD)☐BCD)
(iii) X = (ABC+ BCD)☐(ACD☐BCD + BCD)
(i) X = [(AB)A] [(AB).B](ii) X = (A + B + C) (AB + CD + BCD)
=
(AB).A + (AB). B–
–
–
–
–
= [(A+B+C) +(AB☐CD) . (BCD)
– – – – –
= (A + B). A + (A + B).B = [(A+B + C) + (A+B + C+D)].(BCD)
– – – – – – – –
= AA + AB + AB + BB– = [(A+A) +(B+B)+ C+D].(BCD)
– – – – –
= AB + AB; A A = 0, B B = 0 = (1+1+ C + D). (BCD) = 1.BCD = BCD
(iii) X = (ABC + BCD) +(ACD☐ BCD + BCD)
= (ABC + BCD).(ACD☐ BCD + BCD)
– – – – – – – –
= (ABC + BCD). (A + C + D + BCD +BCD)
– – – –
= (ABC + BCD) [A+ C(1 +BD )+ D (1+ BC)]
– – – –
= (ABC + BCD) (A + C + D)
– – – – – – – – –
= ABC. A + ABC. C + ABC. D + BCD. A + BCD.C + BCD.D
– – – – – – –
= 0 + 0 + ABC D + BCD.A + BCD + 0 ; AA = CC = DD = 0
– – –
= ABCD + BCD(A+1)
– –
= ABCD + BCD
Simplify the following expression using theorems.
(A + B). (A + A–. B–) .C + A–.B + ABC + A(B +C)
– – ––
(i) (A + B).(A + AB). C + AB + ABC + A(B+ C)
– –– = (A+B).(A+B ).C + AB + ABC + A(B + C) ; using Elimination Theorem = AC + AB + ABC + A(B + C) ; using Adjacency Theorem = AC(1+B) + AB + A(B + C) ; using P4(a) – – = AC + A B + A + BC ; using De Morgan’s Theorem and Boundness Theorem.– –
= AC + AB +A ; BC is the Consensus term of – – AC and AB = AC + A (B +1) ; using P4(a) = AC + A– ; using Boundness Theorem –
= AC + A + C ; using Concensus theorem
–
= A + C ; using Absorption theorem
4.4 CANNONICAL FORMS OF SWITCHING FUNCTIONS

We have already introduced the term “literal” and we also know that a switching expression means an expression formed with literals and operators (+), (.), (–). There are two ways to represent an expression.

(a) The sum-of-product (SOP) representation.
(b) The product-of-sum (POS) representation.
4.4.1 The SOP Representation
Consider a function of three variables
– – –
F(X,Y,Z) = X.Y+X.Z + X.Y.Z
This function is written as a Boolean sum (OR) of three product (AND) terms (i) X.Y (ii) X.Z
– and (iii) X– – .Y .Z and each term is formed by ANDing the literals. The ANDed terms are also called the product-terms (p-terms). The SOP representation of a function means “Boolean sum of the ANDed terms”. In this example, F is a function of 3 variables X,Y and Z. The first and second term contains two variables and the third term contains all the three variables. The ANDed term in the SOP expression in which all the variables of a function are present either as complemented or as uncomplemented form is called a MINTERM.

Notice that in the above example, X
– –.Z is a minterm but X.Y and X.Z– .Y are simple terms but not the minterms. A function composed of a logical sum (OR) of only minterms is said to be in CANONICAL or STANDARD SOP. Typical examples are given below.

– – – – – – – – – – – – – – –
F1 (X,Y,Z) = XYZ + XYZ + XYZ + XYZ, and F2(W,X,Y,Z) = W X Y Z + W X Y Z + W X Y Z .

The function F1and F2 are two functions of three and four variables respectively and all the terms, according to definition, are minterms (also called standard product terms). Hence, the two functions will be called canonical. It is known that it is possible to generate eight minterms like X
– – – , X––Z, X–YZ– , X–YZ,XY––,XY–Z,XYZ– Y Z Y Z and XYZ using three variables. In general, a function with N number of variables, the total number of possible minterms are 2N. In the above two examples the functions F1 and F2 contains only 4 and 3 minterms out of 8 and 16 possible minterms respectively. It means that F1 and F2 contains only 4 and 3 minterms out of 8 and 16 possible minterms respectively. It means that F1 and F2 are “true”i.e. the functional value will be 1 only for those minterms present in the functions and “false” i.e. the functional value will be 0 for the rest of the possible minterms. We shall use “mi” to represent the ith minterm. This minterm depends on the variables of the function like X,Y,Z etc. and the value of i depends on the decimal equivalent number of the minterm and the decimal equivalent number is calculated using the following logic variable codes.

Complemented variables of the minterm is assigned with 0.
Uncomplemented variable of the minterm is assigned with 1
Once the 0’s and 1’s have been assigned to all variables following this coding rule in a given minterm, a minterm code is established where the subscript i becomes the decimal equivalent of the binary code. As an example, the minterm X–YZ– of the function F1 is represented by

– –

X Y Z = m2
☐ ☐ ☐
0 1 0 = 2

since 010 has a decimal value of 2. A complete minterm code table for three variables is given in TABLE 4.1. A similar minterm code table can be constructed for any number of variables.

Minterm Binary Decimal mi– – –
XYZ 000 0 m0– –
XYZ 001 1 m1– –
XYZ 010 2 m2–
XYZ 011 3 m3– –
XYZ 100 4 m4–
XYZ 101 5 m5–
XYZ 110 6 m6
XYZ 111 7 m7

Table 4.1 : Minterm code table for 3 variable minterms
A canonical SOP form can also be expressed using decimal notation of the minterms. For example, the function F1(XYZ) = X–YZ– + XYZ– + X–YZ + XYZ can be written as F1 = m2 + m6 + m3 + m7

Generally, the minterm list is written either in the ascending form or in the descending form based on the decimal equivalent value of the minterms. So, the function F1 can be written either as F1 = m2 + m3 + m6 + m7
or, as F1 = m7 + m6 + m3+ m2
Another shortcut method of writing F1 in terms of minterm codes is F1 = ☐m(2,3,6,7) or, ☐(2,3,6,7)
m
This means that the function F1 is the sum of minterms whose decimal equivalent codes are 2,3,6 and 7. With the same arguments the function F
2
= X
––– + X– – + XY––
YZ YZ Z can be written in the forms
F
2
=
☐
m
(0,2,4)
or,
=
☐(0,2,4)
m

Write down the following canonical SOP functions using the decimal notation of minterms.
(a) F
(c) F

–YZ– + XY–Z + XYZ (b) F2(XY) = XY– + X–Y1 (X,Y,Z) = X – X Y– Z + W– X Y Z + W X– Y – Z + W X Y– Z3 (W,X,Y,Z) = W

– – –

(a) F1 (X,Y,Z) = X Y Z + X Y Z + X Y Z
☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐

0 1 0 1 0 1 1 1 1
= m2 + m5 + m7
= ☐m(2,5,7) – – (b) F2(X,Y) = X Y + X Y
☐ ☐ ☐ ☐
1 0 0 1

= m2 + m1
= m1+ m2
= ☐m(1,2) – – – – – – – – – – (c) F3 (W,X,Y,Z) = W X Y Z + W X Y Z + W X Y Z + W X Y Z + W X Y Z ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ 0 1 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0

= m4 m6 m7 m9 m12 = ☐m(4,6,7,9,12) If you are very much familier with the decimal notation of writing a function you may directly write the final step without going through the earlier steps as shown in the above examples.

4.4.2 The POS Representation
Consider a function of three variables as given below
– – – – F(X,Y,Z) = (X +Y).(X+Z).(X+Y+Z)– – The function is written as a Boolean product (AND) of three sum (OR) terms (i) X+ Y (ii) X– + Z and (iii) (X+Y+Z–).The sum terms are formed by ORing the literals. The sum terms are also called S-terms in short and the expression is called the product-of-sum expression or product of the ORed terms”. The ORed term in the POS expression where all the variables of a function are present either as complemented or as uncomplemented form is called the MAXTERM. So, according to the definition, the term X + Y + Z– is a maxterm and the other two terms (X–+Y–) and (X– + Z) are not minterms because the variables Z and Y are absent in these two ORed terms respectively. A function composed completely of a logical AND of maxterms is said to be in CANONICAL or STANDARD POS. Typical examples are given by the following functions.

– – – – – – – –
(i) F3 (X,Y,Z) = (X + Y + Z). (X + Y + Z) . (X + Y + Z) .(X + Y + Z).
– –
(ii) F4 (W,X,Y,Z) = (W+X+Y+Z).(W+X+Y+Z). (W+X+Y+Z), etc.

All terms of the functions F3 and F4 are maxterms (or standard sum terms).Thus, two functions F3 and F4 will be called the canonical or standard POS. As in the case of minterms, for a 3-variable function there may be maximum 8 possible maxterms. Those possible maxterms are X–+Y–+Z–, X–+Y–+Z, X–+Y+Z–, X–+Y+Z, X+Y–+Z, X+Y–+Z, X+Y+Z– and X+Y+Z. In general for a Nvariable function there will be 2N possible maxterms. So, the above two functions F3 and F4 might contain maximum 23 = 8 and 24 = 16 maxterm as F3 and F4 are functions of 3 and 4 variables respectively. We shall use the symbol “M1” to represent the ith maxterm. The value of i is a decimal equivalent number of a binary code evaluated as follows : Complemented variables of maxterm is assigned with 1.
Uncomplemented variables of maxterm is assigned with 0.

The assignment of the 0’s and 1’s in this way to all variables in each maxterm establishes the maxterm code. The maxterm code table for four variable is presented in TABLE 4.2.

Maxterm Term Binary Decimal Mi A+B+C+D 0000 0 M0
A+B+C+D– 0001 1 M1
A+B+C

–
–+ D 0010 2 M2 A+B+C
–
+D 0011 3 M3 A+B
– – + C+D 0100 4 M4 A+B+ C+D– 0101 5 M5 A+B

– –
–+C + D 0110 6 M6 A+B
+ C
– – +D 0111 7 M7–
A +B + C+D 1000 8 M8–+ B + C+D–
A 1001 9 M9–+B + C–
A +D 1010 10 M10– –

A+B+ C+D
– 1011 11 M11–+B–
A + C+D 1100 12 M12– –
A+ B+ C+D
A
A+B+C+D
– 1101 13 M13–+B–+C–+ D 1110 14 M14– – – – 1111 15 M15
Table 4.2 : Maxterm code table for four variables A canonical POS can be represented using a decimal notation instead of writing the full expression using literals. For example, consider a canonical POS form of a function.
– – – – – – – F(X,Y,Z) = (X+Y +Z). (X+Y+Z).(X+Y+Z).(X+Y+Z)
We may write the function F using the maxterm symbols as follows
F(X,Y,Z) = M2.M4.M3M7 = M2.M3.M4.M7 = ☐M(2,3,4,7) The symbol☐ means that the function F is the logical product of the maxterms whose decimal equivalent codes are 2,3,4 and 7.
Write the following canonical POS function using maxterm decimal codes.

(a) Q(X,Y,Z) = (X+Y+Z –).(X+Y–+Z–).(X+Y+Z).(X–+Y+Z–).(X–+Y–+Z–)
(b) R(A,B,C,D) = (A–+B+C–+D).(A–+B–+ C+D).(A–+B– +C–+D).(A–+B–+C–+D–) (c) S(U,V,W,X) = (U+V+W+X–).(U+V– +W+X).(U– +V+W– +X–).(U– +V+W– +X).(U–+V–+W+X–).

– – – – – – – – (a) Q(X,Y,Z) = (X + Y + Z).(X + Y +Z). (X + Y + Z). (X+ Y +Z). (X+ Y + Z) ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ = (0 0 1) (0 1 1) (0 0 0) (1 0 1) (1 1 1) = M1 · M3 · M0 · M5 ·M7 = ☐(0,1,3,5,7) – – – – – – – – – – – (b) R(A,B,C,D) = (A + B + C + D). (A + B + C + D).(A + B + C + D).(A + B + C + D) ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ = (1 0 1 0) (1 1 0 0) (1 1 1 0) (1 1 1 1) = M10· M12 · M14 · M15 = ☐M(10,12,14,15) (c) S(U,V,W,X) =
– – – – – – – – – – (U + V + W + X ).(U+ V + W+ X). (U + V + W + X). (U + V + W+ X).(U + V + W + X) ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ ☐ (0 0 0 1) (0 1 0 0) (1 0 1 1) (1 0 1 0) (1 1 0 1) = M1 · M4 · M11· M13 = ☐M(1,4,10,11,13)
Write down the canonical POS expression using literals for the following functions (a) F(A,B,C,D) = ☐M(0,5,8,9,11,12,15) and (b) F(X,Y,Z) = ☐M(3,4,6)
(a) F(A,B,C,D) = ☐M(0,5,8,9,11,12,15)
= M0. M5. M8. M9. M11. M12. M15
– – – – – –
= (A+ B +C+ D). (A+ B + C + D). (A+ B + C+D).(A+ B + C+D).(A+B+C+ D)
– – – – – – – – – – = (A +B +C+ D).(A+ B+ C+D).(A+ B+ C+ D)
(b) F(X,Y,Z) = ☐M(3,4,6)
= M3 . M4 . M6

– – – – –
= (X+Y+Z).(X+Y+Z).(X+Y+Z).
If all the maxterms are present in a canonical POS function (e.g. in a 3-variable function, there may be 8 maxterms) then the functional value of F will be 0. This type of function is called a null function. This can be shown as follows :
F(X,Y,Z) = ☐M(0,1,2,3,4,5,6,7) ; if all possible maxterms are present in F.
– – – – – – –
= (X+Y+Z).(X+Y+Z).(X+Y+Z).(X+Y+Z).(X+Y+Z).(X+Y+Z)
– – – – –
(X+Y+Z).(X+Y+Z)
– – – – – – – –
= (X+Y+Z.Z).(X+Y+Z.Z).(X+Y+Z.Z).(X+Y+Z.Z)
– – – –
= (X+Y+0).(X+Y+ 0).(X+Y+0).(X+Y+0)
– – –
= (X+Y).(X+Y).(X+Y).(X+Y)
– – –
= (X+Y.Y) (X+Y.Y)
–
= (X+0).(X+0)
–
= X.X = 0 ; Adjacency theorem has been used repeatedly. This can be generalised for N variable function as follows
= ☐M(0,1,2....2N–1)
2N-1
=
i
☐ Mi = 0
= 0
1. The Boolean expression
–
(X+Y)(X+Y) + (XY)☐X simplifies to [GATE 2014] (a) X; (b) Y; (c) XY; (d) X+Y 2. Let☐ denotes XOR operation. Let 1 & 0 denotes the binary levels. Consider the following Boolean expression for F over two variables P and Q.
F(P, Q) = ((1 ☐ P)☐ (P☐ Q))☐ ((P☐ Q)☐ (Q☐ 0)) [GATE 2014]
(a) P + Q; (b) P☐Q; (c) P☐ Q; (d) P ☐Q 3. The Boolean expression below simplifies to
(A☐ B☐ AB) (A☐ C☐ AC)
(a) A +BC; (b) B +AC; (c) ABC; (d) AB +C
5. The number of literals after simplification of the following expression is
– – –
(W + Y + Z)(W + Y +Z)(W + Y +Z)(W +X)
(a) 2; (b) 3; (c) 4; (d) 1
4. The truth table for implementing a Boolean variable F is given by [ISRO 2012]
Where d represents don’t care states. The minimized expression for F is
– – – – – (a) B C + AC + AB (b) AB + C (c) ABC + AB–C– + ABC (d) None of above 6. The expression (ab + bc +ca)(a ☐ b☐ c) simplifies to
(a) a + b +c; (b) abc; (c) ab + bc; (d) ab + c 7. The number of distinct Boolean expression of 4 variables is [GATE 2003]
(a) 15; (b) 256; (c) 1024; (d) 65536 8. In the logic equation
A( A+ B–C + C) +

– –
B
–

( C + A + BC)(A +B
– –C+ AC) = 1, if C = A then, [DRDO 2009]
– – (a) A + B =1; (b) A + B = 1; (c) A + B = 1; (d) A = 1 9. The Boolean function F(A, B, C, D) = ☐(0,6,8,13,14) with don’t care conditions
d(A,B,C,D) = ☐(2,4,10) can be simplified to–– [DRDO 2008]

–– – – – –
(a) F = BD + CD–+ ABC (b) F = BD + CD + ABCD
– – – – – – (c) F = A BD + CD + ABC (d) F = BD + CD + ABCD 10. Write a Boolean expression for Z in terms of A, B, C, D, E. You need not simplify the expression
[ISRO 2010]
(a) [{(A + B) (D E)} +C] (b) [{(A B) + (D + E)}C]
(c) [{(A B) + (D + E)}C] (d) False 5

SIMPLIFICATION OF

BOOLEAN EXPRESSION

5.1 INTRODUCTION

In the preceding chapter the simplification of Boolean expression was performed using theorems. Sometimes it becomes tedious and difficult to get the simplified form of the switching expression using theorems. In this chapter, the graphical method will be introduced for simplifying logic expressions. The graphical method was developed be M. Karnaugh in 1953*. This map technique is much easier to use and less error prone than the algebraic simplification techniques. In this method the minterms or maxterms are displayed in a geometric pattern so that all the logically adjacent terms are visibly apparent. Minimization, therefore can be accomplished by recognizing the basic patterns on the map. This technique can be used for any number of variables but it can be used comfortably for 4-variable switching functions, another technique called Quine McClusky method can be used. This is nothing but a tabular method. Henceforth, the Karnaugh map will be called as K-map and Quine Mc Clusky method will be called QM method in this text.

5.2 FORMATION OF KARNAUGH MAP FOR SWITCHING FUNCTIONS
5.2.1 One Variable Karnaugh map (First order K-map) Karnaugh map provides a group of square boxes arranged in a particular way. Each box represents a minterm (or maxterm). So, the total number of boxes in a map depends on the number of possible minterms (or maxterms) which can be formed with the variables present - * Karnaugh, M – “The map method of synthesis of combinational logic circuits”, Trans. AIEE, Comm. and Electronics, Vol 72, Part I, pp. 593-599, Nov 1953.
109
in the function. With a single variable we can have two minterms. Those minterms are
–
X (= m0) and X(= m1). So, in a one-variable K-map there will be two boxes. We can place the two boxes in two different possible ways as shown in Fig 5.1(a) and (b).
Fig 5.1: Format of a one-variable k-map
– Two boxes are labelled with the two possible variations of the variable X i.e. with X and X. The labelling may also be done with the binary codes of X– and X i.e. 0 and 1 as shown in Fig 5.1(c). The boxes in the figures are identified with the minterms m0 and m1. The presence and the absence of minterms in a function can be indicated by putting 1s and 0s in the respective minterm boxes. One important point may be noted from the figures is that the two boxes are not only physically adjacent but they are also logically adjacent.

To explain the procedure of mapping a one-variable function we take the help of the following examples.

Map the following truth tables in the K-maps.
X F1(X) X F2(X) X F3(X)
0 0 0 1 0 1
1 1 1 0 1 1

Fig 5.2 : Truth table for functions F1(X), F2(X) and F3(X)
(a) F1(X) = X i.e. F1(X) = m1. It means that the function F1 has only one variable minterm X( = m1). So, 1 is mapped in the box identified for m1 and 0 in the other box because the minterm m0 is absent in the function F1(X). This is shown in the following figure.

– –

(b) For the function F2(X) we may write F2 (X) = X. Thus, the minterm X(= m0) is present and X(= m1) is absent. So, 1 and 0 are mapped in the boxes for m0 and m1 of the one-variable K-map. This is shown in the following figure.

–

(c) The function F3(X) can be written as F3(X) = 1 = X + X. This indicates that both the minterms m0 and m1 are present in the function. The presence of the minterms m0 and m1 have been indicated in the K-map by putting 1 in both the boxes as shown in the following map.

Fig 5.3 : Coordinates of the second-order K-map (a) X and Y represent the horizontal and vertical axes (b) X and Y represent vertical and horizontal axes.

5.2.2 Two-variable Karnaugh map (Second order K-map)

A two-variable K-map or a second order K-map is again a graphical representation of a two-variable switching function F(X,Y). This map indicates the logic values (either 0 or 1) of the function for every combination of the two X and Y. We know that with two variables there may be a maximum of four combinations of the variables. These combinations may be either in the

form of product terms (X
– –, X–Y, XY–
Y
and XY) i.e. minterms or in the form of sum terms (X+Y, X+Y
– –+Y and X–
, X
– +Y ) i.e. maxterms. Therefore, we need four boxes (sometimes called cells) in the map for placing 1 or 0 to indicate the presence or absence of the minterms. On the otherhand, for maxterms, 1 and 0 are placed in the boxes to indicate the absence or the presence of maxterms in the given function respectively. The boxes are so arranged that they are not only physically but are also logically adjacent. The minterm (or maxterm) boxes are said to be logically adjacent if there is a change of only one literal between the boxes. Two possible placements of the four boxes are shown in Fig 5.3(a) and (b) to maintain the logical adjacency. The top-left box with coordinate X = 0 and Y = 0 is for minterm m 0
(= X
–– Y ) or for the maxterm M0(=X+Y), the top-right corner box (X= 0, Y=1) of Fig 5.3(a) is for minterm M1(= X + Y–) ; box (X =1, Y = 0) on the bottom left corner is for minterm m2 ( = XY–) or for maxterm M2 (= X– + Y) and the box (X = 1, Y= 1) of bottom-right corner is for minterm m3 (= XY) or for maxterm M3 (X + Y). In Fig 5.4, the boxes are indicated by the respective minterms (or maxterms). The equivalent decimal number of the minterms (or maxterms) are written at the bottom-right corner of each box. The information regarding the logical adjacency of any 2-variables function is shown in TABLE 5.1

Minterm (Maxterm) Adjacent Minterms (Maxterms) are m0(M0) m1, m2(M1, M2) m1(M1) m0,m3(M0,M3) m2(M2) m0, m3(M0,M3) m3(M3) m1,m2(M1,M2) Table 5.1

In Fig 5.4 the box for m0 is logically adjacent to the box for m1 and m2 because between the boxes m0 and m1 there is a change of only one literal i.e. Y and similarly the boxes m0 and m2 are logically adjacent because between the boxes m0 and m2 there is a change of the literal X. But, the boxes for m0 and m3 and also the boxes for m1 and m2 are not adjacent logically because there will be change of both variables, X and Y if we go from one box to the other. With this observation we may verify the entries of TABLE 5.1. From the 2-variable K-map it is seen that there are two logically adjacent boxes for each box. In general, we shall see that in a Nvariable K-map there will be N adjacent boxes for any box in the map.

To map a two-variable function in a K-map we have to find out all the minterms (or maxterms) of the function and then have to put 1 (or 0) in the boxes for those minterms (or maxterms) which are present and 0 (or 1) in the boxes for those minterms (or maxterms) which are absent in the function.

Map the following truth tables in the K-maps.
(i) F1(X,Y) = ☐m(2,3) (ii) F2(X,Y) = X–, (iii) F3(X,Y) = ☐M(0,2)
(i) F1 (X,Y) = ☐m(2,3).
The function F1 (X,Y) has two minterms m2 and m3. So, put 1 in the boxes for m2 and m3 and 0s in the boxes for m0 and m1.

–
(ii) F2 (X,Y) = X

– –

–=X(Y+Y)
=XY + X– –
Y
= m1 + m

0

Fig 5.4 Two varibale K-map with boxes indicated by the minterms

(or maxterms) for F(X,Y)

The function F2(X,Y) has two minterms m0 and m1. So put 1 in the boxes for m0 and m1 and 0s in the boxes for m2 and m3.
Instead of finding the minterms of the function F2(X,Y) we could have plotted this functions directly just by observing the function. As this function F2(X,Y) is true only when X = 0, so we can put 1s in those boxes of the map where the label of the boxes has X = 0 irrespective of Y. In this case the top row of the map has only label X = 0, so the two boxes of this row of the K-map are filled with 1s for the given function F2 (X,Y) = X– and the remaining two boxes are filled with 0s.

(iii) F3 (X,Y) = ☐M(0,2)

In the function F3, the maxterms M0 and M2 are present. So,

put 0 in the boxes for M0 and M2 and 1 in the boxes for M1 and

M3.

Plot the following functions in the K-map.
(i)F1 (X,Y) = X+Y (ii) F2(X,Y) = X– + Y

–
(i) F1 (X,Y) = X + Y = M0 or, F1 (X,Y) = XY + XY + XY
= ☐
m(1,2,3).

In this function only one maxterm M0 is present (or m1,m2 and m3 minterms are present). Therefore, we have to put a 0 in the box with label (X = 0, Y =

0) and 1s in three boxes.

– – – – – –
(ii) F2 (X,Y) = X + Y = M3 or F2(X,Y) = XY + XY + XY = ☐m(0,1,2).

In this function only one maxterm M3 is present (or m0, m1

and m2 minterms are present). Therefore, put 0 in the box with

label (X = 1, Y = 1) and 1s in other three boxes.

Plot the following truth table in K-map.
X Y F
0 0 1

0 1 0
1 0 1
1 1 0

The function is at logic-1 for X = 0, Y = 0 and for X = 1, Y = 0. So, put 1s in the boxes with coordinate X = 0, Y = 0 and X = 1, Y = 0 and fill up the other boxes with 0s. This is shown below.

5.2.3 Three-Variable Karnaugh Map (Third order K-map) Similar to the two-variable K-map, a three-variable K-map gives us the visual indication of the presence and the absence of the minterms (or maxterms) of a three variable function F(X,Y,Z). The number of boxes in this map are eight because we know that there may be 23 = 8 minterms or maxterms using three variables,X,Y and Z. With the previous knowledge of first and second-order K-maps, one would reasonably expect that for three variables the graphical display should be three dimensional, that is, one axis for each logic variable. This three dimensional graph can be used but this representation is difficult to construct and to use this three dimensional graph for minimisation (the minimisation technique will be discussed next). There is a much better way for drawing a third-order K-map as shown in Fig 5.5. The Fig 5.5 shows two possible formats for the third order K-map.

Fig 5.5 : Two commonly used formats for the third-order K-map In both the formats the variable X is considered to be the most significant and Z as the least significant variable of the given function. The decimal equivalent number of the minterms are shown at the bottom right corner of each box. The shape of the two formats are different because of the placement of the variables around the diagonal line drawn at the top left corner. The vertical and the horizontal axes have been represented by the possible binary values of the variable or a group of variables. In the format of Fig 5.5(a), X represents the hoirzontal axis with two possible values 0 and 1 and YZ represents the vertical axis with values 00,01,11 and 10. Similarly, in Fig 5.5(b), the horizontal axis is identified by XY with values 00,01,11 and 10 and the vertical axis of Z with values 0 and 1.

The striking difference between the second and the third order K-map lies in the sequence of the binary values on the twoliteral axis YZ in Fig 5.5(a) and XY in Fig 5.5(b).The twoliteral axis of Fig 5.5 is coded using 2-bit unit distance code. Owing to this type of coding any box becomes logically adjacent to the boxes having common edge with it either vertically or horizontally. If the rectangular map is formed into a cylinder by joining the left and right vertical end edges of the K-map then the left most and right most boxes in a row

become logically adjacent because they differ only in one variable. Similarly, the boxes of top row and bottom row are also logically adjacent column wise. Fig 5.6 identifies the boxes of a third order K-map using minterms and maxterms.

Fig 5.6 : Third order K-map boxes indentified by minterms and maxterms While mapping a three-variable function F(X,Y,Z) in a third-order K-map, we have to find out the minterms (or maxterms) present in the function and then we have to put 1s (or 0s) for those present minterms (or maxterms) in the boxes of K-map idenitified for those terms as shown in Fig 5.6. The absent minterms (or maxterms) are indicated by 0 (or 1) in the boxes.

The logical adjacency information of the boxes of a three variable K-map are given in the TABLE 5.2.

Minterm(Maxterm) Is adjacent to Minterms (Maxterms) m0(M0) m1,m2,m4(M1,M2,M4) m1(M1) m0,m3,m5(M0,M3,M5) m2(M2) m0,m3,m6(M0,M3,M6) m3(M3) m1,m2,m7(M1,M2,M7) m4(M4) m0,m5,m6(M0,M5,M6) m5(M5) m1,m4,m7,(M1,M4,M7) m6(M6) m2, m4,m7(M2,M4,M7) m7(M7) m3,m5,m6(M3,M5,M6) TABLE 5.2
Map the following three functions in a suitable K-map. (i) F1 = ☐m(4,5,6,7) (ii) F2 = ☐m(0,2,4,6)
The maximum decimal equivalent number in the list of minterms for F1, F2 and F3 is a greater than 3 but less than or equal to 7. Thus, plotting for these functions requires third order K-map.
(i) F1 = ☐m(4,5,6,7)

In Fig. 5.7(a) the boxes for m4, m5, m6 and m7 are filled up

with 1s as these minterms are present in the function F1 and

the rest of the boxes are filled with 0s as the minterms m0, m1,

m2 and m3 are absent.

☐m(0,2,4,6)
(ii) F2 =

The boxes for m0, m4 and m6 are filled with 1s as these

minterms are present in the function F2 and the rest of the

boxes are filled with 0s. This is shown in Fig5.7(b).

Map the following functions in suitable K-maps.
(i) F1 = A–BC + AB–C– + ABC
(ii) F2= (A+B+C) (A–+B+C) (A+B+C–) (A–+B–+C–)
(iii) F3= A+BC
In this example, all the functions F1, F2 and F3 are functions of three variables A,B and C. Therefore, for mapping of these functions we need third order K-maps.
– – – (i) In function F1, there are three minterms, ABC = m3 ABC = m4 and ABC = m7. So, the boxes for the minterms m3, m4 and m7 are filled up with 1s and the rest of the boxes with 0s as shown in Fig 5.8(a).

– –
(ii) In function F2, there are four maxterms A+B+C = M0 A+B+C = M4 , A+B+C = M1 and
–+B–+ C–
A = M7. Therefore, the boxes for M0,M1M4 and M7 are filled up with 0s and the rest of the boxes with 1s as shown in Fig 5.8(b).
(iii) The function F3 is not in standard form. This function can be expressed in standard SOP form as follows :
F +B).(C+C) +(A+A_)BC3 = A(B
– –
= ABC +AB +AB C + ABCC + ABC
Thus, it is seen that the function F3 contains 5 minterms m3,m4,m5,m6 and m7

. The function is plotted in Fig 5.8(c) by putting 1 in the boxes 3,4,5,6 and 7 and 0s in the boxes 0,1 and 2.

Fig 5.8(a) Fig.5.8(b) Fig 5.8(c)

The function, F3 may also be plotted without transforming the function into a standard SOP form. In this function there are two terms (i) A and (ii) BC. The first term does not depend on the variable B and C but, the function F3 is true whenever A = 1. This condition can be satisified by putting 1s in the boxes where A is 1 irrespective of variable B and C. This is the bottom row of the map. Similarly, for the term BC, we have to put 1s in the boxes only where B = 1 and C = 1 irrespective of A. This is shown in the third column from left. If we follow this method then 1 appears twice in the box of m7 but only one 1 has been kept there. This is done because we know that in Boolean algebra 1+1=1.

5.2.4 Four-variable Karnaugh Map (Fourth order K-map)

We are familiar with the two formats for first, second and the third order K-map. Following the above procedure, we can also present the two commonly used formats for the fourth order K-map as shown is in Fig 5.9. In this figure, both the axes of the map are coded with the 2-bit unit distance code, 00, 01, 11, 10 so that in any row, the 2 boxes that have a side in common are logically adjacent because they differ by only 1columnvariable and in any column, the 2 boxes that have a side in common are logically adjacent because they differ by only 1 row-variable. In any row, the right most cell is logically adjacent to the left most cell because columns with codes 00 and 10 differ by one variable Y as shown in Fig 5.9 and similarly in any column the top box is logically adjacent to the bottom box because rows with codes 00 and 10 differ only by one variable W. In a 4 variable K-map any group of 4 boxes that have a side in common are also logically adjacent. The 16 boxes of the 4-variable K-maps in Fig 5.9(a) are identified by the minterms m0,m1....m15. Out of 4 map variables W,X,Y and Z the variable W is the most significant and Z is the least significant variable. The boxes of the 4-variable K-maps representing 16 maxterms are shown in Fig 5.9(b).

Fig. 5.9 (a) Fig. 5.9 (b)

The information of logical adjacency of four boxes within the map is shown in TABLE 5.3. Pairing or clustering of two logically adjacent boxes means OR-ing of the minterms (ANDing of the maxterm) of those two boxes. Hence, we get a product term (sum term) having only 3 variables from those two boxes after pairing. Because one variable which changes its state between two boxes is eliminated due to this pairing. Further, two pairs of logically adjacent boxes can be combined into a cluster of 4 boxes called a quad, provided that a box in one pair is logically adjacent to a box in the other pair. These will be explained while we will study the minimisation of the switching functions using maps.

Minterms (Maxterms) Adjacent Minterms(Maxterms)
m0(M0) m1,m2,m4,m8(M1,M2,M4,M8)
m1(M1) m0,m3,m5,m9(M0,M3,M5,M9)
m2(M2) m0,m3,m6,m10(M0,M3,M6,M10)
m3(M3) m1,m2,m7,m11(M1,M2,M7,M11)
m4(M4) m0,m2,m7,m11(M0,M5,M6,M12)
m5(M5) m1,m4,m7,m13(M1,M4,M7,M13)
m6(M6) m2,m4,m7,m14(M2,M4,M7,M14)
m7(M7) m3,m5,m6,m15(M3,M5,M6,M15)
m8(M8) m0,m9,m10,m12(M0,M9,M10,M12)
m9(M9) m1,m8,m11,m13(M1,M8,M11,M13) m10(M10) m2,m8,m11,m14(M2,M8,M11,M14)
m11(M11) m3,m9,m10,m15(M3,M9,M10,M15)
m12(M12) m4,m8,m13,m14(M4,M8,M13,M14)
m13(M13) m5,m9,m12,m15(M5,M9,M12,M15)
m14(M14) m6,m10,m12,m15(M6,M10,M12,M15)
m15(M15) m7,m11,m13,m14(M7,M11,M13,M14) Table 5.3

Map the following function in suitable K-maps.
(i) F1 = ☐m(0,2,3,7,8,9,10,11,13)
(ii) F2 = ☐M(0,5,8,9,11,12,15) (iii) F3= WXYZ– + W–X–Z + XY–Z + WX–YZ + XYZ +
WX–Y–Z–+ W–XY–Z
(i) Largest decimal number of the minterm

of F1 is greater than 7 and less than 15. So, for mapping

this function we need a four variable map. Consider

the four variables to be W,X,Y and Z, where W is the

most significant variable and Z is the least significant

variable. Mapping of F1 is shown in Fig.5.10(a). The

minterms m0, m2, m3, m7, m8,m9, m10, m11,m13 are

present in the function F1. Therefore, we fill-up the

corresponding minterm boxes with 1s and the

remaining boxes with 0s for the absent minterms.

(ii) For plotting the function F2 we need a 4-variable

K-map because the decimal code for the maxterm is

maximum 15. The maping is done by filling up the

appropriate maxterm boxes with 0s and the remaining

boxes with 1s to indicate the present and absent

maxterms respectively. This is shown in Fig 5.10(b).

(iii) Express the function F3 in the form of a

canonical SOP. For each present minterm of F3 put 1

and for absent minterm put 0 in the appropriate

minterm boxes of a 4-variable K-map with map

variables W,X,Y and Z.

F3 = WXYZ + WXZ + XYZ + WXYZ + XYZ + WXYZ
+ WXYZ
= ☐m(1,3,5,7,8,11,13,14,15); F3 is in canonical SOP expressed using decimal codes of the minterms.
This function is mapped in the 5.10(c).
5.3 SIMPLIFICATION OF SWITCHING FUNCTIONS USING KARNAUGH MAPS
5.3.1 Introduction In section 5.2 we have learned to plot the switching functions (upto four variables) in Karnaugh maps. From the map we observed that “Any two adjacent boxes in the map differ by only one variable i.e. one variable is with overbar (primed) in one box and without overbar (unprimed) in the adjacent box.” This way of mapping is done to obtain a quick visual identification of the logically adjacent terms of the function. For example, the minterms m 1
( = X
––Z) and m3 (= X– Y YZ) lie in two adjacent boxes [Fig 5.9(a)] because they differ in variable Y only. When these two minterms boxes are combined (i.e. algebraically ORed together) we will get a product term consisting of two literals X and Z with Y absent. This is nothing but the application of the Adjacent theorem in the map. Similarly, when two adjacent maxterm boxes are combined it is equivalent to ANDing of two maxterms then it causes a removal of the changing variable in the two adjacent boxes. For example, in a 3-variable map the boxes for M5 and M7 are adjacent. The only variable Y differs in the two boxes because M

–
5
= X
+ Y
+ Z
– and M7 = X– + Y– –
+ Z. So, Y can be removed when these two maxterm boxes are combined i.e. ANDed. This can be verified by using the Adjacency theorem as follows :– – – – – – –
M5· M7 = (X+Y+Z) · (X+Y+Z) = X+ Z

From these two examples we may conclude that a larger group of logically adjacent boxes of minterms (maxterms) give rise to a product (sum term) with smaller number of literals. In general, for a Nvariable map if 2M (where M = 1,2....,N) logically adjacent boxes are combined the then combination gives rise to a term with (N–M) number of literals. There are two guidelines for a judicious selection of group of the minterm(maxterm) boxes in a K-map.

1. The size formed with a group of logically adjacent minterm (maxterm) boxes should be as large as possible. This guideline follows from the fact that larger the number of minterm (or maxterm) in a group fewer will be the number of literals in its product (or sum) term after the combination.

2. A minimum number of groups should be used. This guideline stems from the fact that each grouping of minterms (or maxterms) corresponds to a product (or sum) term and consequently the number of terms in the expression, can be kept to a minimum.

This type of solution with minimum number of terms with the minimum number of literals in each term is called the minimal solution. From the following examples we will see that the minimal solution is not always unique. In the following sections, several examples will be given to use the K-maps of 2–, 3– and 4– variables for the simplification of the switching functions. Each example will be explained in detail so that we may understand the systematic procedure for getting the minimal solution.

5.3.2 Simplification of 2-variable Function Using a Second-Order K-map

To illustrate the use of the second order K-map for the simplification of the switching function, let us start with the function F(X,Y) = ☐m(0,1,2). This function is mapped in second-order K-map as shown in Fig 5.11(a). Using algebra, we can simplify this function.

F(X,Y) =☐m(0,1,2) = m0 + m1 + m2
– – – – – – – – – –
= XY + XY + XY = (XY+ XY)+(XY+XY); sharing m0, with m1 and m2.
– – The reduced form of F(X,Y) = X +Y shows that the number of terms in the function is reduced from 3 to 2 and the number of literals in the terms is reduced from 2 to 1. The reduced term X– is the outcome of the combination of two logically adjacent minterms (m0,m1) and Y– is produced due to the combination of (m0,m2) which are also logically adjacent.

In a K-map, the logically adjacent boxes filled up with 1s can be grouped together to get the reduced product term and the logically adjacent boxes filled with 0s can be grouped to get the reduced sum term. In Fig 5.11(a) the box for m0 is logically adjacent to the boxes of m1 and m2. Thus, the box for m0 with an entry 1 can be combined with the boxes for m1

Fig 5.11(a) Fig 5.11(b) and m2 having 1 in them to get the reduced product term. The standard practice is to encircle the logically adjacent boxes to show the formation of a group as it is shown in Fig5.11(b). When the logically adjacent boxes are circled, they are said to be covered. To identify the different groups of the adjacent boxes we may use some alphabetic symbols like p1, p2, p3 etc. for the group of 1s (i.e.group of logically adjacent maxterms boxes of the kmap).

In Fig 5.11(b) we have two groups p1 and p2. The reduced term for p1 and p2 can be obtained by removing the variable which is complemented in one box and uncomplemented in the other, within the circled group. For example, in the p1 group, the variable Y changes from Y– to Y but X remains as X–. Therefore, strike out the literal Y– from the minterm m 0
= X
– – and Y from m1 = X–Y to get p1 = X– Y . Similarly, we can strike out X from m0 = XY and X from m2 = XY– to get p2 = Y–. Finally, the minimal form of the function F(X,Y) can be obtained by ORing the reduced terms of the two groups p1 and p2. Therefore, the minimal sum from F(X,Y) is p1+p2 = X–+Y–.

It may be noted in Fig 5.11(b) that while looping the boxes of minterms, m0 is shared by both the groups of p
1
and p
2
. This is equivalent to sharing of the product term X
– – Y (= m0) with m1 ( = X–Y) and m2 (=XY– ). Though, the box for m0 has been shared with m1 and m2 i.e. the box m0 is common in both the groups of p1 and p2 but m1 and m2 are looped only in one way with m0. The group of two logically adjacent boxes is called a Pair or Daid. Thus, p1 and p2 are Pairs or Daids.

Map the function F(X,Y) = ☐m(0,3) in a K-map and find out the reduced sum form if possible.
The function F is plotted in two variable K-map
with 1s in the boxes for m0 and m3 and 0s in the boxes for m
1
and m2. This is shown in Fig 5.12. In this map, two boxes m
0
and m3 are not logically adjacent. Therefore, they cannot be
combined and hence the result is

– –

F(X,Y) = m0 + m3 = XY + XYFig 5.12

The boxes with 1s which cannot be combined in any way with other logically adjacent are called Isolated box or Island or Monad. The monads are encircled in an isolated way. In this example there are two monads m0 and m3 in Fig 5.12.

Find the minimal POS form for the function F(X,Y) = ☐M(1,2,3)

The function is mapped by filling the boxes for M1, M2 and M3 with 0s and the remaining box with 1. It is shown in Fig 5.13(a). For finding the minimal POS expression we have to search for logically adjacent boxes filled up with 0s and to cluster them. The two groups s1 and s2 are shown in Fig 5.13(b). In the group S1, the variable X changes its state but Y remains in the true form therefore the reduced sum term out of this clustering of 0s gives s1 = Y–. Similarly, the other group of two gives S2 = X– as the variable Y changes its state but X remains in the true form. The minimal POS form is F(X,Y) = S

1
S
2
= Y
– – .X.
Map the function F(X,Y) = ☐m(0,1,2,3) and find out the minimal SOP form of this function.
All the four boxes of the 2-variable k-map are filled up with 1s indicating that all the minterms are present in the function. This is shown in Fig 5.14(a).

In this figure, each box has its two logically adjacent boxes filled up with 1s. The adjacent boxes with 1s form a group -of-four boxes called a Quad. In this quad we can see that both the variables X and Y change their logic state as they move horizontally or vertically from box-to-box within the quad. We may say that four 1s are continuosly adjacent because in this figure we can write m0☐m1☐m2☐m3☐m0where an arrow between two minterms mi

and mj indicates the logical adjaceny. For a 2-variable K-map a quad produces 1 because the total number of variables in the function are two (N=2). This can be verified using boolean algebra as follows : –– – – – – – –
F(X,Y) = m(0,1,2,3) = XY + XY + XY + XY = X(Y + Y) X(Y +Y) = X + X = 1 Let us summarise the different possible groups of minterms (or maxterms) in a second order K-map for the minimal solution.

Possible Monads : When any minterm (or maxterm) box cannot find its logically adjacent box to form a group then this box is called a Monad. The maximum number of monads in a 2-variable map may be two when the 1s (or 0s) are placed in the diagonally opposite boxes.

Possible Diads : When any box can be looped with its logically adjacent box to form a group-of-two that group it is called a Diad. The pair of boxes which can form the distinct possible diads in a 2-variable K maps are (0,1), (0,2),(3,1) and (3,2) where the decimal numbers represent the minterm-box or maxterm-box numbers.

Possible Quads : In a second order K-map a quad may be formed only in one possible way i.e. in case, when all the four boxes are filled up with 1s (or 0s). In case of a quad of four minterms in second order K-map the result becomes unity and for four maxterms the quad results is zero.

From the examples cited in this section it is observed that to get the smallest number of literals in a product-term(or sum-term) the size of the cluster of 1s (or 0s) of logically adjacent boxes should be made as large as possible and to have minimum of terms in an expression the total number of clusters should be minimum. Expression consisting of minimum number of product terms (or sum-terms) having minimum number of literals in each term is called a minimal SOP (or POS form).

5.3.3 Simplification of 3-variable Function Using Third-order K-map

In this section we shall learn to get the minimal solution of a 3-variable function using a third order K-map. In a third order K-map there are 8-boxes and the possible groups may be monads, diads, quads and octet (the group of 8 boxes). The minimal solution may be expressed either in SOP form using the different groups of 1s or in POS form using the different groups of 0s.

Let us consider an illustration to get the minimal solution of a 3-variable function F(X,Y,Z) = ☐m(2,3,6,7).

The function F(X,Y,Z) = ☐m(2,3,6,7) is plotted in a third order K-map by putting 1s in the boxes for the minterms m2,m3m6 and m7 and 0s in the rest of the four boxes. This is shown in Fig 5.15(a).

Fig 5.15(b) and (c) show how the minterm boxes can be combined to form diads following the Adjacency Theorem. It can be observed that any box containing 1 can be combined in two ways with their adjacent boxes e.g. m3 with m2 or m7; m2 with m3 or m6 etc. The possible groups are shown in Fig 5.15(d). A ring of diads is formed by combining the boxes in this manner. In this situation, the four boxes are said to be continuously adjacent and we can cover these four 1s using a single bigger loop which is called a quad. This is shown in Fig 5.15(e). Within this quad, the logic state of the variable Y does not change but that of X and Z changes from box to box. The reduced term generated out of this quad is same as the literal which does not change in the quad. In this case it is Y. This can be verified as follows using boolean algebra.

F(X,Y) = m2 + m3 + m6 + m7
– – –
= XYZ + XYZ + XYZ + XYZ
– – –
= XY(Z + Z) + XY (Z+Z)
– – = X Y + XY = Y(X+X) = Y ...(5.1) If we follow the looping schemes as shown in Fig 5.15(b), (c) and (d) we will get the following reduced forms : –
From Fig 5.15 (b) we get two product terms, p1 = XY and p2 = XY ...(5.2)
–
From Fig 5.15(c) we get two product terms, p1 = YZ and p2 = YZ ...(5.3)
–
From Fig 5.15(d) we get four product terms, p1 = XY, p2 = XY
– p3 = YZ and p4 = YZ ...(5.4) From Fig 5.15(e) we get one term p = Y ...(5.5) The Eqn 5.2, 5.3 and 5.4 show that they are partially reduced. In Eqn, 5.2 and 5.3 there are two product terms each with two literals. In Eqn 5.4 there are four terms each with two

literals. In Eqn.5.5 there is one term with one literal Y. Hence, p = Y is the minimum solution. From this example we may conclude that “Instead of taking the smaller groups of minterm/ maxterm-boxes one should always try for the largest valid group of logically adjacent boxes because the largest possible valid group gives a term with the smallest number of literals”.

Find out the reduced SOP and POS expression for the function F(X,Y,Z) =☐m(0,2,4,6)
The function is mapped as shown in Fig

5.16. In this figure we can observe that there are two

quads - (i) a quad of 1s and (ii) a quad of 0s. The formation

of the quad with 1s is not self evident from the picture

but two boxes in a row positioned at two extreme ends

are also logically adjacent.
Fig. 5.16 Thus
(i) the box for minterm m0 is logically adjacent to the box for minterm m2 because there is a change of logic state of Y only.

(ii) the box minterm m4 is logically adjacent to the box for minterm m6 because there is a change of logic state of Y only.
(iii) the box for m0 is adjacent to the box for m4 and the box for m2 is adjacent to the box for m6. Therefore, we can say that the four boxes is this figure containing 1s are all adjacent logically.
To obtain the reduced SOP form, the four 1s can be looped together as shown with the solid line in the figure. Within this quad, the variable Z does not change its logic state (it remains in the complement form) but either of the two variables X and Y changes their state whenever the boundary lines of the boxes are crossed horizontally or vertically starting from any box within this quad. So, the reduced term out of this quad of 1s is Z– and the reduced SOP form of the function F(X,Y) = Z–. This can also be verified using boolean algebra as follows :
p = m0 + m2 + m4 + m6

–– – – –– – – – – – – –– – – – –
= XYZ + XYZ + XYZ + XYZ = XZ(Y + Y) + XZ(Y+Y) = XZ + XZ = Z(X+X) = Z

For finding the reduced POS form, one has to loop the logically adjacent boxes which are filled up with 0s. It is shown with the dotted line in Fig 5.17. In this quad of 0s, the logic state of the variable Z does not change but it remains in the true form. The reduced POS form is S = Z–. This part can also be proved algebraically using Adjacent theorem. The ANDing of the maxterms M1, M3, M5 and M7 means – – – – – –
S = M1.M3.M5.M7 = (X+Y+Z).(X+Y+Z)(X+Y+Z).(X+Y+Z)
– – – –
= (X+Z) (X+Z) = Z .
Find out the reduced SOP and POS expression for the function F(X,Y,Z) = X–Y–Z +XY–Z + XYZ using K-map.
The given function is plotted in Fig 5.17. The two K-maps of fig.5.17(a) and Fig 5.17(b) are exactly indentical but they are repeated to show the group of 1s and the group of 0s seperately.
–
In Fig 5.17(a), we have two diads, p1 and p2 where p1 = YZ and p2 = XZ.

–
The reduced SOP form of F(X,Y,Z) = p1 + p2 = YZ + XZ.
In the Fig 5.17(a) it is noted that the box m5 has been shared by both the diads p1 and p2. This is allowed as explained in Sec 5.3.2.

In Fig 5.17(b), a quad with the maxterm boxes M0, M2, M4 and M6 and a diad with the boxes M2 and M3 are indicated. In this figure the box for M2 has been shared by the quad and the diad because a box with 0 can be thought of AND of many 0s (0..0.0 = 0) therefore, a box with 0 can be shared many times with other boxes filled with 0s. The reduced form of the quad is S1=Z. The reduced POS expression of the diad is S2 = X + Y_. Therefore, the reduced POS form of the function can be written as F(X,YZ) = S2.S1 = (X+Y–).Z.

Find out the reduced SOP and POS form of the function F whose output is described by the following truth table.
X Y Z F

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1
1 0 1 1 Fig 5.18
1 1 0 0
1 1 1 0

The truth table is mapped in a third-order K-map. 1s are put in the boxes for m2,m3,m4 and m5 ans 0s are put in M0, M1, M6 and M7. This is shown in Fig 5.18. The 1s and

0s are encircled using solid and dotted lines for convenience. The product terms out of the two diads are p1 = X–Y and p2 = XY– as shown in Fig 5.18. The reduced SOP form of the function F is p1 + p2 = X–Y + XY–.

The 0s in the boxes for M0 and M1, give a reduced sum term S1 = X+Y. Similarly, the 0s of–
the boxes M–. The reduced POS form of the function F is6 and M7 give S2 = X + Y
S1· S2= (X+Y)(X–+Y–).

5.4 SOME DEFINITIONS

From the previous examples it may be concluded that a bigger clustering of minterms (or maxterm) boxes of a K-map leads to a product (or sum) term with fewer number of literals. But sometimes it becomes difficult to get the bigger groups simply by the visual inspection. It needs some judicious selection procedure for the identification of the bigger groups for the minimal solution. Before describing the selection procedure we define certain terms which are necessary for the description of the procedure.
5.4.1 Definition –1 : Implicant and Implicate (a) Implicant : For a Boolean function F expressed in SOP form, a product term p is an Implicant of the function F if and only if F = 1 for every combination of the input values to the variables of the product term p, for which p = 1.

If F = WX + YZ then show that the product term p = WXY– is an implicant of F. The product term p = 1 for W = 1 and Y = 0. These input values of the product
–
term variables makes F = WX + YZ = 1.1 + 0.Z = 1. So, the product term WXY is an implicant of the function F = WX +YZ.

(b) Implicate : For a Boolean function, F is expressed in POS form, a sum term ‘S’ is an Implicate of the function F if and only if F = 0 for every combination of the input values to the variables of the sum term for which S = 0.

If F = (X+Y–+Z) (X–+Y–+Z), show that S = Y–+Z is an implicate of the function F. The sum term S = 0 for Y = 1 and Z = 0. These values of the variable of the sum
– –
term make F = (X+0+0). (X+0+0) = X.X = 0. So, the sum term Y + Z is an implicate of the function F = (X+Y–+Z) (X–+Y–+Z).

Implicants or Implicates can easily be found from the K-maps. For illustration, let us consider an example of a 3 variable K-map in which a function F(X,Y,Z) = ☐m(1,2,3,6,7) is mapped. It is shown in Fig 5.19(a). We know that any minterm implies a function i.e. a function F becomes 1 for any of its minterm. Thus, the function F = ☐m(1,2,3,6,7) has 5 implicants which are all minterms of this function.

Fig 5.19
–– – – – – These possible implicants in terms of variables are X YZ, XYZ, XYZ, XYZ and XYZ. Similarly, any maxterm of a functon is the implicate of the function because F = 0 for any of its maxterm. Thus, the maxterms M0 = X+Y+Z, M4 = X–+Y+Z and M5 = X–+Y+Z are implicates of this function.

Besides the minterms (or maxterms), any term out of the logical ORing (or logical ANDing) of two or more minterms (or maxterms) will also be implicant (Implicate) of the function. Fig 5.19(b) and Fig 5.19(c) show five diads i.e. X–Z,X–Y,YZ–,XY and YZ and one quad i.e. Y for the function F (X,Y) are all implicants of the function. It can be easily verified using algebra and using the definitions of Implicant (or Implicate) that all the reduced terms obtained from the K-map are also the implicant (or Implicate) of the function. The 5 reduced terms out of the diads of the Fig5.19(b) implying the function are contained partially or completely in a larger group which also implies the same function. For example, in Fig 5.19(b) the diads p2, p3,p4 and p5 are all partially overlapped though they are all individually implicant of the function. Also, the diads p2, p3,p4 and p5 are all completely enclosed within a bigger loop i.e. quad p as shown in Fig 5.19(c). This quad is also an implicant of the function.

Thus, we may conclude that “Any valid (i.e.monad, diad, quad and other higher order groups) obtained from a K-map of a function F is an Implicant (or Implicate) of the function F. These valid groups may be isolated, partially overlapped or completely overlapped within a group of similar size or a group of bigger size.”
5.4.2 Definition -2 : Prime Implicant (or Prime Implicate) An Implicant (Implicate) of a function F is a Prime Implicant (or Prime Implicate) of F if it is not completely enclosed in bigger valid group of minterms (or maxterms) in the K-map.
Fig 5.20

For example, consider three K-maps shown in Fig 5.20(a), (b) and (c). If the Fig 5.20(a) and (b) are checked carefully, then it can be seen that all the circled group-of-1s are valid Implicants of the mapped function but no groups are included completely into another. So, according to the definition-2, all the Implicants shown in Fig 5.20(a) and 5.20(b) may be called the Prime Implicants (PI). In Fig 5.20(a) the PIs are Y,XZ– and X–Z and in Fig 5.26(b) the PIs are YZ
–, XY, XZ, Y–Z, X– – and X– –
Y Z. But if we check the Fig 5.20(c) it can be observed that the diads p2 and p3 are completely inside the bigger loop i.e. inside the quad p1. So XZ and
–
XZ are simply Implicants of the mapped function, but not the prime implicants. The prime implicant in Fig 5.20(c) is p1 = Z.
5.4.3 Definition-3 : Essential Prime Implicant (or Essential Prime Implicate) A prime Implicant (or Implicate) of a function F is an Essential Prime Implicant (or Essential Prime Implicate) of F if the loop for prime Implicant (or Implicate) contains at least one minterm (maxterm) box that is not contained in any other prime Implicant (or Implicate) loop of F.

Consider the Fig 5.20(a). In this figure the minterm m1 is contained only in the loop p3 and not in any other loops i.e. the minterm m1 is covered only in way by the loop p3. So, the product term p3 i.e. X–Z is an essential prime implicant (EPI) of F. Similarly, the minterm m4 of the loop p2, m2 and m7 of the loop p1 are covered only in one way i.e. they are not contained in other prime implicant loops so the product term out of p1 i.e. Y is an EPI and –Z is another EPI of F obtained from loop p2. But if we consider the Y is an EPI and X– X Z is another EPI of F obtained from loop p2. But, if we consider the loops of Fig 5.20(b), it may be noted that each minterm box is contained in the two loops e.g.

the minterm m0 is contained in the loops p6 and p5,
the minterm m1 is contained in the loops p5 and p4,
the minterm m2 is contained in the loops p6 and p1,
the minterm m5 is contaiend in the loops p4 and p3,
the minterm m6 is contained in the loops p1 and p2,
the minterm m7 is contained in the loops p2 and p3.

Therefore, according to the definition 3 none of the loops is an EPI. Such prime implicants for this function are called cyclic prime Implicants and the K-map for such a function is called cyclic PI K-map.

5.4.4 Definition-4 : Distinguished Minterm (Maxterm)

Any island i.e. any isolated minterm (or maxterm) of F or any minterm (or maxterm) of EPI not contained in any other prime Implicant (Implicate) loop of F is called a Distinguished Minterm (Maxterm) of F.

In the Fig 5.20(a) the distinguished minterms are m1, m2, m4 and m7. The boxes of the distinguished minterms are marked with stars in Fig 5.20(a).
5.4.5 Definition-5 : Optional Prime Implicant (Implicate) Optional Prime Implicants (or Implicates) (OPI) are those PIs which are used for alternative minimum cover.

In some K-map we may find some minterm (maxterm) boxes which can be combined with other logically adjacent boxes in more than one way. In Fig 5.21(a) and Fig5.21(b) it is seen that the minterm m0 can be combined either with m1or with m2. These two combinations give two alternative simplified solutions for the same function shown below.

Fig 5.21
– – ––
From Fig 5.27(a) : F = YZ + YZ + XY ...(5.6)
– – ––
From Fig 5.27(b) : F = YZ + YZ + XZ ...(5.7)
– –
Observe that the product terms YZ and YZ are two EPIs of the function common to the two alternative solutions of the function and the terms X
– – and X– – Y Z depend on the choice of the looping of the minterm m0. These type of PIs are called the optional Prime Implicants (OPI). In this example, we have two OPIs – X
–– and X–– Y Z. Once one alternative minimum cover has been selected, none of the remaining OPIs can be used for minimum cover in that expression. Referring to Eqn(5.6) and Eqn(5.7) we see that the OPI diad used in one expression then other becomes redundant diad. OPIs are also called nonessential PIs or non-EPI.

5.4.6 Definition-6 : Redundant Prime Implicant (or Implicate) (RPI) Superfluous PIs, which cannot be used for minimum cover is called a Redundant Prime Implicant (RPI).–
–If we follow the looping scheme as in Fig 5.21(c) we get the reduced expression F = YZ + YZ
+ X
–– + X– – Z Y. In this expression first two product terms are EPIs because they have covered the distinguished minterms m5 and m6 respectively and out of the last two terms if we use any one, the other will be redundant. Thus, X
– – may be a RPI if we use X–– Y Z in the expression. Similarly, X
–– will be RPI if we use X––
Z Y in the expression.
5.4.7 Definition-7 : Minimal Cover A minimal cover of a Boolean function F contains of all essential prime implicants (or implicates) and some non essential prime implicants (or implicates) that cover all the minterm (or maxterm) boxes of a K-map.

We may now conclude that a minimal solution of a function is not always uinque because in the solutionn there may be non-EPIs besides EPIs and the non-EPIs are not unique.
5.5 SIMPLIFICATION OF 4-VARIABLE FUNCTION USING FOURTH-ORDER K-MAP

A function with four variables may have maximum 16 minterms (or maxterms). To map this type of function, the K-map should have 16 boxes. The 16 boxes for this map are arranged in a 4☐4 matrix. The rows and the columns are coded with unit distant code. There may be four different possible groups of minterm (or maxterm) boxes in a 4-variable map. Those possible groups may be isolated boxes (or Monad), group of two boxes (or Diad), groups of four boxes (Quad), group of eight boxes (or Octed) or a group of sixteen boxes. Some typical groups of 1s in a 4-variable K-map are shown in Fig 5.22. Similar types of groups are possible with the boxes of 0s. The Fig 5.22(a) shows a monad or an isolated Fig 5.22

box of 1, Fig 5.22(b) shows a diad. The groupings in Fig 5.22(b) is possible because any box of the top row is logically adjacent to a box of the bottom row having the same column. In Fig 5.22(b) the two 1s are in the second column. In Fig 5.22(c) the four corner boxes are

logically adjacent to form a valid quad. Logical adjacency of these corner boxes can be proved by the repeated application of the adjacent theorem. The four corner boxes represents the four minterms m0, m2 m8 and m10. When they are combined then we get F = m0 + m2 + m5 + m
– –– – – –10 ––– – –
= WXYZ + WXYZ + WXYZ + WXYZ
– –– – –– –
= WXZ(Y+Y)+WXZ(Y+Y)
––– –– –– – –
= WXZ + WXZ = XZ (W+W) = XZ.

The reduced form of the functions are shown below each map of Fig 5.22. All these minimised expressions out of the cluster in each map can be obtained by using the Adjacent Theorems repeatedly. From Fig 5.22 it is seen that each cluster of the boxes can be represented by the (n–m) literals where n is the number of variables of the mapped function (here n = 4) and 2m is the cluster size where m = 0 for a monad, m = 1 for a diad, m = 2 for a quad and m = 3 of an octed etc. If m = 4 (this case has not been considered in the figure) then the cluster will contain 24 = 16 boxes of 1s. Therefore, the function is identically equal to 1. The minimised product or the sum term out of a cluster can be obtained by inspecting the cluster. Each cluster represents a product or a sum term formed with the literals which remain unchanged within the cluster. For example, within the cluster of 1s of Fig 5.22(e) the literals X and Y– remain unchanged within the cluster of 4 minterm boxes but the logic state of W and Z changes when we move from one box to another. So, the minimized product term is XY–.

In the earlier section we have defined the Essential prime implicants (EPI) and the Nonessential prime implicants. Here we shall utilise earlier definitions to get the minimal solution in case of 4-variable K-maps.

Find out the prime implicants, essential prime implicants and minimal SOP expression for the following function. F (W,X,Y,Z) = ☐m(1,3,4,5,10,11,12,13,14,15). The function F(W,X,Y,Z) is mapped in a 4-variable K-map as shown in Fig 5.23(a). Fig 5.23(b) shows the different possible clustering of the minterms. Each cluster or a group represents a prime implicant because no group is completely included in the other. The groups are indicated by p1, p2, p3, p4, p5 and p6 and the corresponding prime implicants are WY, WX, W
– –Z, W– –Z, X–YZ and XY–
Y X .

To get the essential prime implicants we search for the distinguished minterm boxes in the map. From Fig 5.23(b) we can see that there are two distinguished mintern boxes, m4 and m10 because these boxes have been combined only in one way i.e. these boxes are covered by a cluster of four boxes only in one way. These boxes are marked with star (*). Thus, the groups p1 and p6 are the essential because they cover the distinguished minterm boxes. Once we consider the essential groups p1 and p6 of the map then the minterms m4, m5, m10, m11, m12, m13, m14 and m15 are covered and only the minterms m1 and m3 remain uncovered. The remaining minterms m1 and m3 can be combined in two ways with the adjacent boxes. The minterm m1 may be combined either with m3 or with m5 and m3 may be

combined either with m1 or m11 as shown in Fig 5.23(b). But the combination m1 with m3 is the best choice because this group (shown with dotted line in Fig 5.23(c) contributes only one term W

– –
XZ to the solution otherwise two product terms would come to the solution, one from the group of (m1 and m3) and another from the group of (m3 and m11).
Fig 5.23

–
Thus, the essential prime implicants are XY and WY and the optional prime implicant is WXZ. The minimal solution for this problem is F = XY
– + WY + W– –
XZ.
5.6 INCOMPLETELY SPECIFIED FUNCTIONS
(DON’T CARES)
5.6.1 Introduction In the earlier sections we have seen that the functional outputs were either 1 or 0 for all possible combinations of the switching variables. These type of functions are called the completely specified functions. Sometimes, however, when certain combinations of input logic variables never occur, the output function for such combinations are nonessential. Also, there are cases, when all combinations of input logic variables occur but certain combinations of these variables are nonessential for the outputs. In the design of logic circuits, nonessential minterms or maxterms may be introduced so as to simplify the circuit. Such nonessential minterms or maxterms are called Don’t Cares. As the functional output does not depend on these terms, so the output for the don’t care terms can be taken either as logic-0 or logic-1 and hence the name don’t care has been coined for these outputs of the non essential minterms (or maxterms). The commonly used symbols for don’t care outputs are ‘X’, ‘–’, ‘d’ and☐. We will use the symbol☐ to represent the outputs of the nonessential minterm or maxterm for the output of the function. The symbol☐ may be thought of as 0 with 1 superimposed on it.

As an example, say, a function F(W,X,Y,Z) gives an output 1 for minterms 1,3,7,8,9,10,11,12,13,14 and 15 but depends in a don’t care fashion on the minterms 0,2,4,5,6 and 11 i.e. the output of the function F may be either 1 or 0 for these minterms. This can be represented in the following way.

F(W,X,Y,Z) = ☐m(1,3,7,8,9,10,11,13,14,15) + ☐☐ (0,2,4,5,6,11) where ☐☐ (0,2,4,5,6,11) represents the don’t care minterms.

While designing the logic circuit for a function with don’t care terms, we should be careful that the don’t care inputs should never occur and if this is confirmed, we may assign either 0 or 1 to the don’t care outputs and the choice depends only on the maximum simplification that can be achieved.

As an example, we consider the case of BCD coding. We know that the decimal numbers 0 to 9 can be coded using 8-4-2-1 code. This needs four binary bits for each code and using four binary bits we can write 16 codes but only 10 codes (0000 to 1001) are used for the coding of decimal digits 0 to 9. That is, the BCD coding does not use 6 input codes (1010 to 1111) and we may say that these 6 input 8-4-2-1 codes are non essential.

If we design a logic circuit which gives an output, equal to logic-1 whenever the BCD codes are the inputs to the circuits, then for the 6 non essential codes the output will be don’t care type as shown in table (TABLE 5.4).

Decimal number 8-4-2-1 code Logic
Circuit Output

0 0000 1
1 0001 1
2 0010 1
3 0011 1
4 0100 1
5 0101 1
6 0110 1
7 0111 1
8 1000 1
9 1001 1
10 1010 ☐
11 1011 ☐
12 1100 ☐
13 1101 ☐
14 1110 ☐
15 1111 ☐

Table 5.4 This can also be written using notation of canonical SOP form as Logic circuit output = ☐m(0,1,2,3,4,5,6,7,8,9) + ☐☐(10,11,12,13,14,15).

Represent the function given in the following table in canonical SOP and POS form by using don’t care coding.
Reading the truth table we may write using canonical SOP form F = ☐m(0,4,6) + ☐☐(1,3,7)
Reading the truth table we may write using canonical POS form
F = ☐M(2,5). ☐☐(1,3,7) X Y Z F
0 0 0 1
0 0 1 ☐
0 1 0 0
0 1 1 ☐
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 ☐ Table 5.5. Truth tabke for the Example 29

5.6.2 Mapping of Incompletely Specified Functions in a K-map
Consider an incompletely specified function
F(X,Y,Z) = ☐m(0,1,5,7) + ☐☐(2,4) Here 0,1,5 and 7 are the essential minterms and 2 and 4 are the non essential minterms or the don’t care terms. This function is plotted in the 3-variable Karnaugh map with entry F in the boxes for minterm 2 and 4. This is shown in the fig 5.24(a).

For illustration, consider another function F(W,X,Y,Z) = ☐m(4,5,13,15) + ☐☐(2,3,7,9,14). This is plotted in the Fig 5.24(b).
Let us take another function which is expressed using maxterms. Let the function be F(W,X,Y,Z) = ☐M(0,1,4,6,8,14) ☐☐(2,3,9).

Fig 5.24

Here, the essential maxterms are 0,1,4,6,8,14,15 and nonessential maxterms are 2,3 and
9. This function is plotted in a 4-variable Karnaugh map as shown in Fig 5.24(c). Substituting
0 in the boxes 0,1,4,6,8,14 and 15; ☐ in the box number 2,3 and 9 and 1s in the remaining boxes.

5.6.3 Minimisation of Incompletely Specified Function using K-map.
The loop-out protocols for the SOP and POS cover while the Karnaugh map contains the don’t care (☐) entry along with the usual 1s and 0s are stated as follows: (1) For SOP cover allow ☐’s to be included when looping the boxes of 1’s assuming ☐ = 1, to make the cluster of 1’s as large as possible. This reduces the number of variables in the corresponding prime implicants.

(2) For POS cover allow ☐’s to be included while looping the boxes of 0’s assuming ☐ = 0, to make the cluster of 0’s as large as possible.This reduces the number variables in the corresponding prime implicates.

(3) The looping of only☐’s either for SOP or POS cover leads to the unnecessary terms. So, one should avoid grouping of only☐’s in the K-map.
Find the minimum SOP and POS expression for the following function. F(X,Y,Z) = ☐m(0,1,5,7) + ☐☐(2,4)
The incompletely specified function is plotted in the Karnaugh map Fig 5.25

(a). In this figure, if we take ☐ = 1 in the box-4 then we can make a cluster of 4-boxes to give a reduced term Y–. The box-5 and box-7 gives a term XZ. So, the minimum SOP form is F(X,Y,Z) = Y–+XZ. But we need not assume☐ = 1 in the box-2 because this will give rise to an extra term X

– –
Z due to the looping of box-2 with the box-0. Therefore, it is better to assume ☐ = 0 in the box -2.

For a POS cover of the same function we have to loop the 0s of the map with the ☐. Wherever we need, we may put☐ = 0 for bigger clustering to occur. This is shown in the Fig 5.25(b). In the map, we assume☐= 0 in box 2 to loop with logically adjacent 0s. This looping scheme gives the reduced POS form of the function as F(X,Y,Z) = (X+Y–)(X–+Z).

Fig 5.25
Note : Had we chosen not to use the☐ = 0 in these two boxes in Fig 5.25(b) the reduced function F(X,Y,Z) would have been
– – – –
F(X,Y,Z) = (X + Y + Z) (X+ Y+ Z), for☐ ☐ 0 in both boxes.
= (X + Y) (X+Y+Z), for☐ = 0 in box-2 and☐ ☐ 0 in box-4;
= (X + Y + Z) (X + Z), for☐ = 0 in box-4 and☐ ☐ 0 in box -2;
– –
= (X+Y) (X+Z), for F = 0 in both boxes.
Find out the minimum SOP and POS expression for the following function. F(W,X,Y,Z) = ☐M(0,1,4,6,8,14,15). ☐☐(2,3,9).

The given function is plotted in a 4-variable Karnaugh map 5.26(a). Treating ☐ = 1 in box-2 and 3 (for a bigger clustering with 1s of box –10 and 11) and using the rules of minimal SOP cover we get F(W,X,Y,Z) = X–Y + W–XZ + WXY–.

–
Note : Had we not taken F = 1 in box - 2 and box -3 we would get F(W,X,Y,Z) = WXY +–
WXZ + WXY– and this would not be a minimum SOP form of the function.

For a POS cover, the don’t care entry F in any block of the map may be treated to be 0 to form a bigger group with other 0s of the logically adjacent boxes. The looping scheme is shown in Fig 5.26(b).

In this map, ☐’s of box-2 and box - 9 have been taken to be 0 to have a bigger cluster with adjacent 0s as shown in Fig 5.26(b). The reduced POS form is
– – –
F (W,X,Y,Z) = (X + Y) (W + Z) (W+X+Y)
Fig 5.26
Note : Had we not taken☐ = 0 both for box-2 and box-9 we would have got
– –
F = (W,X,Y,Z) = (W + X + Y) (W +X+ Z) (X+Y+Z) (W +X+Y)
– – – –
and F(W,X,Y,Z) = (X+Y) (W+X+Y) (W+X+Z) if☐ = 0 in box-9 only.– – –
and F(W,X,Y,Z) = (W+Z) (X+Y+Z). (W+X+Y). (W +X+Y) is F = 0 for box-2 only etc.
5.7 QUINE MCCLUSKEY METHOD OF MINIMISATION 5.7.1 Introduction In chapter-4 we have seen the application of different theorems to simplify the switching functions. The method of simplification was tedious and prone to errors if the theorems are not properly applied especially for a function containing large number of variables. Later on Karnaugh map method which is discussed in this chapter can be applied very easily and comfortably for the minimisation of a function containing upto 4 variables. But the complexity increases gradually when we go for a function containing a number of variables beyond 4.

In 1952 W.V. Quine first introduced a tabular method of minimisation for the functions having larger number of variables. This method introduced by Quine was much improved by E.T. McClusky in 1956. Therefore, the method which we use for the minimisation is known as Quine McClusky method (QM method). This method utilises the Adjacency theorem repeatedly to the minterms (or maxterms) present in a function with large number of variables. This method is very much systematic. Therefore, the function which is to be minimised should be expressed in the form of a canonical SOP (or POS) form if the function is not in minterm(or maxterm) form.

QM method works in two phases :
Phase (i) The set of all the Prime-Implicanta (or Prime Implicates) are obtained following a systematic rule.

Phase (ii) The set of all irredundant prime implicants are selected in the 2nd phase. The irredantant prime implicants includes the Essential Prime Implicants (EPI) and a few NonEssential Prime Implicants (Non-EPIS).

The selection of all the EPIs and a few Non-EPIs gives the minimal solution of the function.

If don’t care terms (minterms or maxterms) are present in the given function then don’t care terms must always be included in the first phase; howevers don’t care terms must never be used in the second phase since their inclusion at this point prevent us from obtaining the smallest number of prime implicants to cover only specified outputs of the function.

It is mentioned earlier that in QM method the Adjacency theorem is applied repeatedly to the minterms (or the maxterms) present in the given function to determine all the Prime Implicants (or the Prime Implicates). Here, the logically adjacency of two terms means that the two terms differ in exactly in one variable only. For example, A BC D in

logically adjacent to A B C D because these two terms differ in variable A only. If these two terms are combined i.e. ORed together then we get the following

m9 = A B C D = 1001 (binary code of m9)
m1 = A BC D = 0001 (binary code m1) m9 + m1 = B C D = –001 (binary code after combining m9 & m1) The dash (–) in binary notation after ORing indicates that the variableA is absent in the resultant reduced terms. In the above example, the reduced term is B C D and the binary code of it is-001. Here, the combination of two minterms means OR-ing and for two maxterms the combination means AND-ing.

In no case we shall combine two terms if they differ by two or more variables. For example, two minterms A B C D and A B C D can’t be combined because these two minterms differ in A and D i.e., in more than one positions. Thus, two terms are not logically adjacent. Therefore, the given function is to be expressed in canonical form preferably in decimal number notation to test logical adjacency. This is the 1st step.

5.7.2 Grouping of Minterms

Instead of searching for the logically adjacent minterms from a large number of minterms of a function unweildy a systematic approach is followed as follows : The binary coded minterms are sorted in several groups in an ascending order according to the number of 1’s present in each minterm of the function. This is the 2nd step of the QM method.

In this 2nd step, we search for the minterm m0(☐0000) i.e., the minterm without any 1 in the binary coded form. If it is present then this is placed in Gr-0 but if m0 is absent in the function then Gr-0 will remain vacant. In Gr-1 all the minterms are with single 1 and are written in the sorted form. They are sorted in the ascending order within the group depending on the decimal equivalent number of the minterms. In this group we will find the minterms m1, m2, m4, m8, m16 etc. if they are present.

In Gr-2, all the minterms of the function containing two 1’s in the binary coded form are to be included in the sorted form in the ascending order e.g. the minterms m3, m5, m12, m17 etc. are placed within this group. Following the same procedure all other minterms of the function are placed in the sorted form in other groups.

Let us illustrate the step-2 considering a function F = ☐m(0,1,3,5,7,8,11,12,13,15) containing 10 minterms. The sorted minterms in different groups are shown in a tabular form in TABLE 5.6. with the binary coded form of the minterms along with their decimal equivalent numbers and the number of 1’s present in the minterm.

Group Decimal Number of minterms Gr-0 0
Gr-1 1

8
Gr-2 3
5
12
Gr-3 7
11
13
Gr-4 15

Binary Coded Number Minterms minterm of 1’s using variables
– – – –
0 0 0 0 0 A B C D
– – –
0 0 0 1 1 A B C D
– – –
1 0 0 0 1 AB C D
– –
0 0 1 1 2 A B C D
– –
0 1 0 1 2 A B C D
– –
1 1 0 0 2 AB C D
–
0 1 1 1 3 A B C D
–
1 0 1 1 3 A B C D
–
1 1 0 1 3 AB C D 1 1 1 1 4 AB C D
Table 5.6 : Minterms arranged in groups depending on the number of 1’s (step 2 of QM method)
5.7.3 Determination of Prime Implicants After sorting out the minterms it may be noted from the TABLE 5.6 that the minterms within a group are not logically adjacent because within a group one minterm must differ in at least two position i.e. by two variables. But a minterm of a group Gr-i with decimal equivalent number ma is logically adjacent to a minterm mb of the adjacent group Gr-j provided mb – ma = 2p and mb > ma where p = 0 or any positive integer and j = i + 1. This is the key point to find out the prime implicants using the decimal numbers of the minterms for a given function instead of writing binary representation for each term of the function. This process will be discussed later in this chapter.

After developing the TABLE-5.6 containing the sorted minterms depending on the number of 1’s of the minterms next try to find the prime implicants. To get the prime implicant the Adjaceny Theorem is to be applied between the minterms of one group and the minterm of the next higher group. For example, in TABLE-5.6 the minterm m 0
(=A
– – – –
BCD ) of Gr-0 can be combined with the minterm m
1
(=A
– – – B CD) and m8 (=) of Gr-1. to get the reduced terms because both pairs (m0, m1) and (m0, m8) differ in one variable. The reduced terms after combination is two cases are shown below : m0 = A B C D = 0 0 0 0 m0 = A B C D = 0 0 0 0
m1 = A B C D = 0 0 0 1 m8 = A B C D = 1 0 0 0
m0 + m1 = A B C = 0 0 0 – m0 + m8 = B C D = – 0 0 0

One interesting point to be noted here is that the two minterms mb and ma (b > a) of two adjacent groups can be combined if the difference (b – a) of the two minterms can be expressed as a power of-2 i.e., b – a = 2p, p = 0, 1, 2, 3 .... and a dash (–) appears in the binary code of

mb in the position of p starting from the least significant position (p = 0). In the above example for the pair (m0, m1) the value of p = 0 because 1– 0 = 2° and for the pair (m0, m8) the value of p = 3 because b – a = 8 – 0 = 23. Therefore, the dash the pair (m0, m1) appears in the least significant position p = 0 of m1 and for the pair (m0, m8) the dash appears in the position of p = 3 of m8 after combination.

Similarly, for the same reasons

(i) the minterm m1 of Gr-1 can be combined with m3 and m5 but not with m12 of Gr-2 because for the pairs (m1, m3) and (m1, m5) the difference of decimal numbers of the two pairs can be as expressed as 21 and 22 respectively but the difference 12 – 1 for the minterm pair m12 and m1 cannot be expressed as a power of 2 and therefore m12 can’t be combined with m1. The reduced terms after the combinations m1 with m3 and m1 with m5 can obtained as follow – ––
m1 = ABCD = 0 0 0 1 ;
– –
m3 = ABCD = 0 0 1 1 ;
––
m1 ; p = 1.1 + m3 = ABD = 0 0 – 1 ; 3 – 1 = 2
– – –
m1 = ABCD = 0 0 0 1 ;
– –
m5 = AB CD = 0 1 0 1 ;
– –
m2 ; p = 2.1 + m5 = ACD = 0 – 0 1 ; 5 – 1 = 2

(ii) The minterm m8 of Gr-1 can be combined only with m12 of Gr-2 but not with m3 and m5 where 12 – 8 = 22, p = 2. The reduced term for the pair (m8, m12) can be obtained as follows.

m
– ––
m8 = ABCD = 1 0 0 0 ;
––
m12 = ABCD = 1 1 0 0 ;
– – 2 ; p = 2.8 + m12 = ACD = 1 – 0 0 ; 12 – 8 = 2

In this way we can combine the minterms of Gr-2 with Gr-3 and the minterms of Gr-3 with Gr-4 maintaining the rules stated above to generate Column-2 containing the reduced terms from the Column1. This is shown in TABLE-5.7. The Column-2 shows the reduced term using 1, 0 and dashes. We use tick mark (3) for the minterms in Column1 which are able to combine. The Column1 of the TABLE-5.7 shows that all the terms have been checked off meaning that each term of one group i can be combined at least once with the term of the adjacent highest group j. The decimal numbers of the two minterms of Column1 which are successfully compared and combined have also been listed within parentheses seperated by a comma in the Column 2 of TABLE-5.7.

Any term in Column1 which can’t be combined with any of its logically adjacent term of next higher group are marked with a star . Such a term which can’t be combined with logically adjacent term is the Prime Implicant. Any prime implicant obtained from Column1 of TABLE-5.7 actually represents isolated minterm of the given function. In Column1 of TABLE-5.7 no such term is present because all minterms of one group can be combined with minterms of the next higher group. They are indicated using the tick mark (3) in Column1.

Column - 1

Decimal
number of
minterm A B C D

Gr-0 0 0 0 0 0 3
Gr-1 1 0 0 0 1 3
8 1 0 0 0 3
Gr-2 3 0 0 1 1 3
5 0 1 0 1 3
12 1 1 0 0 3
7 0 1 1 1 3
Gr-3 11 1 0 1 1 3
13 1 1 0 1 3
Gr-4 15 1 1 1 1 3

Column - 2

Decimal
number of
minterm A B C D

(0, 1) 0 0 0 – A B C

Gr(0,1) (0, 8) – 0 0 0 B C D (1, 3) 0 0 – 1 3 A B D
Gr(1,2) (1,5) 0 0 – 1 3 A C D (8, 12) 1 – 0 0 A C D (3, 7) 0 – 1 1 3 A C D (3,11) – 0 1 1 3 B C D
Gr(2,3) (5,7) 0 1 – 1 3 A B D (5,13) – 1 – 1 3 B C D (12,13) 1 1 0 – A B C (7,15) – 1 1 1 3 B C D
Gr(3,4) (11,15) 1 – 1 1 3 A C D (13,15) 1 1 – 1 3 A B D Table 5.7 : Table to find out the prime implicants.

The Column-2 of TABLE-5.7 contains all the reduced terms with dash notation and also interms of variables. Again this column is divided into groups depending on the numbers of 1’s. The reduced terms of the first group contain no 1’s, the second group contain single 1, third group contains two 1’s and so on. The members of the first group Gr (0,1) of Column-2 are obtained by combining the terms of Gr-0 and Gr-1 of Column1. Likewise the members of the other groups of Column-2 are obtained. It may be noted that when Gr-i, and Gr-j (where j = i + 1) are combined in Column1 then the combined group in Column-2 will be Gr (i, j) and that group members will contain i numbers of 1’s but always one dash (–).

The Column-2 also indicates the pair of minterms that are combined to obtain the reduced term. The decimal numbers a and b of the minterms ma and mb are enclosed in bracket and are written besides the reduced terms in the Column-2. For example, the 1st row of Gr. (1, 2) of Column-2 with entry (1, 3) 00 –1 (= A – –
BD) gives the information that the reduced term 00–1 (=A
–– B D) is obtained by combing the minterm m1 of Gr-1 with m3 of Gr-2 of Column1 and the dash (–) is placed in the position of p = 1 (because 3 – 1= 21; p = 1) in the binary coded form of m3 (☐0011) keeping all other bits of m3 same.

To get further reduced terms from Column-2, we have to combine the reduced term of one group of Column-2 with the terms of the adjacent group of this column. When an attempt is made to combine two reduced terms of this column belonging to two adjacent groups Gr (i, j) and G (j, k), it is very much important to look for the position of dash (–) in the two terms of these two groups. The dash (–) in the identical position in two reduced terms and differing in bit in exact one position indicates that the two reduced terms are again logically adjacent i.e., they can be combined to get further reduced terms. The reduced terms within a group can’t be combined because of different position of dashes within the group.

If a reduced term of a group G(i, j) of Column-2 with a dash (–) in a position ‘p’ can’t find another reduced term in the next higher adjacent group Gr. (j, k) where j = i+1 and k = j+1 having a dash (–) in the same position p then they can’t be combined due to lack of logical adjacency. Under this condition the reduced term of the group Gr(i, j) will be declared as Prime Implicant for the function. For example, the two reduced terms B

– – –
CD = –000 and
– ––
ABC = 000– of Gr (0, 1) of table-5.7 can’t find any terms within G(1, 2) with dash (–) in the same position. For this reason these two reduced terms A
–– – and B– – – B C CD of Gr (0, 1) are the Prime Implicants of the given function F = ☐m(0, 1, 3, 5, 7, 8, 11, 12, 13, 15) and these two terms are marked with star in the Column-2 in TABLE-5.7.– – Comparing the reduced terms of Gr(1, 2) with Gr (2, 3) it is found that the term AC D (☐1– 00) of Gr (1, 2) cannot be combined with any reduced terms of Gr (2, 3) though there is match in the position of dash (–) between the terms AC
– – and A–
D CD because they differ in three bit position. Therefore, the term AC
– – D is a Prime Implicant from Gr (1, 2) and is marked with . The other term of Gr (1, 2) when compared with those of Gr (2, 3) are found to be logically adjacent. Therefore, these logically adjacent terms of Gr(1,2) are marked with tick mark (3). This shows that these terms are not prime implicants. The terms with tick marks when combined give rise to further reduced terms as shown below.

– –
(i) Gr (1, 2) (1,3) 0 0 – 1 A B D
–
Gr (2, 3) (5,7) 0 1 – 1 A B D
–
Gr (1,2,2,3) (1,3,5,7) 0 – – 1 AD
– –
(ii) Gr (1,2) (1,5) 0 – 0 1 ACD
–
Gr(2,3) (3,7) 0 – 1 1 A C D
– Gr(1,2,2,3) (1,5,3,7) 0 – – 1 AD

Similarly, the terms of Gr (2,3) can be combined logically with the terms of the group Gr(3,4) if the position of dash (–) is matched and they differ only in one bit position. The term ABC– (☐110–) of Gr(2,3) has a dash in the position of p = 0 but the terms of group Gr(3,4) do not have a dash in this position. Therefore, the term ABC– is a Prime Implicant and this is marked with star . Except this term of Gr(2,3) all other terms of Gr(2,3) find one logically adjacent term in Gr(3,4). The terms which are able to combine in two adjacent groups are marked with tick (3). After combining the terms of Gr(3,4) and Gr(2,3) the reduced terms are obtained as shown below.

–

(i) Gr (2,3) (3,7) 0 – 1 1 = A C D
Gr (3,4) (11,15) 1 – 1 1 = A C D
Gr (2, 3, 3, 4) (3, 7, 11, 15) – – 1 1 = C D

–

(ii) Gr (2,3) (3,11) – 0 1 1 = B C D
Gr(3,4) (7,15) – 1 1 1 = B C D
Gr (2,3,3,4) (3,11,7,15) – – 1 1 = C D

–

(iii) Gr(2,3) (5,7) 0 1 – 1 = A B D
Gr (3,4) (13,15) 1 1 – 1 = A B D
Gr (2,3,3,4) (5,7,13,15) – 1 – 1 = BD

–

(iv) Gr (2,3) (5,13) – 1 0 1 = B C D
Gr (3,4) (7,15) – 1 1 1 = B C D
Gr (2,3,3,4) (5,13,7,15) – 1 – 1 = BD

After combining the terms of G(0,1) with Gr(1,2); Gr(1,2) with Gr(2,3) and Gr(2,3) with Gr(3,4) we get the further reduced terms and they are placed in Column 3 of TABLE 5.8.dividing into several groups depending on the number of 1’s. One point is to be noted is that the Column-3 contains all the terms with two dashes. In this particular illustration we have only two groups.

(i) Gr(1,2,2,3) Combining Gr (1,2) with Gr (2,3) with single 1 (ii) Gr (2,3,3,4) Combining Gr (2,3) with Gr(3,4) with two 1’s All prime implicants of different groups are marked with . The Column-3 in TABLE 5.8 shows four sections.

Column-3
Combined groups Minterms Combined A B C D
– Gr (1,2,2,3) (1,3,5,7) 0 – – 1 = A D
– ☐(1,5,3,7) 0 – – 1 = A D
Gr (2,3,3,4) (3,7,11,15) – – 1 1 = C D (3,11,7,15) – – 1 1 = C D ☐ (5,13,7,15) – 1 – 1 = B D ☐ (5,7,13,15) – 1 – 1 = B D Table : 5.8

Each section represents some information obtained in the step 2. Each section is described as follows :
(i) The 1st section shows the groups that have been combined e.g. Gr(1,2;2,3) means that Gr(1,2) and Gr(2,3) are combined.
(ii) The 2nd section shows the minterm pairs that are combined e.g. (1,3,5,7) means that the minterm pairs (1,3) and (5,7) of Gr (1,2) and Gr(2,3) are combined. (iii) The 3rdsection shows the reduced terms after the combination of pairs using minterm pair (3,7) with the minterm pair (11,15).

(iv) The 4th section shows the reduced terms using variables e.g. BD represents –1 –1. One interesting point may be noted from the combinations in column-3 is that “Any term of the group Gr(i,j), j = i + 1 with decimal designation (a,b) can only be combined with another term of the immediate adjacent group Gr (j,k), k = j + 1 in column-2 with decimal designation (c,d) if and only if following two conditions are satisfied”.

Condition -1 : (a-b) = (c-d) = 2p1

Condition-2 : (a-c) = (b-d) = 2p2 where p1 and p2 may be 0,1,2,3.....

The condition-1 is the condition of matching of position dash in the minterm pairs (a,b) and (c,d) in the position p1, and the condition-2 indicates that there is a single mismatch regarding 1 and 0 in the minterm pairs (a,b) and (c,d) in Column-2 in the position of p2. The new dash will appear in the position of p2 when the minterm pairs (a,b) and (c,d) are combined to get a further reduced term (a,b,c,d) in Column-3.

For example, the minterm pair (3,7) = 0 – 11 and (11,15) = 1 – 11 can be combined. For this pairs a = 3, b = 7, c = 11 and d = 15. The two conditions.
(a-b) = 4 (c -d) = 22 ; p1 = 2
(a-c) = 8 (b-d) = 23 ; p2 = 3

are satisfied. Thus, a new dash will appear in the position of p = 3 of the reduced represented by the dash notation either for the pair (a,b) or (c,d). To get the reduced easily after the combination of the minterm pairs (a,b) and (c,d) we write the binary representation of the decimal number d where d is the largest of a,b,c and d and replace the bits in the positions p1 and p2 by dashes keeping all other bits of d unchanged.

In TABLE 5.8 there are some duplicate terms in the two groups Gr(1,2; 2,3) and Gr(2,3;3,4) obtained after the combinaton of the same set of four minterms in different order. For example, (1,3,5,7) ands (1,5,3,7) represent the same term 0 – – 1= A–D. Similarly, (3,7,11,15) and (3,11,7,15) are identical and (1,5,3,7) and (5,7,13,15) are also identical. Therefore, the rows containing the duplicate terms from the groups of Column-3 should be removed. The rows to be removed are marked with cross (X) in Column-3 of the TABLE-5.8.

After removing the duplicate terms in Column-3 it is found that the reduced terms represented by (1,3,5,7) of Gr(1,2; 2,3) can’t be combined either with the terms (3,7,11,15) or with (5,7,13,15) because the position of dashes differ. The process of combination is stopped otherwise we have to combine further to form a new groups of terms and a new column would be required until no further terms can be combined TABLE 5.8, the terms which can’t be combined are marked with stars . These terms of column-3 represent Prime Implicant of the given function F = ☐m(0,1,3,5,7,8,11,12,13,15). Considering all the prime implicants marked with of Column-2 of TABLE 5.7 and Column-3 of TABLE 5.8 we get the following list of prime implicants.

– ––
(0,1) = 0 0 0 – = ABC ; this P1 covers m0 and m1.
– ––
(0,8) = – 0 0 0 = BCD ; this P1 covers m0 and m8.
––
(8,12) = 1 – 0 0 = ACD ; this P1 covers m8 and m12.
–
(12,13) = 1 1 0 – = ABC ; this P1 covers m12 and m13.
– (1,3,5,7) = 0 – – 1 = AD ; this P1 covers m1,m3,m5 and m7. (3,7,11,15) = – – 1 1 = CD ; this P1 covers m3,m11,m7 and m15. (5,7,13,15) = – 1 – 1 = BD ; this P1 covers m5, m13,m7 and m15.

Obtain the Prime Implicants for the function F = Sm(0,5,6,7,9,10,13,14,15) using QM method and verify using Karnaugh Map.
Column1

Group Decimal
minterm A B Gr-0 0 0 0 Gr-1
Gr-2 5 0 1

6 0 1
9 1 0
10 1 0
Gr-3 7 0 1
13 1 1
14 1 1
Gr-4 15 1 1

Column-2

Group Decimal No
C D minterms A B C D

0 0
Gr-(2,3) (5,7) 0 1 – 1 3

0 1 3 (5,13) – 1 0 1 3
1 0 3 (6,7) 0 1 1 – 3
0 1 3 (6,14) – 1 1 0 3
1 0 3 (9,13) 1 – 0 1

1 1 3 (10,14) 1 – 1 0

0 1 3 Gr-(3,4) (7,15) – 1 1 1 3
1 0 3 (13,15) 1 1 – 1 3
1 1 3 (14,15) 1 1 1 – 3

Table 5.9(a) Table 5.9(b)

Column -3
Group Decimal No A B C D Gr(2,3;3,4) (5,7,13,15) – 1 – 1

(5,13,7,15) – 1 – 1 ☐ (6,7,14,15) – 1 1 –

(6,14,7,15) – 1 1 – ☐

- Note : means P1 term☐ means duplicate PI term.
Table 5.9(c)
Therefore, the prime implicants are (after removing the duplicate PI terms) (a) Using dash notation : 0 0 0 0 1–01, 1–10, –1–1 –11–– – – – – – (b) Using variable (A,B,C,D) : A B C D ACD ACD BD BC
(i) Verification using K-map

– –– – –
Fig 5.46: The Prime implicants from the k-map are BC, ACD, ABCD.
Obtain the Prime implicants of the function F(A,B,C,D) = AB + BC– + CD + B–D–. Writing the function in canonical form we get
– – – – – – – – – – – – –
F(A,B,C,D) = A B C D + A B C D + A B C D + A B C D + A B C D + A B C D +
– – – –
+ A B C D + A B C D + A B C D + A B C D + A B C D
= ☐m(1,3,4,5,7,9,11,12,14,15)
Column -1 Column-2
Group Decimal Group Decimal No. of No. of
minterm A B C D minterms A B C D Gr-0 0 Gr(1,2) (1,3) 0 0 – 1 3 Gr-1 1 0 0 0 1 3 (1,5) 0 – 0 1 3

4 0 1 0 0 3 (1,9) – 0 0 1 3
Gr-2 3 0 0 1 1 3 (4,5) 0 1 0 – 3
5 0 1 0 1 3 (4,12) – 1 0 0 3
9 1 0 0 1 3 Gr(2,3) (3,7) 0 – 1 1 3
12 1 1 0 0 3 (3,11) – 0 1 1 3
Gr-3 7 0 1 1 1 3 (5,7) 0 1 – 1 3
11 1 0 1 1 3 (9,11) 1 0 – 1 3
13 1 1 0 1 3 (9,13) 1 – 0 1 3
14 1 1 1 0 3 (12,13) 1 1 0 – 3
Gr-4 15 1 1 1 1 3 (12,14) 1 1 – 0 3
Table 5.10 (a) Gr(3,4) (7,15) – 1 1 1 3
(11,15) 1 – 1 1 3
(13,15) 1 1 – 1 3
(14,15) 1 1 1 – 3
Table 5.10 (b) Column-3
Group Decimal
No. of
minterms A B C D

Gr(1,2; 2,3) (1,3,5,7) 0 – – 1
(1,3,9,11) – 0 – 1
(1,5,3,7) 0 – – 1 ☐ (1,5,9,13) – – 0 1
(1,9,3,11) – 0 – 1 ☐ . (1,9,5,13) – – 0 1 ☐ (4,5,12,13) – 1 0 – (4,12,5,13) – 1 0 – ☐

Gr(2,3; 3,4) (3,7,11,15) – – 1 1
(3,11,7,15) – – 1 1 ☐ (5,7,13,15) – 1 – 1
(5,13,7,15) – 1 – 1 ☐ (9,11,13,15) 1 – – 1
(9,13,11,15) 1 – – 1 ☐ (12,13,14,15) 1 1 – – (12,14,13,15) 1 1 – – ☐

- Note : X represents duplicate term
Table 5.10 (c)
Modified Column-3 (after removing duplicate terms) from TABLE 5.10(c). Group Decimal
No. of
minterms A B C D

Gr(1,2; 2,3) (1,3,5,7) 0 – – 1 3
(1,3,9,11) – 0 – 1 3
(1,5,9,13) – – 0 1 3

–
(4,5,12,13) – 1 0 – BC

Gr(2,3; 3,4) (3,7,11,15) – – 1 1 3
(5,7,11,15) – 1 – 1 3
(9,11,13,15) 1 – – 1 3

(12,13,14,15) 1 1 – – AB
- Note :
represents PI
Table 5.10(d)

Column - 4
Group Decimal No A B C D

Gr(1,2; 2,3; 2,3,3,4) (1,3,5,7,9,11,13,15) – – – 1
D (1,3,9,11,5,7,13,15) – – – 1 ☐ (1,5,9,13,3,7,11,15) – – – 1 ☐
- Note : X represents duplicate terms
Table 5.10 (e)
The following are the prime implicants
–
(i) –10– ( = BC) from group Gr(1,2,2,3); 11 – – (= AB) from group Gr(2,3,3,4) and
–
– – – 1( = D) from Gr(1,2,2,3,2,3,3,4) (ii) using variables the PIs are BC, AB D.
Find the Prime Implicants and Implicates of the following function using the QM method.
F(A,B,C,D) = ☐M(2,4,6,7,8,11,12,13,15)
The function is given in standard POS form. If we treat these maxterm numbers of the function as minterms as follow the QM method then we will get the prime implicants of F–. These minterms when inverted will give us the prime implicates of F. To get the prime implicants we express the function F in the standard SOP form. The standard SOP form of the function is F (A,B,C,D) = ☐m(0,1,3,5,9,10,14). The QM method can be applied to this SOP form to get the prime implicants.

Column -1 Column-2 Group Decimal Group Decimal
No. of No. of
minterms A B C D minterms A B C D Gr-0 0 0 0 0 0 3 Gr-(0,1) (0,1) 0 0 0 –
A–B–C
Gr-1
1
0
0
0
1
3
––
Gr-(1,2) (1,3) 0 0 – 1 ABD Gr-2
3
0
0
1
1
3
––
(1,5) 0 – 0 1 ACD 5 0 1 0 1 3 (1,9) – 0 0 1

– – BCD
10 1 0 1 0 3 Gr-(2,3) (10,14) 1 – 1 0 ACD– 3 Table 5.11(b)Gr-3 14 1 1 1 0
Table 5.11(a) No prime
implicants from Column1
The possible prime implicants of this function are (i) using dash notation 000–, 00–1, 0– 01, –001, 1–10 (ii) using variables A
–– –, A––D, A––D, B– –D, ACD–
BC B C C , for the function F = ☐m(0,1,3,5,9,10,14).
Prime Implicants of F–.

Column1 Column-2 Group Decimal Group Decimal
No. of No. of
minterms A B C D Minterms A B C D

Gr-0 Gr-0– Gr-1 2 0 0 1 0 3 Gr-(1,2) (2,6) 0 – 1 0 ACD 4
0
1
0
0
3
–
(4,6) 0 1 – 0 ABD 8
1
0
0
0
3
–
(4,12) – 1 0 0 p BCD Gr-2 6 0 1 1 0 3 (8,12) 1 – 0 0 p– –D 12 1 1 0 0 3
AC
–
Gr-(2,3) (6,7) 0 1 1 – p ABC Gr-3
7
0
1
1
1
3
– (12,13) 1 1 0 – p ABC 11 1 0 1 1 3 Gr-(3,4) (7,15) – 1 1 1 BCD Gr-4 15 1 1 1 1 3 (11,5) 1 – 1 1 ACD Table 5.11(c) (13,15) 1 1 – 1 ABD Table 5.11(d) –
Therefore, the prime implicant of F is
(i) using dash notation 0–10, 01–0, –100, 1–00, 011–, 110–, –111, 1–11, 11–1
– – – – –– – – – –
(ii) using variables ACD, ABD, BCD, ACD, ABC, ABC, BCD, ACD, ABD. Therefore, the prime implicants of this function F are
– – – – – – – –
(A+ C + D), (A + B + D), (B + C+ D), (A + C + D), (A + B + C ), (A + B + C).
– – – – – – – – –
(B + C + D), (A + C+ D), (A + B+ D).
5.7.4 Essential Prime Implicants According to the definition of Essential prime implicant we know that those prime implicants are essential prime implicants which covers one minterm in only way. Based on this definition we can find the EPIs very easily from the PI table. In the PI table [TABLE 5.14(a)] we find that the minterm m11 is covered only by the prime implicant CD. Therefore, the term is an Essential Prime Implicant of the given function in this way whenever we find a column containing a single cross (☐), then the corresponding row is an EPI. Whenever, an EPI is detected then the row of PI table containing that prime implicant and the column of minterms covered by that prime implicant and the column of minterms covered by that prime implicant are to be removed from this PI table [TABLE 5.12(a)], the row for the prime implicant CD and the column for the minterms 3,7,11 and 15 are removed. This is shown by drawing horizontal and vertical lines in [TABLE 5.12(a)]. The row for this EPI term CD is marked withi and the minterm no.11 which is covered once is also markedi in [TABLE 5.12(a)].

Prime Implicants 0 1 3 5 7 8 11 12 13 15 (5,7,13,15) BD ☐ ☐ ☐ ☐ (3,7,11,15) CD ☐ ☐ ☐ ☐

–

(1,3,5,7) A D ☐ ☐ ☐ ☐
– ☐ ☐(12,13) ABC
(8,12) AC–– ☐ ☐

– ––D
(0,8) BCD ☐ ☐
(0,1) A
–– –
BC ☐ ☐
Table 5.12(a) : PI table showing the coverge of the minterms by the prime implicants. PI table after deleting the row for the prime implicant CD and column for the minterms 3,7,11 and 15 we get a reduced PI table [TABLE 5.12(c)].

Prime Implicants 0 1 3 5 7 8 11 12 13 15 (5, 13, 7, 15) BD ☐ ☐ ☐ ☐

(3, 11, 7, 15) CD ☐ ☐
☐
– ☐ ☐ ☐ ☐(1, 3, 5, 7) A D
(0, 1) A
–– –
BC ☐ ☐
– – ☐ ☐(8, 12) AC D
(0, 8) B
– – –
C D ☐ ☐–
(12, 13) A B C ☐ ☐ Table 5.12(b) : PI table showing the coverge of the minterms by the prime implicants. Prime Implicants 0 1 5 8 12 13 (5,13,7,15) BD ☐ ☐
–
☐ ☐(1,3,5,7) AD
––– ☐ ☐(0,1) ABC
– –
(8,12) ACD ☐ ☐
– ––
(0,8) BCD ☐ ☐
– ☐ ☐(12,13)ABC
Table 5.12(c) EPIs are marked with

From the reduced PI table [TABLE-5.12(c)] it may be noted that no minterm is covered by a single PI i.e. one cannot decide for the remaining EPIs if any. But to get minimal solution we have to select minimum number of PIs from this table covering all the minterms with each PI should have the minimum number of literals. For this reason we choose the two PIs BD and A–D which are marked with star in a circle
showing that these two are selected EPIs of the function. This is shown in TABLE -5.12(c).

–
After removing the two rows of the selected EPIs AD and BD and their associated mintermcolumns covered by there two EPIs we get a further reduced PI table [TABLE-5.12(d)]. Prime
Implicants 0 8 12

– – – ☐(0,1) ABC
(8,12) AC–D ☐ ☐
(0,8) B

– ––
CD ☐ ☐
(12,13) ABC– ☐
Table 5.12(d) : Reduced PI table after removing the selected EPIs BD and BD and AD and their associated minterm columns 1,5 and 13. From this reduced table we can see that the minterms 0,8 and 12 can be covered if we consider the PIs AC
–– and B– –– because AC–– covers 8 and 12 and B– – –
D CD D CD covers consider the PIs AC
–– and B–– – because AC– – covers 8 and 12 and B– – – D CD D CD covers 0 and 8. There is another choice for covering three minterms. The second choice is to consider the two PIs ABC– for covering minterm 12 and B

– ––
CD for covering the minterms 0 and 8.
– –– – – The third choice is to consider the PIs A BC for covering minterms 0 and ACD for covering 8 and 12.
Thus, there are three alternative minimal solution for
F = ☐m(0,1,3,5,7,8,11,12,13,14).

– – – – –
(i) CD + BD + AD + ACD + BCD
– – – – –
(ii) CD + BD + AD + ABC + BCD
– –– – – –
(iii) CD + BD + AD + ABC + ACD
5.8 QUINE MCCLUSKY SIMPLIFICATION OF FUNCTIONS CONTAINING DON’T CARE TERMS

When a switching function has don’t care terms we set all the don’t care minterms equal to 1 and find the prime implicants. In determining the essential prime implicants and minimum cover of the function, we use a value of 0 for all the don’t care minterms that is the decimal numbers that denote the don’t care terms should not appear in the PI table. Following are some illustration for the simplification.

Find out the minimal SOP solution for the following function using Quine McCluskey method and verify the result using K-map.
F(A,B,C,D) = ☐m(2,3,4,6,9,11,12) + ☐☐(0,1,14,15)
In the first phase, the don’t care terms are treated as the normal minterm (i.e. F = 1 for m0, m1,m14,m15) to get the PIs for this function.
Phase 1 : Finding of PIs using don’t care minterm as the normal minterm
Column1
Group Decimal No.
of minterm A B C D

Gr-0 0 0 0 0 0 3
Gr-1 1 0 0 0 1 3

2 0 0 1 0 3
4 0 1 0 0 3

Gr-2 3 0 0 1 1 3
6 0 1 1 0 3
12 1 1 0 0 3

Gr-3 11 1 0 1 1 3 14 1 1 1 0 3 Gr-4 15 1 1 1 1 3
Table 5.13(a)
Column-2
Group Decimal No.
of Minterm A B C D

Gr(0,1) (0,1) 0 0 0 – 3
(0,2) 0 0 – 0 3

(0,4) 0 – 0 0 3
Gr(1,2) (1,3) 0 0 – 1 3

(1,9) – 0 0 1 3
(2,3) 0 0 1 – 3
(2,6) 0 – 1 0 3

(4,6) 0 1 – 0 3 (4,12) – 1 0 0 3

Gr(2,3) (3,11) – 0 1 1 3
(6,14) – 1 1 0 3
(9,11) 1 0 – 1 3
(12,14) 1 1 – 0 3

Gr (3,4) (11,15) 1 – 1 1 PI (14,15) 1 1 1 – PI Table 5.13 (b) Column-3

Group Decimal No.
of minterm pairs A B C D

Gr(0,1;1,2) (0,1,2,3) 0 0 – – PI (0,2,1,3) 0 0 – – ☐ (0,2,4,6) 0 – – 0 PI (0,4,2,6) 0 – – 0 ☐ Gr(1,2;2,3) (1,3,9,11) – 0 – 1 PI (1,9,3,11) – 0 – 1 ☐ (4,6,12,14) – 1 – 0 PI (4,12,6,14) – 1 – 0 ☐
Column-4

Group Decimal No.
of minterm pairs A B C D

Gr(0,1;1,2) (0,1,2,3) 0 0 – –
PI
(0,2,4,6) 0 – – 0
PI
Gr(1,2; 2,3) (1,3,9,11) – 0 – 1
PI
(4,6,12,14) – 1 – 0
PI
Table 5.13(d) : Reduced table after deleting the duplicate terms from Column-3 Phase 2 : Finding the EPIs from the PI table.
Prime Implicants 2 3 4 6 9 11 12
– –
(0,1,2,3) AB ☐ ☐
– –
(0,2,4,6) AD ☐ ☐ ☐
–
(1,3,9,11) BD *
* EPI
(4,6,12,14) BD ☐ ☐
EPI
(11,15) ACD ☐
Table 5.13(e) : Prime Implicant table The prime implicant with minterms 0,1,14 and 15 are not considered in the PItable because these two are don’t care minterms.– –
The PI table [TABLE 5.13(e)] shows two EPIs – BD and BD. After removing these two EPIs and the minterm columns associated with these two EPIs there remains only uncovered minterm with decimal number 2. This minterm 2 can be covered either selecting the PI–A– B– or A–D–.
Therefore, the minimal SOP solution is – – – – – – ––
(i) BD + BD + AB or (ii) BD + BD + AD.
Fig 5.14
Find the minimal POS and the SOP solution for the following function. F(A,B,C,D) = ☐M(3,4,5,7,11,13,15) ☐☐ (6,8,10,12) using QM method.
Phase-1 : Considering the don’t care maxterms as the normal maxterms and
–
treating all the maxterms as the minterms we find the prime implicants of F. This is done as follows in the first phase. Column1 Group Decimal No. of minterm Gr-1 4
8
Gr-2 3
5
6
10
12
Gr-3 7
11
13
Gr-4 15
Table 5.15 (a) Column-2
Group Decimal No.
A B C D of minterm A B C D

0 1 0 0 3 Gr(1,2) (4,5) 0 1 0 – 3
1 0 0 0 3 (4,6) 0 1 – 0 3
0 0 1 1 3 (4,12) – 1 0 0 3

0 1 0 1 3 (8,10) 1 0 – 0 PI 0 1 1 0 3 (8,12) 1 – 0 0 PI 1 0 1 0 3 Gr(2,3) (3,7) 0 – 1 1 3
1 1 0 0 3 (3,11) – 0 1 1 3
0 1 1 1 3 (5,7) 0 1 – 1 3
1 0 1 1 3 (5,13) – 1 0 1 3
1 1 0 1 3 (6,7) 0 1 1 – 3

1 1 1 1 3 (10,11) 1 0 1 – PI

(12,13) 1 1 0 – 3
Gr(3,4) (7,15) – 1 1 1 3
(11,15) 1 – 1 1 3
(13,15) 1 1 – 1 3

Table 5.15 (b) Column-3
Group Decimal No.
of minterm pairs A B C D
Gr(1,2; 2,3) (4,5,6,7) 0 0 – –
PI
(4,5,12,13) – 1 0 –
PI
(4,6,5,7) 0 1 – – ☐
(4,12,5,13) – 1 0 – ☐
Gr(2,3,3,4) (3,7,11,15) – – 1 1
PI
(3,11,7,15) – – 1 1 ☐
(5,7,13,15) – 1 – 1
PI
(5,13,7,15) – 1 – 1 ☐

–
The prime implicants of F are
– –
(8,10) = 1 0 – 0 = A B D
–
(8,12) = 1 – 0 0 = A C D
–
(10,11) = 1 0 1 – = A B C
–
(4,5,6,7) = 0 1 – – = A B
– (4,5,12,13) = – 1 0 – = B C
(3,7,11,15) = – – 1 1 = CD
(5,7,13,15) = – 1 – 1 = BD

Phase 2 : Finding the EPIs using PI table Prime
Implicants 3 4 5 7 11 13 15

– ☐ ☐ ☐(4,5,6,7) AB
– ☐ ☐(4,5,12,13) BC

(3,7,11,15) CD
☐ ☐ ☐ EPI (5,7,13,15) BD ☐ ☐ ☐ ☐
–
(10,11) ABC ☐
Table 5.15(d) : Prime Implicant table From the PI table it is seen that the minterm 3 is covered only by the prime implicant CD.Therefore, CD is the EPI. Remove the row for the CD and the columns for the minterm 3,7,11,15. From the remaining crosses within the PI after the removal of columns for 3,7,11,15 and the row CD we can see from TABLE 5.15(d) that the row for BC– is a dominant row which dominates over the rows A–B and BD. Therefore, remove the rows A–B and BD and keep only the row BC–. This term BC– becomes the EPI.

–
The minimal solution of F is
–
F = CD + BC
– – –
or, F = (C + D) (B + C).
–– – – –
The minimal SOP solution F = CB + DB + D C after simplification.
- Note : The prime implicants ABD and ACD cover only the don’t care terms. So, these two term are ignored in the PI table.
1. The truth table X Y f(X,Y)
0 0 0
0 1 0
1 0 1
1 1 1
[GATE 2012]

(a) X; (b) X+Y; (c) X☐Y (d) Y

_
2. A logic circuit implements the Boolean function F= XY + XYZ. It is found that the input combination X = Y =1 can never occur. Taking this into account a simplified expression for F is given by [GATE 2007]

_ (a) X + YZ. ; (b) X + Z; (c) X – Z; (d) Y + XZ
3. Let X = X1X0 ; Y = Y1Y0 be unassigned 2 bit numbers. The function F =1 when X>Y and F= 0 otherwise. The minimized sum of products expression for F is [GATE 2007] (a) Y1Y0 + X0Y0 +X X Y1 ; (b) X0Y1 + Y1Y0 + X1X2;
(c)
Y X + Y X X + Y Y X + X X Y
1 0 1 0 0; (d)X Y1 + X Y0 0 Y1 0 1 01 1 0 1
4. Simplify Boolean function represented in sum of product of minterms, F(x, y, z) = Ó(0, 2, 4, 5, 6) [ISRO 2016]
(a) z +xy ; (b) xyz ☐ xyz + xyz (c) xyz + x + y + z; (d) xy + yz + zx
5. Using K-map the Essential Prime Implicant and Prime Implicant of the 4 variable function F = ☐m(0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13, 15) are
(a) (abd),(c,bd, ad) ; (b) (acd), (b, c d,ad)
(c) (bdc), (c, bd, ad) ; (d) (abd), (a, b c, cd)
6. If f = BC + (A + B)C and g = A + B + C, then the simplified expression using K-map for f + g is
(a) B + C ; (b) A + C ; (c) B + D ; (d) A + D
7. Simplify the below function represented in sum of minterms [ISRO 2017] F(A, B, C, D, E) = ☐(0, 1, 2, 3, 8, 9, 16, 17, 20, 21, 24, 25, 28, 29, 30, 31)
(a) AD + (C+D) + ABC + (A + B + C) (b) ADE + (C + E)D + ABC D + AEC
(c) AD B + (C + B)+ CDE + (B + C + D) (d) AC + (D + E)+ AE + (C + D + E)
8. The prime implicants of the function
F(A,B,C,D) = ☐m(0,1,2,5,7,8,9,10,15) using QuineMcClusky method is
(a) ABC, AC D, BC D, BC, BD ; (b) ABC, BC D, C DA, BC, AB ;
(c) AC D, ABD, BCD, BC, B D ; (d) ABC, AB D, C DA, BC, BD .
9. The minimum SOP solution of the function F(A, B, C, D, E) = Óm(4,5,6,7,9,11,13,15,16,18,27,28,31) is
(a) AB D + ABE + ABC D + ABCDE + BDE; (b) ABC + BCD + CDE + ABCD + ABC DE ;
(c) BCE + B DE + ABCE + B DE + ABC DE; (d) ABC + A BE + ABCE + ABCDE + BDE
10. The minimum SOP expression for the logic function f is represented by the given Kmap is
[GATE 2009]
(a) QS + PRS + PQR + PRS + P QR ; (b) Q S + P RS + PQR + PRS + PQ R ;
(b) P RS + PQR + PRS + PQ R ; (d) PRS + PQR + PRS + P QR .
11. In the sum of product function [GATE 2012] F (X,Y,Z) = ☐(2, 3, 4, 5); the prime implicants are
(a) XY, XY (b) XY, XYZ, XYZ ; (c) XYZ, XYZ, XY; (d) XYZ, XYZ, XYZ,XYZ
12. The Boolean function F(A, B, C, D) = ☐(0, 6, 8, 13, 14) with don’t care condition of d(A, B, C, D) = ☐(2, 4, 10) can be simplified to [DRDO 2008)
(a) F = BD +CD + ABC ; (b) F = BD + CD + ABC D
(c) F =ABD + CD + ABC; (d) F = BD + CD + ABCD
161
6.1 INTRODUCTION

Logic circuits can be classified into two categories – (i) Combinational (ii) Sequential. A combinational logic circuit is defined as a circuit whose output (or outputs) at any instant of time is a function of the combination of the inputs applied at that time without regard to the previous

inputs. Each output of this type of

a circuit is a specific function of the

... inputs. The block diagram of a

combinational circuit is shown in

Fig 6.1. In this figure, there are N

logic-inputs i.e. each input may be
either in the logic-1 or logic-0 state, so there will be a maximum of 2N possible combinations of inputs to the circuit and for each combination of inputs, there is one and only one possible set output {Y1,Y2,.....YM}.

The functional dependance of each output is a fixed function of the input set and does not depend on the time of application of the inputs to the circuit. Thus, for any combinational circuit with M outputs and N inputs we may write Yi = Fi(I1,I2....,IN) where i = 1,2,....M.

In practice, this statement for the combinational logic circuit is not absolutely true because every physical logic device used in the design of the logic circuit introduces a propagation time delay, albeit small, in the signal path between its inputs and outputs. Therefore, in a combinational circuit, the output at time t is actually a function of the inputs of time t–tpd, where tpd denotes the signal propagation time delay through the logic device used in the circuit.

161

In chapter-3 we have seen the input-output behaviour of the basic gates AND,OR,NOT, EX-OR (XOR) and EX-NOR (XNOR) gates. Also, in chapter-5 we have learned to minimize a given switching function to get the minimal SOP and POS from a function. The purpose of this chapter is to use the knowledge of these two previous chapters to devlop a systematic design and analysis procedure keeping the following points in mind (i) Minimum number of logic gates to be used,
(ii) Minimum number of inputs to the individual gate to be used, (iii) Minimum number of interconnections between the logic gates to be used, (iv) Minimum propagation delay for the signal to go from the inputs to the outputs of the circuit.

The first three conditions give us the circuit with minimum cost and the last condition gives us the circuit with higher speed. If the design is based on the minimal solution, the first two conditions are satisfied.

6.2 AND-OR (OR-AND) Implementation of Logiccircuit

We know that any switching function can be expressed either in SOP or in POS for. The SOP expression means ORing of some ANDed terms and hence switching functions expressed in SOP can be implemented by AND-OR gate combinations. With AND gates, the ANDed terms are generated first and with the OR-gate, the ANDed terms i.e. outputs of all the AND gates are ORed together to get the final output. The number of inputs to any AND gate depends on the number of literals present in the ANDed term for which the AND gate is used and the number of inputs to the OR gate depends on the number of term of the function. In this case we have assumed that the primed and the unprimed form of the variables are available for inputting to the AND gates. If both the primed and unprimed form of inputs are available then those inputs are called “double rail inputs”, otherwise if only the unprimed inputs are available then these inputs are called “single rail inputs”. For single rail inputs we have to use logic-inverters or NOT gate to generate the primed inputs if required. The general form of the AND-OR circuit is shown in Fig.6.2(a).

Similarly, the POS expression can be implemented using OR-AND combination where

OR gates are used to generate the indivdual sum term and the AND gate is used to AND all the sum terms. Thus, the number of inputs to the OR gate depends upon the number of literals present in the individual sum term and the number of inputs to the AND gate depends on the number of sum terms present in the function. The general circuit-structure is shown in Fig 6.2(b).

So, it may be used that if a circuit designer start with minimal SOP or POS expression then he may get an economic design solution because in minimal solution the number of literals per term are reduced therefore the number of inputs to the gates are reduced and also, in a minimal solution the number of terms are reduced, hence the number of gates in the circuit. But, sometimes due to some restrictions imposed in the circuit design the designers are forced to violate the above rules and have to use more gates than required according to the minimal SOP or POS expression. This will be discussed in the section on hazards in “combinational circuits”(See6.10).

6.2.1 2-level AND-OR(OR-AND) Implementation

In this section we shall learn to realise a digital circuit using one OR gate and many AND gates when the output of the logic circuit is expressed in SOP form and using one AND gate and many OR gates when the output of the logic circuit is expressed in POS form. Also, we shall see how to implement a circuit directly from an expression of the output which is neither in SOP nor in POS form.

– – –
Consider an expression, X1X2+X3X4X5. In this expression there are two terms, X1X2 and
– –
X3X4X5. The first term (X1X2) can be realised using one 2-input AND gate with one input as
– –
X1 and the other input as X2. The second term (X3X4X5) can be realised using a 3-input
–
ANDgate with inputs X3,X4 and X5. Finally, using one 2-input OR-gate with its two inputs X
– – 1 X2 (i.e. the output of the 2-input ANDgate) and X3X4X5 (i.e. the output of the 3-input AND gate) in the AND-OR circuit the given expression can be implemented. The logiccircuit is shown in Fig 6.3(a).

This circuit is called a 2-level circuit. Levels are marked in the figure with dotted lines as level-1 and level-2. The counting of levels of a circuit starts from the output end. The total number of levels of the circuit is referred to by the maximum number of gates cascaded in series between a circuit-input and the output. From Fig.6.3(a), it is evident that any SOP expression can be implemented using 2-level AND-OR logic circuit. The OR gate is to be placed in the level-1 and the AND gates are to be placed in the level-2. One basic assumption for a 2-level AND-OR or OR-AND logic circuit is that the primed and unprimed input variables are available to the circuit. Otherwise, one has to use NOT gates to generate the primed inputs and there will be three levels altogether. The third level will be due to the presence of the NOT gates.– Let us consider an example of a POS expression (X1+X2)(X3+X4)(X1+X3). This expression can be implemented using three 2-input OR-gate-one for each sum term and one 3-input
–ANDgate for ANDing the three sum terms. The 2-level OR-AND circuit is drawn in Fig.6.3(b) assuming that the primed input X2 is available directly.

From the above two examples we may note that there is no restriction regarding the number of inputs to the gates present in the two levels. But, for a large number of inputs beyond a certain limit a logic-gate may not work correctly. This is called the Fan-in restriction of the logic-gates.

Following assumptions are made to realise a 2-level AND-OR(OR-AND) logic circuit. 1. (a) Many ANDgates in level-2 and only one OR-gate in level-1 of the circuit for realising the SOP expressions.
(b) Many OR-gates in level-2 and one ANDgate in level-1 of the circuit for realising the POS expressions.

2. Double rail inputs are available.
3. No limitations regarding the number of inputs to the logic gates.

Implement the function F = ☐m(1,3,4,5,10,11,12,13,14,15) using a 2-level ANDOR circuit.
Using a 4-variable K-map as shown in Fig 6.4(a) we may get the minimal

– – –
SOP expression of the given function as FSOP= XY + WY + W X X level AND-OR circuit is shown in Fig 6.4(b).
Design a minimum cost 2-level circuit to implement the following function F =☐m(5,6,7,9,10,11,13,14,15) using AND and OR gates only.
Using the 4-variable K-maps [Fig6.5(a) and Fig.6.5(b)] we get the SOP and POS expression of the given function as follows :
FSOP = XZ + XY + WZ + WY ; minimal SOP expression from Fig 6.5(a) and FPOS = (W+X) (Y+Z) ; minimal POS expression from Fig.6.5.(b).
Fig 6.5(a)
Fig 6.5(b)

The circuits for FSOP and FPOS are shown in Fig.6.5(c) and 6.5(d) respectively. The circuit in Fig6.5.(d) is cost effective compared to the circuit of Fig.6.5(c) because it needs less number of gates.

Fig 6.5(d)Fig 6.5(c)
6.2.2 Multilevel AND-OR (OR-AND) Implementation In the section 6.2.1, we have learned the procedure for designing a 2-level AND-OR or ORAND circuit. In that method, no restriction was imposed on the maximum allowable number of inputs to the gates. If this restriction is taken into account then sometimes it may not be possible to design the logic circuits with 2-level AND-OR or OR-AND network.

To satisfy this limitation, we must modify the design by increasing the number of levels of the circuits to maintain the limitation of the number of inputs. But there are no systematic guidelines known for the modification. Thus, it is done heuristically and the resulting networks may not lead to the minimal solution.

Design a logic circuit to realise a function F = WX–YZ–+WX–Y–Z using only AND and OR gates. The number of inputs to any gate should not exceed 2. This function could be implemented

input AND gates (assuming double rail inputs

are available) and one 2-input OR gate. But,

according to the problem no logic gate should

have inputs greater than 2. To satisfy this

restriction we rewrite the given function after a

little modification as follows :

– – –

– – ––
F = WXYZ+ WXYZ+ WX·(YZ+YZ).
This alternative way of writing produces Fig 6.6
three product terms WX–, YZ– and Y–Z with two

– –
literals and one sum term YZ + YZ. These 3 product terms and one sum-term can be generated Z. These 3 product terms and one sum-term can be generated
– – – input AND gate to get WX ·(YZ+YZ). The 3-level circuit is shown in in Fig.6.6.This type of circuit is called AND-OR-AND circuit. Thus, factoring increases the levels of the circuit but reduces the number of inputs to each gate. For this circuit, number of level=3, number of gates = 5 and the total number of inputs = 10.

Design a logic circuit to realise a function F = (W+X –+Y–+Z–)(W– +X–+Y+Z–) using only AND or OR gates. The number of inputs to any gate should be greater than 3. The double rail inputs are available.

The given function may be written by multiplying the two terms so that,
– – – – – – – – – – –
F = W(X+Y+Z) +W(X+Y+ Z) +(X+Y+Z) (X+Y+Z).
– – –
–
This expression has no terms with literals greater than three, to generate (X +Y+Z) and
– (X +Y+Z) we need two 3-input OR-gate. For the first, second and the third term we need three 2-input AND gates and finally, for OR-ing the three terms we need another 3-input OR-gate. The circuit is shown in Fig. 6.7(a).This circuit requires 3 levels, 15 gate-inputs and 6 gates. This circuit-structure is called OR-AND-OR structure.

The same example can be solved with the help of much simpler circuit. This is done by– – – – completely multiplying the expression to a much simpler form F = Z+ X+ WY+WY.

This reduced form of the given function can be implemented using the 3-level circuit with only AND and OR-gates. This is shown in Fig. 6.7(b). This circuit needs 5-gates with 2inputs in each. The total number of inputs are 10.

Fig 6.7(a)
Fig 6.7(b)

A combinational switching circuit has 4 inputs (W,X,Y,Z) and one output F. The output F = 0 if 3 or 4 of the input bits are 0.
(a) Write the POS expression for F.
(b) Using AND-OR-AND structure, find a 3-level circuit to realise F with 5 gates and 12 inputs.

We draw a 4-variable K-map as shown in Fig.6.8(a) with minterms m0= m1 = m2 = m4 = m8 = 0 and m3= 1, m5 = m6 = m7 = 1 and m9 = m10 = m11 = m12 = m13 = m14 = m15 =1. From the K-map we get the minimal POS form as
F = (W+X+Y) (W+X+Z) (W+X+Z) (X+Y+Z)
= (W+X+YZ) (Y+Z+WX); using the theorem (A+ B) (A+ C) = A+ BC.
6.4Fig 6.8(a)
6.4 Fig 6.8(b)
Using this expression we may draw a 3-level AND-OR-AND circuit with 5 gates and 12 inputs as shown in the Fig.6.8(b).
6.3 2-LEVEL LOGIC CIRCUIT IMPLEMENTATION USING ONLY NAND GATES

We know from the earlier discussions that any switching function which can be expressed in the SOP form can be implemented using a 2-level AND-OR structure provided the double-rail inputs are available. In this section we shall see how a 2-level AND-OR logiccircuit can easily be transformed to a circuit with NAND gates only. It will be shown that this transformation can be done by replacing each AND gate and OR gate by the NAND gates keeping all the interconnections of the input/outputs unchanged. For a minimal NAND implementation we should start with a minimal SOP form of the function.

But a logic function may not be always in purely SOP form and may contain one or more terms containing single literal along with the normal product terms. For example, the
– – – – – – – –
expression X1X2X3 + X1X2X3 + X4 + X5 contains two product terms X1X2X3 and X1X2X3 and
– – –
X1X2X3 having 3 literals in each and two terms X4 and X5 of single literal.

Let us now see the 2-level NAND-NAND implementation of the functions consisting of (a) purely sum of product terms (b) a few terms of single literal along with the product terms and (c) all the terms of single literal. The procedures for implementating the three cases are described below.

Case A : Purely sum-of-product form
The function for this case may be written as
F = p1 + p2 + p3 + ....+ pn; where p1, p2 ... etc. are the product terms =1 2p ·p ...pn ; using De Morgan theorem.

The product terms may

contain the variables in the true

and complemented form. If the

double-rail inputs are available

then we can realise this type of

function with 2-level NAND

structure. This is shown in the

Fig. 6.9. If the double rail inputs

are not available then we require

extra NAND gates in level-3 to

complement the input variables.

Consider the following examples Fig 6.9

for illustrations.

Design a 2-level NAND-NAND circuit for the function F = ☐m(1,3,5,9,11) + ☐☐(13,15). Draw the equivalent AND-OR circuit for this function. Discuss how the NAND-NAND circuit can be developed directly from the AND-OR circuit and vice versa.

The minimum SOP form of the function obtained using 4-variable K-map is F
– –
= YZ + XZ. This can be expressed as F = YZ + XZ = (YZ)·(XZ).
This can be implemented using 2-level NAND-NAND structure [Fig. 6.10(a)].
– –
We may draw the 2-level AND-OR circuit for the same function F = YZ + XZ. The ANDOR is shown in Fig. 6.10(b).

Comparing these two circuits we can see that the

replacement of AND and OR gate of level-2 and level-1

of the AND-OR circuit by the NAND gates yields the

2-level NAND-NAND circuit. No change of

interconnections of the input-output signals are

interconnections of the input-output signals are

required for this transformation. The reverse is also true

i.e. for converting one NAND-NAND circuit to one

AND-OR circuit.

Another way of conversion from AND-OR circuit

to NAND-NAND and viceversa directly from the

circuit diagram is to utilise the double negation property

of Boolean algebra i.e. X = X. Negation of the logic

signal is symbolised with a bubble attached to the logic

gate. So, addition of two bubbles along a signal path

does not alter the logicstate of the signal. An extra

bubble is attached to each output of the NAND gate of

level-2 and to each input of the NAND gate of level-1 of

the circuit in Fig.6.10(a). The circuit diagram with the

extra bubbles is shown in Fig.6.10(c). From this figure

we can see that the gate-1 and gate -2 represents AND

gate (NAND followed by negation) and gate-3

represents one OR-gate (A.B = A+B). Thus the circuit

in Fig.6.10(c) is the same as the AND-OR structure

shown in Fig.6.10(b). Similarly, if we start from AND

OR circuit of Fig. 6.10(d) and add two extra bubbles

along the signal path we can get the NAND-NAND

circuit of Fig.6.10(a). This is shown in Fig. 6.10(d). The

OR-gate with active low inputs in level-1 means aFig. 6.10
NAND gate (A+B = AB ).
Fig 6.10(d)
Implement each of the following functions using 2-level NAND-NAND circuit. Also, find out the 2-level AND-OR equivalent circuit for each.
– – – – – – – – –
(i) F1 = (X2 + X4) (X1 + X3 + X4) (X1 + X2 + X3+ X4) (X1+X2+X3+X4)
(ii) F2 = ☐m(1,4,7,10,14,15)
(i)– The minimal solution SOP form of function F1 is
– – – – –
F1 = X1X2 + X2X3 + X3X4
and this can be written as
F1= (X X1 2 2 3)·(X X )·(X X3 4)
This is implemented using 2-level NAND-NAND gate circuit as shown in Fig. 6.11(a). The AND-OR circuit is also shown in the Fig.6.11(b).
Fig 6.11(a)
Fig 6.11(b)
(ii) The minimal SOP solution of F2 is
– – – – – – –
F2 = XYZ + WYZ + W XYZ + W XYZ
Fig 6.11(c)
Fig 6.11(d)
which can be written as
F2 = (XYZ) · (WYZ) · WXYZ) · (WXYZ)
This is implemented using NAND gates in 2-levels [Fig.6.11(c) and its AND-OR equivalent circuit is shown in Fig. 6.11(d).
Case B : Product terms along with terms of single literal
The function for this case may be written as F = p1 + p2 + ....+ pn +(X1 + X2 +....+ Xm) where p1, p2, ....., pn are the product terms and X1, X2,...., Xm are the terms of single literal.
This function F may be written as F = 1 2(p p ....pn 1 2)·(X X ....Xm) The general form of the NAND circuits in two levels are shown in Fig. 6.12(a) and Fig.6.12(b).
Fig 6.12(a)
Fig 6.12(b) Fig.6.12(a) is one from where the complement of the terms having single literals is not available and Fig. 6.12(b) shows the other form where complement of each such term is available for direct connection to the NAND gate in level-1. Following examples may be considered for explanation of this case.

Implement the following functions using 2 level circuit with all NAND gates. F1 = ☐m(0,1,2,3,4,8,9,10,11,13) + ☐☐(14,15)
Using a 4-variable K-map one can get the minimal SOP form of the function F
– – – –
= X + WZ + W YZ. This can be written as F = (X)·(WZ) ·(WYZ) using De Morgan’s law. The NAND-NAND circuit is shown in Fig
6.13.

Case C : When the product term is

absent

For this case the function F is of the
form
F
1 = X1 + X2 = ....+Xm, where X1,
X2,....Xm are all of single literal.
Fig 6.13

This function F can be written as F
=X· X ....X using De Morgan’s2 m
theorem. The implementation of this function F by 2-level NAND gates is shown in Fig. 6.14(a) and by 1-level NAND gate is shown in Fig 6.14(b).

Fig 6.14(a)
Fig 6.14(b)
6.4 2-LEVEL LOGIC CIRCUIT IMPLEMENTATION USING ONLY NOR GATES

Like the 2-level logic circuit using NAND gates, we may use only NOR gates for the same purpose. For the design of a logic circuit with all NOR gates we may follow the dual of all steps followed for the design using NAND gates because NOR operation is dual of the NAND operation. Consequently, the implementation of a function with NOR gates requires the function F to be simplified in a POS form.

But, in practice it is not always possible to have an expression purely in POS form and may contain some terms with single literal along with the sum terms. The general form of the expression for this NOR logic design may be of the form F = (S1·S2.....Sn) · (X1·X2.....Xm) where S1, S2,....Sn are the sum terms involving at least two literals and X1, X2,.....Xm are the terms of single literal. Using DeMorgan’s, we may write, F = (S1☐ S2 ☐ ☐Sn)☐(X1☐X2☐....☐
... Xm)
Fig 6.15(a)
Fig 6.15(b) Using the two forms of the fucntions we can draw the 2-level OR-AND and NOR-NOR circuit as shown in Fig.6.15(a) and Fig.6.15(b) respectively. Fig.6.15(b) shows that we can transform any OR-AND circuit to a NOR-NOR circuit by replacing the AND and OR gates by the NOR gates without changing the gate interconnections. If there are some terms of single literal like X1, X2.....Xm present in the minimised expression then these terms should be complemented before connecting them to the NOR-gate of level-1 whereas for the ORAND circuit [Fig.6.24(a)] these terms directly as inputs to the AND gate of level-1. If the complements of X1,X2,...Xm are not available, they should be complemented using NOR gates used as an inverter in level-2 in case of NOR-NOR implementation.

Implement the logic expression X–YZ– + XZ+ Y– using only NOR gates. Double rail
inputs are available.

– – –
F = XYZ + XZ + Y
= XYZ + XZ + Y
= (X+Y+Z)(X +Z)Y, using DeMorgan’s theorem.
= (XZ +XY + YZ + XZ) Y
= (XYZ) · (XYZ) = (X+Y+Z)·(X+Y+Z) = S1 ☐ S2 ,

– – – –
where S1 = X + Y + Z and S2 = X + Y + Z.
The NOR-NOR circuit is shown in Fig.6.16.
Fig. 6.16
Let F(W,X,Y,Z) = ☐m(0,1,3,5,15). Implement this function using only NOR gates. Double rail inputs are available.
Using K-map we can get the minimal POS form of the function as
– – – – – –
F = (Y+Z) (X+Z) (W +X)(W +Y)(W+X+Y)
= S1☐S2 ☐S3 ☐S4☐ S5 where
– – – –
S1= Y + Z; S2 = X + Z; S3 = W + X; S4 = W +Y
–
and S5= W + X + Y
This minimal POS form can be implemented using NOR-NOR circuit. This is shown in Fig.6.17.
6.17
6.5 MAP FACTORING METHOD

There is another useful method known as Map Factoring Method for the direct design of multilevel NAND gate circuit. This new technique is based on Karnaugh map but it is an extension of the ideas used for the design of 2-level AND-OR or OR-AND network. The designers need very good practice and intuition to get the minimal solution. A good feeling about the use of this method can be obtained.

Construct a multilevel circuit containing only four 4 NAND gates to implement the function F = A–BD + ACD– + BC–D + AB–C.
The function F is mapped in a 4-variable K-map. This is shown in Fig.6.42(a).

From the figure it is noted that the minterm box-15 contains a 0. If this entry would be 1
then the solution from the K-map would be BD + AC. But the presence of 0 in the box-15
can be thought as the absent minterm ABCD. The absence of this minterm can be represented as ABCD . So, the two clustering of the Fig. 6.18(a) can be written as Fig 6.18(a)
Fig 6.18(b)
(i) BD but NOT ABCD i.e. BD ( ABCD ) and (ii) AC but NOT ABCD i.e. AC ·( ABCD ). Thus, from the K-map we may write the solution as
F = BD( ABCD )+ AC( ABCD )
= BD(ABCD)· AC(ABCD)
This expression can be realised using all NAND gates. This is shown in Fig 6.18(b).
Use map factoring method to implement the function F = AB– + AD– + B–C + CD + AC using all 2-input NAND gates.
The function is mapped in a 4-variable k-map as shown in Fig 6.19(a). In this example we have to use all NAND gates with two inputs. Therefore, during looping of the boxes of the k-map we should be careful to generate terms with not more than two literals. This problem is solved using POS form as follows.
The boxes 0,1,4 and 5 gives a sum term (A+ C) of two literals. The boxes 5,7 and 13 contain all zeros but we can’t form a group of –4 with these 0’s because we have a 1 in box
– –
15. If we assume a 0 in this box then the loop of boxes –5,7,13,15 gives a term (B– – +D) but sure to the 1 in box-15 we can write for the boxes 5,7,13 and 15 as F1 = (B+D) OR ABCD or Therefore, from the k-map we can write
– –
F = (A+C) · [(B+ D) + ABCD] in POS form.
Fig 6.19(a)
Fig 6.19(b) The last term ABCD contains 4

literals. To reduce the number of literals

to 2, the best choice is to consider

another group of 4 boxes-10,11,14 and

15. This is shown in Fig.6.19(b). Then

the function from this k-map is F =

– –
(A + C)[(B + D ) + AC]. This can be
manipulated as

– –
F = (A+ C) (B + D) + AC
=
(AC) ☐(B· D) + AC
6.19
= ( A C )( BD ) ·(A C )
This function can easily be realised by a 3-level circuit with all 2-input NAND gates. The circuit is shown in Fig.6.19(c).
Implement the function F = A–C + AC– + B–C using all NAND gates.
The given function is mapped in the 3-variable k-map (Fig.6.20(a)]. Assuming the entry box-7 to be 1 we may write the solution as F = C + A. But due to the presence of 0 in the box-15 we may write for the two clusterings as follows :

(i) C but NOT ABC i.e. C(ABC)
(ii) A but NOT ABC i.e. A·(ABC) Fig 6.20(a)
Fig 6.20(b)
The term ABC implies the absence of 1 in the above box 7.

Therefore, F = C · (ABC)+A· (ABC) = ☐ ☐A· ABC ·C·(ABC) = (AX)·(CX) = Y.Z

where X = ABC , Y = AX and Z = CX
The circuit corresponding to this final form of the function is shown in fig.6.22(b).
Implement the function F = AB C + ABC + ABC using all NAND gates. The given function is mapped in a 3-variable k-map (Fig.6.21(a). Assuming 1 in the box-5 we may loop the boxes as shown in Fig.6.21(a). But the absence of 1 in the
– –
box may be indicated by a term ABC in each reduced term BC, AC and AB. So the reduced expression can be written as
Fig 6.21(a)
Fig 6.21(b)
F = AB ABC + AC ABC + BC ABC
F = AB(ABC) · AC(ABC) · BC(ABC)
= (AB(X) · AC(X) · (BC)(X) where, X = ABC = W.Y.Z, where = (AB) · X, Y = (AC)(X) and Z = (BC) · X The 3-level circuit using all NAND gates are shown in Fig. 6.21(b).
Design an Exclusive -OR circuit using four 2-input NAND gates.

– –

The expression of 2-input Exclusive-OR function is F = XY + YX. This expression is mapped in a 2-variable k-map [Fig.6.22(a)]. Assuming 1 in the box-3 we may obtain two reduced terms X and Y as indicated in the figure. But the absence of 1 in the box-3 may be indicated by ANDing each term by (XY)because the presene of 1 in box-3

Fig 6.22(a)
Fig 6.22(b)
means a term XY. So, the expression out of the two loops considering the absence of 1 in the box-3 may be written as :
F = Y(XY)☐X(XY) = Y·(XY) · X(XY)
The NANDgate circuit corresponding to this final expression is shown in Fig.6.23(b).
Implement the following function using all NAND gates.
F = Y–Z– + X–Y– + W–XZ + WXZ
The maximum number of inputs to any NAND gate may be 3. The function F is mapped in a 4-variable K-map Fig. 6.23(a). As the restriction to the inputs of the gates is maximum of 3, so any loop of 1s should encircle atleast 2 boxes and the number of 0s in these of loop-of-1s should be such that these absent minterms (due to looping of 0s) contribute terms of maximum 3 literals.

Keeping the ideas in mind the boxes of the K-map have been grouped as shown in Fig.6.23(a). Assuming 1s in the boxes-3,11,13 and 15 we may obtain the reduced terms as Z, WX and Y

– –

Z . To take into account of the effect of absent minterms i.e. the 0s of the boxes-13 and 15 and the boxes-3 and 11 in the terms WX and Z we encircle the 0s of the box-13 with 15 to get a term WXZ and the 0s of the box-3 with 11 to get a term XYZ. So, including the effects of 0’s in the two terms we may write the reduced expression of F as

Fig 6.23(b)Fig 6.23(a)

F = YZ + Z( WXZ)( XYZ) + WX ( WXZ)
= Y Z·Z(WXZ) (XYZ)·WX (WXZ) = A·(Z·B·C)·(WXB) where A = YZ, B = WXZ and C = XYZ The implemented circuit is shown in Fig. 6.23(b).
Implement the function W–X–Y + W–YZ + WY–Z + WX–Y– with all NAND gates subject
to a fan-in of 3.
The function is mapped in a 4-variable K-map Fig.6.24(a). Assuming 1 in the boxes 6,10,11,14 and 15 we get the reduced

term Y and assuming 1 in the boxes 10,11,12,14

and 15 we get the second reduced term as W.

These two groups cover all the 1s of the map.

But due to the presence of 0s in the boxes we

have to AND the terms Y and W with the

cluster of 0s which were assumed to be 1.

During clustering of 0s we should be careful

that no groups should produce a term with

more than three literals. So, in this map it may

Fig 6.24(a) be noted that the two boxes 4 and 6 have been combined with box, 12 and 14, for the formation of a group of 4 though the boxes 12 and 14 are not included in the group-of-8 boxes which give the terms Y and W. From the K-map we may write F = Y(XZ)(WY)☐ W(XZ)(WY)
=
Y(XZ)(WY)·W(XZ)(WY)
The circuit corresponding to this expression is
shown in Fig.6.24(b).
6.6 DUAL PROPERTY OF THE
Fig 6.24(b)
CIRCUIT

Dual of a function F can easily be realised if AND gates and OR gates of a 2-level or a multilevel AND-OR or OR-AND circuits are replaced by their duals i.e. AND by OR and OR by AND. Similarly, for a 2-level or multilevel NAND circuit if all NAND gates are replaced by their duals i.e. NOR gates and for a NOR-circuit if all the NOR gates replaced by NAND gates then the dual circuit can be realised. For example the circuits of Fig.6.25 shows some dual circuits. In this figure the circuits of the left side and the circuits of the right are dual to each other.

Fig 6.25(a)
Fig 6.25(b) Fig. 6.25(c)
Fig. 6.25(d)
6.7 XOR IMPLEMENTATION OF THE LOGIC CIRCUITS

The XOR gates can be used for designing the logic circuit using the properties of the XOR operator as described in Chapter 4. We already know that the XOR operator is not universally complete by itself, it requires another operator AND or OR to complete the set. Thus, for realising the logic circuit it is not possible to use only XOR gates but we need either AND gate or OR gate along with it.

6.7.1 Transformation of a SOP Expression into
an Expression Containing XOR and AND Gates Only We have learned from the chapter-4 that a SOP expression contains ANDed terms and one ANDed term is connected to another by the OR operator. Also, it is known from the properties of the XOR operator that an OR operator between the minterms can be replaced by the XOR operator i.e. mi + mj = mi☐ mj for i☐ j and any variable X with cover-bar in a term can be replaced by 1☐X. Using these two properties we may transform any canonical SOP into an expression containing only XOR and AND operators.

In some applications XOR-AND realisations gives a better solution than with AND-OR NAND-NAND or NOR-NOR logic because the XOR-AND circuit may require smaller number of gates and the interconnections.

Transform F = XYZ– + XY–Z– + X–YZ into an expression containing only XOR and
AND operators.

– – – –
F = XYZ + XYZ + XYZ
– ☐– – ☐–
= XYZ XYZ XYZ ; replacing each ‘+ ’
operator by☐ because each term is a minterm.
= [XY(1☐Z)]☐ [X(1☐Y)(1☐Z)] ☐ [(1☐X)YZ];
replacing each overbar operator.
= (XY☐XYZ) ☐ (X☐XZ☐XY☐XYZ☐(YZ☐
XYZ); using distributive law.

= XYZ ☐ XZ☐ YZ☐ X; eliminating the even

number of repeated terms from the XOR-AND

expression.

The 3-level circuit drawn using the final
Fig 6.26
expression is shown in Fig.6.26.
Implement the function F = X–YZ– + X–Y–Z + XZ–W + XZW– using the XOR and AND
gates. Compare this XOR-AND circuit with the NAND-NAND circuit.
F = X–YZ– + X–Y–Z + XZ–W + XZW
– – –
Replacing X, Y, and Z by 1☐X, 1☐Y and 1☐Z respectively and the ‘+’ operator by☐ operator we get, F = [(1 ☐X)Y(1☐Z,)]☐[(1☐X)(1☐Y)Z]☐☐X(1☐Z)W☐[XZ(1☐W)] = (Y☐YZ☐XY☐XYZ)☐(Z☐YZ☐XZ☐XYZ)☐☐XW☐XWZ)☐☐XZ☐XWZ)

= Y☐XY☐Z☐XW; eliminating the repeated even number of terms from the XOR-AND expression.
The XOR-AND circuit based on this expression is shown in 6.27(a).
Fig 6.27(a) Fig 6.27(b) The same function can be expressed using only NAND operators. This is shown as follows :
F = XYZ + XYZ + XZW + XZW = X(YZ+YZ) + X(ZW + XW)
= X(YZ+YZ)·X(ZW + ZW)
= X(YZ)·X(YZ)·X(ZW)· ZW) The logic circuit using all NAND gates can be drawn for this expression. This is shown in Fig. 6.27(b) assuming double rail inputs for X,Y,W and Z are available. Comparing the circuits of Fig. 6.27(a) it may be said that the requirement of number of gates and the number of gate inputs in circuit of Fig.6.27(b) is larger than that of Fig.6.27(a) even if we do – – –
not use extra NAND gates to produce X from X,Y from Y and Z from Z.
1. Which one of the following circuits is not equivalent to a two input XNOR gate? 2. The output Y in the circuit below is always “1” when [GATE 2011]

(a) two or more of the inputs P, Q, R are ‘0’
(b) two or more of the inputs P, Q, R are ‘1’
(c) any odd number of inputs P, Q, R is ‘0’;
(d) any odd number of inputs P, Q, R is ‘1’

3. If the input to the digital circuit (shown below) consisting of cascade of 20 XOR gates is ‘X’ then the output ‘Y’ is equal to
(a) 0; (b) 1; (c) X ; (d) X 4. All the logic gates in the circuit shown below have finite propagation delay. The circuit can be used as a clock generator if [GATE 2006]

(a) X = 0; (b) X = 1; (c) X = 0 or 1; (d) X = Y 5. For the ring oscillator designed with NOT gates having the propagation delay of each inverter is 100 pico-second. What is the fundamental frequency of the oscillator output?
(a) 10 MHz; (b) 100 MHz; (c) 1 GHz; (d) 2 GHz.
6. The CMOS circuit shown below implements the function [ISRO 2017]
(a) (A + B)C + D; (b) (AB + C) + D; (c) (A + B)C + D; (d) (AB + C)D. 7. The Boolean expression for output of the logic circuit shown in the figure is [ISRO 2007]
(a) Y = AB + AB + C ; (b) Y = AB + AB + C ;
(c) Y = AB + AB + C ; (d) Y = AB + AB + C
8. Maximum number of 2-input NAND gates that will be required to implement the function Y = AB + CD + EF is [ISRO 2008] (a) 4; (b) 5; (c) 6; (d) 7 7

LOGIC FAMILIES

7.1 TRANSISTOR AS AN INVERTER

The gates of TTL logic family are basically based on the action of transistorised inverter. The simple inverter circuit is shown in Fig.7.1. In this circuit one resistor RB is connected to the base and the collector is pulled up to the power supply VCC using the resistor RC. The output Vout is measured from the collector with respect to the ground. The external load connected to the collector of the transistor Q is considered to be resistive in nature. Later we will see the detrimental effect of the capacitive load on the speed of operation of the circuit. Also, we will see how the speed of the inverter can be improved by replacing the passive pull-up resistor RC by an an device. The switching action of the above inverter circuit can be understood from the following discussions.

When the input voltage Vin is larger than the turn-on voltage Vf of the baseemitter junction, then the base current IB is
IB = (Vin–Vf) /RB

For silicon transistor V ☐ 0.7V. For the forward biasing of the base emitter junctionf
the base voltage should be higher than the emitter voltage by at least 0.7V. The current flowing through the collector of this transistor will be IC = ☐IB when transistor is in active region, IC < ☐IB when the transistor is in saturation and ideally IC = 0 for cut-off condition.

187

For saturation both the junctions– baseemitter and collector-base junctions are forward biased and for cut-off the base -emitter should be reverse biased or at least the base-voltage should be lower than 0.7V with respect to the emitter. Unlike analog circuits, the logic circuits are operated only in following two states of the transistor.

(i) Saturation and
(ii) Cut-off

(i) Saturation : We know that in saturation, the collector current IC is no longer equal to☐IB. But when the transistor is just arriving at saturation from the active region we may write Ic(sat)= ☐IB(0N) where, IB(ON) = (Vin–Vf)/RB ... ...(7.1) Under this condition the voltage drop across the collector and emitter of the transistor becomes VCE = VCE(sat)☐ 0.30V or less. From the Fig.7.1 and using Equn.7.1 we may now write the expression for Vout as Vout = VCE(sat) = Vcc – RcIc(sat)
=
V
cc
–
☐
☐ Vin - Vf ☐
☐ ☐ Rc ... ...(7.2)➔ RB ☐
Rearranging this equation we get the input voltage Vin to reach saturation as
☐ Vcc- VcE(sat)☐☐
V
☐
RB ☐ ... ...(7.3)in(sat)= ☐☐ ☐☐R ☐
C ☐☐ ☐☐➔
For RB = 2K☐, Rc = 1K☐,☐ = 100, Vcc = 12v, Vf = 0.7v and VCE(sat) = 0.2v we get from Equn(7.3) Vin-(sat) = 3v and
Ic(sat) = [Vcc – VCE(sat)]/Rc = 11.8mA. Also we know that
☐IB(ON) = Ic(sat)
☐
☐ Vin - Vf ☐= Vcc- VCE(sat)
☐ ☐ ... ...(7.4)➔ RB ☐ Rc
or, RB ☐ ☐.RB is Vcc >>VCE(sat) and Vin>>Vf.RC RC

Eqn(7.4) shows that Rc must be approximately RB/☐ to get the minimum value of Ic(sat) to start saturation. Since the value of☐ depends heavily on the temperature and varies from transistor to transistor even of the same type, it is good practice to use Rc>>RB/☐min where ☐min is the minimum of☐ as quoted in the data sheet of the transistor.

(ii) Cut-off : When Vin< VBE(on) (☐ 0.6v for silicon transistor) the collector current Ic = 0 and output voltage across the external load is Vout= Vcc.

Thus, for Vin< VBE(on) the Vout = Vcc and for Vin>Vin-sat, the Vout = VCE(sat) = 0.3V or less. Therefore, we get the inverse of the logic state of the input at the output. Between cut-off and saturation region the transistor passes through the constant current region or forwardactive region. For this region we may write : Vout = Vcc – IcRc
= Vcc – ☐IBRc ; Ic = ☐IB is valid for this region.
☐ Vin - Vf ☐ = Vcc – ☐☐ ☐ RC➔ RB ☐
=
-
☐RC Vin ☐ ☐Vcc ☐ ☐Rc ☐
R
☐ ☐
B ➔ RB ☐ for VBE(ON) < Vin < Vin-sat ... ...(7.5) If this Vout is plotted against Vin then we

get a variation as shown in Fig.7.2. This curve

is called the transfer characterisitc of the

inverter. The curve shows three regions of

operations of the transistor. In the active

regions Vout falls linearly with the increase of

Vin with a slope –☐Rc/RB. This also indicates

that the large ratio of Rc /RB.This also indicates

that the large ratio of Rc/RB produces a sharp

change from cut-off to saturation and vice

versa. This sharp change leads to the fast

switching between cut-off and saturation

state at the output.This fast switching is

desirable for the high speed digital circuits.

7.2 BASIC TTL NAND GATE CIRCUIT

The basic TTL inverter circuit discussed above can be converted into a NAND circuit if the input transistor Q1 is replaced by a multiemitter transistor. Multiemitter transistor can be fabricated very easily using the IC fabrication technology. The circuit for a 2-input NAND gate is shown in Fig.7.3 and the equivalent circuit of a 2-input multiemitter transistor is shown in Fig.7.4 where the two base inputs B1 and B2 of the transistors Q☐ and Q☐☐ are shorted together to have one equivalent base input B. Similarly, C is the equivalent collector of this composite transistor obtained by shorting the two collectors C1 and C2. E1 and E2 are the emitters and they are not connected. From this equivalent circuit it is evident that the equivalent base point B is clamped to 0.7v when at least one emitter input is at low voltage because of forward biasing of that transistor having its low emitter voltage. On the

otherhand when all the emitter inputs are high then the multiemitter transistor enters into the inverse active mode and the equivalent base input attains high voltage as described earlier. The constructions of multiemitter transistors is advantageous because it reduces silicon chip area and eliminates the parasitive capacitances that arise from individual devices.

7.2.1 Analysis of 2-input NAND Gate Circuit
We know analyse the complete circuit of the 2-input TTL NAND circuit shown in Fig.7.3 for the following two cases.
(i) All the emitter inputs are HIGH, (ii) Only one emitter input or both are Low. This analysis can be equally applied to the TTL NAND gate circuit having more than two inputs.
Case I : When both the inputs are HIGH : When the input voltage Vinat both the emitters of Q1 as shown in Fig.7.5 starts increasing from a low value then the base voltage VB1 of Q1 increases and follows the equation VB1 = Vin + 0.7v.

When VB1 just exceeds the sum of the turn-on voltages of the following three junctions in series (i) base -to-collector of Q1, (ii) base-to-emitter of Q2 and (iii) base-to-emitter of Q3, then these three junctions become forward biased. The voltage at B1 with respect to ground becomes VB1 = VB1C1(Q1) + VB2E2(Q2) + VB3E3(Q3)☐ 0.6V + 0.7v + 0.7v = 2.0v and the minimum value of Vin required for this purpose is Vin = VB1– Vf(BE)Q1= 2.0v –0.7v = 1.3v. Once this voltage is reached at Vin the base voltage VB1of Q1 is clamped to 2.0v with respect to ground (emitter of Q3).Therefore further increase of the input voltage Vin will make the baseemitter junction of Q1 reverse biased and the transistor Q1 enters the inverse active mode. Under inverse active condition Base current IB1of Q1 = Vcc -VB1 =5v- 2v = 0.75mAR1 4k☐
Collector current IC1of Q1 under inverse active mode = (1 +☐r)IB1☐ IB1= 0.75mA. Total emitter current or the input current IIH of Q1 when both inputs are high (inverse active mode) is IIH = ☐rIB1= 0.02(0.75mA) = 0.15☐A (assuming☐r = 0.02).

As the transistor Q1 may be considered as two seperate transistors with their bases and may be considered as two seperate transistors with their bases and input NAND gate is IA = IB = IIH /2. In general for N-input NAND gate the individual emitter current will be IIH/N = ☐rIB1/N when all the emitter inputs of Q1 are high. The directions of the current IIH is shown in Fig.7.5.

Collector Voltage Vc1of Q1 = VB1– VBC(Q1)= 2.0v – 0.6v = 1.4v Base current IB2of Q2 = Ic1= 0.75mA
Base voltage VB2of Q2 = Vc1= 1.4V
Collector voltage Vc2of Q2 = Vc2= VCE(sat)Q2 + VBE(Sat)Q3 = 0.3v + 0.7v = 1v Collector current IVcc - Vc2 =5v -1v = 2.5mAc2of Q2 = R2 1.6k☐
Emitter current IE2of Q2 = IB2+ Ic2= 0.75mA + 2-5mA = 3.25mA.

The emitter current IE2of Q2 is divided into two parts as IB3and IR3as shown in Fig.7.5. As the voltage across the base emitter junction of Q3 is 0.7v so the voltage across R3 is VBE(Q3) hence the current through R3 is IR3 = VBE(Q3)/R3 = 0.7v/1k☐ = 0.7mA
IB3 = IE2–IR3= 3.25mA – 0.7mA = 2.55mA.

The gain ( ☐) of the transistor Q3 should be such that with this base current (2.55mA) and the maximum load current (IL) flowing into the collector of Q3, the condition IL<☐IB3 is satisfied otherwise this transistor Q3 will come out from the saturation. If Q3 is in saturation the voltage at its collector C3 is Vc3= VcE(sat) Q3 ☐ 0.3v.

The two saturated transistors Q3, Q2 and the presence of the Si-diode D keeps the pull up transistor Q4 of the totem pole output stage in cut-off condition because the base emitter voltage of Q4 in presence of diode D is VBE(Q4) = Vc2– Vc3– VD where VD is the diode drop voltage.
= 1v – 0.3v – 0.7v = 0v Without this diode the voltage across the base
emitter junction of Q4 would be VBE(Q4)= Vc2 – Vc3=

1v – 0.3v = 0.7v and this could cause the transistor

Q4 to conduct. So, the use of this diode ensures

that Q4 will remain in cut-off when Q3 is in

saturation for all Vin inputs HIGH.

It has already been stated that if the load current

(this is the sink current of the transistor Q3)

increases to a value such that the relation IL <<

☐ IB3is not satisfied the Q3 will cone out of

saturation gradually with the increase of IL. Each

TTL gate has a maximum specified sink current
that must not be exceeded if the voltage of the logic low output is to stay below the upper limit of the logicLOW threshold. The variation of Vout with load current IL when Q3 is in saturation is shown in Fig 7.6.

Case II : When at least one input is Low

Fig.7.7 shows the same circuit

as was shown in Fig.7.5. In this

figure one input is at low voltage

of the order of 0.2v. For the

multiemitter type transistor (Q1) if

one emitter input Vinis low (☐ 0.2v)

then the base of this transistor is

clamped to a voltage.

VB1= Vin + 0.7v. irrespective of

other inputs. In this particular case

Vin = 0.2v, VB1= 0.2v + 0.7v = 0.9v
.The current entering into the base of Q1 from Vccthrough R1 is IB1= Vcc -VB1 =5v -0.9V = 1mA.R1 4k☐

From the base of Q1 to the ground point (emitter of Q3) the three junctions– (i) basecollector of Q1 (ii) baseemitter of Q2 and (iii) baseemitter of Q3 fall in series which can’t be forwaded biased by the voltage VB1= 0.9v because they need atleast a 2.0 volt (= VBC(Q1) +VBE(Q2) + VBE(Qs) = 0.6v + 0.7v + 0.7v = 2.0v) at B1 with respect to ground. So, all the three junctions remain in the reversed biased condition for which the transistor Q1 enters in the active region and the remaining two junctions are in the cut-off conditions. The

transistor Q1 draws the stored base charge of Q2 as its collector current to maintain the relation Ic1= ☐IB1so that it may remain in the active region. Once the stored base charge current IB2from the base Q2 and hence the collector current Ic1of Q1decreases and the relation Ic1< ☐IB1will be quickly satisfied for Q1. This is a condition of saturation of Q1. For this reason Q1 enters into saturation and the collector voltage of Q1 becomes Vc1= Vin + VCE(sat)Q1= 0.2v + 0.3v = 0.5v. Therefore, VB2= VC1= 0.5v which again can’t forward bias the two baseemitter junctions of Q2 and Q3 which are in series between B2 and ground entirely (neglecting any leakage current of Q2) into the base of Q4. The collector current from the emitter of Q4 as shown in Fig.7.7. Depending on IL the transistor Q4 may be either of magnitudes of load current IL can be obtained as follows : Vout = Vcc – VCE(Q4)– VD where
VBE(Q4)☐ 0.6v and VD☐ 0.7v. Therefore, Vout = 5v – 0.6v –0.7v = 3.7v for Vcc = 5v.

(ii) If IL is increased, Q4 and D conduct more heavily, but for a range of IL, Q4 remains in the active region and
Vout= Vcc– R2Ic2 – VBE(Q4) – VD
= V
cc – R2 ☐ ☐
☐ IL ☐ –VBE(Q4)– VD;☐ is the gain of Q4➔1☐ ☐☐
☐ VR2IL –VBE(Q4) – VD ; ☐ >>1 ... ...(7.6)cc – ☐

(iii) If the load current is increased further the Q4 goes into saturation and the drop across collector and emitter of Q4 becomes VCE(sat). On the verge of saturation we may write VCE(Q4) = VCE(sat)Q4 and IC4 = ☐IB4.

VCE(sat)Q4 = (VCC – IC4R4) – (Vout + VD)
=
☐VCC - IL☐R4 ☐
☐ – (VCC – IC2R2–VBE(Q4)–VD + VD)➔ 1☐ ☐ ☐
☐
=
☐ ☐
-
☐ VCC- IL☐R 4 ☐ ☐ VCC- ILR 2 - VBE(Q4 )☐ ➔
1
☐ ☐
☐ ☐
☐ ➔ 1 ☐ ☐ ☐
V V
or, I
VBE(Q4 )- VCE(sat)O4 ☐ BE(Q4)- VCE(sat)Q4 ☐ BE(Q4)- VCE(sat)Q4 for☐>>1 ...(7.7)L = ☐ ☐R 4 - R 2 ☐ R 4 R4☐ 1 ☐ ☐ 1 ☐ ☐ ☐
➔ ☐
The above expression for Vout indicates that the resistor R4 is used to limit the load current when Q4 saturates.

Switching Noise : A totem pole circuit is inherently noisy. This will be cleasrly understood from the following discussions. When the output changes from LOW to HIGH state, the transistor Q3 should change state from saturation to cut-off. On the other hand the transistor

Q4 should change state from cut-off to saturation respectively. Ideally, these two changes should be expected to occur simultaneously. But Q3 takes longer time to come out of the saturated state due to the effect of storage time than

Q4 to enter into the saturation from cut-off. So, there

is a momentary overlap of the LOW state of Q3 and

Q4 before their transitions are complete as shown in

Fig 7.8 (a) and (b). Owing to the overlap of the low

state of Q3 and Q4 for a short duration the power

supply Vcc momentarily finds a very low resistance

path through these two ON transistors to ground

and a surge of current Icc flows momentarily from

the power supply as shown in Fig 7.8(c) where ICCL

and ICCH are the steady power supply current when

the output Vout is LOW and HIGH respectively. The

current spike causes a sudden rise and fall of the power

supply voltage from normal value of VCC = +5V due to

the inductive effect of the power supply line. This

sudden change of the voltage and current may

seriously damage the ICs used in the power supply

unit.

Another cause of flow of heavy current through

the pull-up transistor Q4 of the totem pole output stage

is the presence of the stray capacitance or the capacitive

load at the output terminal. Even if Q3 goes from LOW

to HIGH the output voltage i.e. the collector voltage

of Q3 will be held at VCE(sat) for a short-time before it changes to HIGH level due to the infinite time of charging the stray or load capacitor. As soon as Q3 just enters the cut-off, the base voltage of Q4 becomes VB4= VBE(sat)Q4 + 0.7v + 0.3v = 1.7v Collector voltage of Q2 = VB4= 1.7v
V
cc
-
Base current of QVc2 =5v -1.7 v = 2.06mA4 = IB4= IC2= R2 1.6k☐
- VCE(sat)Q4 -VD -Vout(C)and collector current of Q4 = IC4= Vcc
130☐
= 5v - 0.3V - 0.7 v - 0.3v☐ 28.5mA130☐
This large collector current IC4will flow through the saturated transistor Q4. To keep Q4 in saturation with this collector and base circuit the condition Ic4<☐Q4IB4should be satisfied.
This means☐ >
Ic4 ☐ 13.9. If this condition is not satisfied then Q4 will come out of saturationIB4momentarily.
Modified Totem Pole Output Stage Modified totem pole output stage
is shown in Fig.7.9 where the

pull-up transistor (Q4) of a

standard TTL gate discussed so

far is replaced by a Darlington

pair using two transistors Q

4

and Q5. The Darlington pair

provides much greater current

gain when the output is at logic

High state. Darlington

connection reduces the output

impedence so the switching time

is improved. The baseemitter

junction of Q5 fulfils the

requirement of the diode D of the
Fig 7.9

totem pole output. The emitter
resistor R5 of Q5 is included to increase the current in Q5 while it conducts. When both Q4 and Q5 start conducting then the emitter current of Q5 becomes : I
E(Q5)
=
E
V (Q )
4
[V
= out(Q4 )- VCE(Q5)- VBE(Q5)] 3.8= 0.95 mAR5 R =
5 4k☐
where Vout is VCC minus the sum of baseemitter drops of Q4 and Q5 = 0.6V. In absence of R5 the emitter current of Q5 is
ILIE(Q5)= 1☐ ☐Q4
If IL = 100 ☐A and☐Q4 = 50
then IE(Q5) = 1.96 ☐ A
This current IE(Q5) in absence of R5 is at very low level and the recombination in the base of Q4 dominates.
7.3 ELECTRICAL CHARACTERISTICS OF LOGIC GATES

The electrical characteristics of logic gates provides us the information regarding the input/ output voltage and current levels, current-driving capability, switching speed, noise immunity, power dissipation and speed-power product etc. In this section we shall see the electrical properties of the different subfamilies of TTL. Later on in this chapter discussions will be made for the same electrical properties for the MOS families and will be compared with those of TTL family. The knowledge of these electrical properties are necessary to have

an idea of the power consumption, speed and noise sustaining capacity of a complex digital circuit designed with logic gates. Also, the information regarding the voltage/current levels and current driving capability of the logic gates are important when the circuit designer interfaces the logic gates of two different logic families like TTL family followed by MOS family or the reverse. Following are the discussions of different input/output features of the TTL logic gates.

7.3.1 Propagation Delay

The output of a logic gate or logic module cannot respond to the change in their inputs instantenously. There is a short delay of the order of several nanoseconds, between an input change and its output response. This delay is called “Propagation Delay”. This delay is due to the finite charging and discharging time of the switching transistors used for fabricating the logic gates. It is already known to us from the previous discussions that the turn-ON and turn-OFF time of the transistors internal to the gates are finite, the magnitude of which depends on the type of the transistors. Also, the turn-ON and turn-OFF times are not identical so the propagation delay when the gate-output changes from HIGH to LOW(tPHL) and the propagation delay when the gate-output changes from LOW to HIGH (tPLH) are not the same.

Two types of delays (tPHL and tPLH) are illustrated in Fig.7.10 using two gates. The changes in logicstate changes of the input and output waveform are shown with exaggerated slope. This is done to indicate vividity that the rise and fall time of the waveform are finite due to the capacitive effect of the internet components of the circuit of the gate. The time delays are Fig 7.10

measured between input and output voltages passing through standard reference voltage levels. In the Fig.7.10 these reference points have been indicated by V1 and V2. These reference voltages are as follows : For LSTTL : Time from 1.3V at input to 1.3V at output.

Other TTL : Time from 1.5V at input to 1.5V at output.
CMOS : Time from 50% of maximum input to 50% of maximum output.

Typical values of these parameters for a few gates of standard TTL family are shown in TABLE 7.1. This table shows the maximum and typical values of tPHL and tPLH. The manufacture guarantees that the switching times of the output for the logic gate will not exceed the quoted maximum value. The typical value of the propagation delays indicate the values that gates can often achieve. While designing the complex logic circuits for high frequency, the circuit designer should start with the worst case values of the propagation delays i.e. the maximum values of these switching parameters.

Propagation Delay 7400 7402 7408 7432 tPHL(Typical) 7ns 8ns 12ns 14ns tPHL(Maximum) 15ns 15ns 19ns 22ns tPLH(Typical) 11ns 12ns 17.5ns 10ns tPLH(Maximum) 22ns 22ns 27ns 15ns Table 7.1 : Typical and maximum values of the propagation delays of a few standard TTL gates The propagation delay of a logic gate having the same part number but belonging to different subfamilies of TTL logic family varies. The values depend on the technology used for the fabrication of the gate. For example the TABLE -7.2 shows how the propagation delays of 2-input NAND gate varies when we consider this gate of standard, S,LS,AS and ALS type.

Propagation Delay Delay of 2-input NAND gate
tPHL(Typ)
tPHL(Max)
tPHL(Typ)
tPLH(Max)
TTL Subfamily Standard 74S 74LS 74AS 74ALS 7ns 3ns 10ns 1.5ns 4.0ns 15ns 5ns 15ns 4.0ns 8.0ns 11ns 3ns 9ns 1.5ns 4.5ns 22ns 4.5ns 15ns 4.5ns 11.0ns Table 7.2 : Typical and maximum values of the propagation delays(nano seconds) 2-input NAND gate belonging to different TTL subfamilies
7.3.2 Input/Output Current and Voltage Parameters It is a common observation by the users of the ICs that there is no fixed voltage and current for logic-1 and logic-0 level, both for the input and output of an IC instead a finite range of voltage and current exist for both the logic levels. The manufacturer of the IC chips specifies the guaranteed upper and lower limit of this acceptable range but they do not give any gurantee for the normal operation of the ICs if the input/output voltage and current falls outside their current levels both for input and output of a logic gate. Fig.7.11(a) and (b) show the acceptable voltage range for logic-0 and logic-1 both for input and output of any logic gate.

Fig 7.11(a)
Fig 7.11(b)
7.3.3 Power Dissipation Each gate in a logic circuit consumes a finite amount of energy from the power supply. The measure of the energy over a time is called “Power Dissipation”. The manufacterers of the TTL family specify two currents –ICCH and ICCL. These two currents are defined as follows : ICCH = current drawn from the power supply by the circuit of logic gates of an IC when the outputs of all gates of the IC are LOW.
Fig 7.12(a) and (b) show an IC 7402 (Quad 2-input NOR gate) drawing currents ICCH and ICCL. If the gate outputs are not all at the same logic level, then the supply current drawn by the IC package is the sum of currents which can be written as by Icc=NH ICCH +N

N L ICCL, where N is the total number of gates in the IC package, NH is the number of gatesN
whose outputs are HIGH, NL is the number of gates whose outputs are LOW and N = NH + NL.

Fig 7.12(a) :
Fig.7.12(a) Supply current ICCH when all outputs are HIGH (b) Supply Current ICCL when all outputs are low.
For TTL ICs the power dissipation depends on the duty cycle of the gate outputs. That is, it depends on the fraction of the time that the IC’s outputs are HIGH. For 50% duty cycle NH =NL = 1 . So the supply current for this particular condition is Icc = (ICC+ICL)/2. But forN N 2
a duty cycle other than 50% the supply current Icc drawn from the power supply can be calculated as follows
Icc = DICCH + (1–D)ICCL where D is the duty cycle. The power dissipation for the IC is PD = Icc Vcc. 7.3.4 Fan-out The term Fan-out is the maximum number (N) of inputs of load gates that can be connected to the output terminal of a driver logic gate preventing the voltage level of output of the driver gate to go below the guaranteed specified value
VOH(min) and to go above VOL(max) due to the loading

effect of the N number gate inputs. The output or

the input current of any logic gate changes, with logic

state so the following two cases will arise while we

calculate the Fan-out.

(i) Fan-out when the driver gate output is HIGH

(ii) Fan-out when the driver gate output is LOW

Fan-out in the High State : This situation is

explained in Fig.7.13(a). IOH(max) is the maximum

source current available from the driver gate in its

high state. This current is shared by the NH number

of inputs of different types of load gates. Each input

of the load gate connected to the output of the driver

in High state and in worst case each input may draw

maximum amount of input current (Sink

current)IIH(max). So, for NH number of load inputs

we may write :Fig 7.13

IO(max) = NHIIH(max)
or, Fan-out in High state = N
-IOH(max).H = IIH(max) In this calculation the magnitude of the ratio is to be considered, otherwise NH will be negative number. This happens because according to the sign convention of the current flow the sign of the source and sink current are negative and positive respectively.

How many 74LS00 NAND gate inputs can be connected to the output of 7400 when the output of one gate of 7400 is in the HIGH state.
IOH(max) for 7400 is –400☐A and IIH(max) of 74LS00 is 20 ☐A. So, the Fan-out of 7400 in its HIGH state is
NH= -400 ☐A/20☐A = 20
7.3.5 Fan-In Fan-in of a logic gate means the number of possible inputs to a gate. Following figure (Fig.7.14) shows the Fan-in of different NAND gates. The family numbers of the TTL family are also mentioned besides each gate symbol.

Fig 7.14 :
Show, how can the fan-in of the following logic gates be reduced. (a) AND and NAND gate. (b) OR and NOR gate.
The scheme for reducing the fan-in is shown in Fig.7.15.
Fig 7.15
7.4 OPEN COLLECTOR TYPE LOGIC GATES

We have so far seen the logic gates with totem pole outputs. The logic gates with totem pole output has a serious drawback that the output of two or more gates can’t be tied together to

have a common output. The cause behind this can be explained using the Fig.7.16.This figure shows the effects of short circuiting the totem pole outputs YA and YB of two gates when the outputs are in opposite states. The common output is Y when YAand YB are tied together.

In Fig.7.16(a) the output YA is in HIGH therefore, Q4A is ON and Q3A is OFF and on the otherhand the output YB is in Low state so Q4B is OFF and Q3B is ON. For this reason Q3B offers a low resistance load (☐ 10W to 20W) to Q4A and allows a large amount of current to ground from VCC. This current flows through 130☐, Q4A, the diode DA and Q3B. The direction of current flow is shown with a dotted line. If this flow of current is allowed for a long time then the two ON transistors will be overheated and will be damaged. The probability of damage of the transistor Q4A is higher compared to Q3B. Even if, by chance, these two transistors are not damaged the output YB will be higher than the specified value of VOL(max) of Gate-B due to this excessive flow of current through Q3B and the common output Y will follow this output of YB which is neither in perfect low state nor in the perfect high state.

Similar situation arises if the output YA of Gate A is in low state and the output YB of GateB is in HIGH state. In this case the transistors Q3A and Q4B are ON and large amount of current is drawn from VCC to ground following the dotted path shoen in Fig.7.16(b). This flow of current will cause overheating and ultimately damage the two transistors Q4B and Q3A.

Thus, the tied together outputs of two TTL gates with totem pole outputs will cause a serious problem if the outputs are in opposite states. From this figure it is also clear that if the two outputs are in the same state (i.e. both of them are either LOW or HIGH) then there will be no problem. For example, if the outputs YA and YB are LOW then the two transistors Q3A and Q3B will share the sink current equally and if the outputs YA and YB are HIGH then the two transistors Q4A and Q4B will share the source current.

Fig 7.16

To overcome the above problem of tied together

outputs of TTL gates the totem pole output circuit is

modified by removing the upper transistor (Q4), the

diode(D) and the 13☐
resistor. This type of the output

circuit of a TTL gate is called Open-Collector Type.

This is so called because the collector of the lower

transistor (Q3) of the totem pole circuit is open in this

circuit configuration. The internal circuit of an open

collector type TTL-2input NAND gate is shown in

Fig.7.17. The output of this gate is taken from the open

collector point of Q3. The transistor Q3 is saturated

for inputs A = B = HIGH and the output Y becomesFig 7.17

VCE(Sat) of Q3. The transistor Q3 is cut-off if any one of

the two inputs A and B or both are low. For this situation the output Y floats and the output can neither source nor sink any current.

To identify an open collector gate an underlined diamond symbol is used near the output of the logic symbol of the open collector type gate. Following are some examples of the logic symbols shown in Fig.7.18.

Fig 7.18
External Pull-UP Resistor (Rext) for the Open Collector Output We have noted in the Fig.7.17 that when outout transistor Q3 is cut-off then the output terminal Y floats, we can’t get the logic-1 output voltage at Y and the circuit can’t source any current to any load gate connected to the output Y. To overcome this situation an external resistor (Rext) has to be connected between the open collector Y of Q3 and the power supply Vcc. This is shown in Fig. 7.19.

If the external resistor Rext is connected in this way then a current☐IIH will flow to the N number of inputs of the load gates connected to the output Y of the open collector NAND gate and leakage current IOHwill flow towards cut-off transistor Q3 when either of the two inputs A and B or both are low. These two currents flows through Rext from VCC. The order of magnitude of IOH is 250☐A. The sum of these two currents will cause a voltage drop across Rext and recommended value of VOH(min). Otherwise, the inputs of the TTL load gates connected to Y will not recognise this voltage at Y as logic high. So, the following condition should be satisfied when the collector output is at logic high.

Vcc – Rext (IOH+ ☐IIH)☐ VOH(min)N

On the otherhand when Q3 is saturated (when A = B = 1) then the output voltage V0 will be VOL = VCE(sat)Q3 and the current through Q3 will be IOL. This IOL has two components (i) IL = (Vcc – VOL) /Rext (ii) ☐IILfrom N inputs of load gates. These currents are shown with N

dotted line in Fig.7.25. But the current IOL through Q3 should not exceed the maximum sink current IOL(max). So, the following condition has to be satisfied when the open collector output ia st low state VCC- VOL(max)+ ☐IIL ☐ IOL(max)R ext N
7.5 TRISTATE LOGIC GATES (TSL GATES) The third category of logic gates which belong to the TTL family are Tristate gates (TSL gates). This name implies that these type of gates have three states and the states are (i) LogicHIGH (ii) LogicLOW and (iii) High impedence state (Hi-Z). The Hi-Z state makes these gates different from the gates with totem-pole and the open collector type output. On the other hand the outputs of open collector type gates can be connected together to get the wireANDed function which is not possible with the totem-pole outputs. The tristate gates combine all the advantages of the totem-pole and open collector outputs. Therefore, tristate logic gates have active pull-up, lower output impedance, faster switching time and also the outputs can be tied together. In reality, the output terminal is not an exact open circuit in the Hi-Z state but has output impedence of several megohms relative to ground and Vcc. The high impedence state at output is obtained when both the transistors of the totem pole output are turned off with the help of some external control circuit. Following two circuits will explain how the three states can be achieved in tristate gates. Circuit in Fig. 7.20(a) is a simple tristate inverter, and the corresponding logic symbol is in Fig. 7.20 (b).

C

G A Q1 Q2 C D2 Q3 Q4 Y LOW ☐ ON OFF HIGH ON OFF OFF Hi-Z HIGH LOW ON OFF HIGH OFF ON OFF HIGH HIGH HIGH OFF ON LOW OFF OFF ON LOW

Table 7.3 : State table of the circuit shown in Fig.7.20(a)
Without the diode D2 and the second emitter (G input) of the transistor Q1 the circuit is exactly similar to the circuit of an inverter with totem pole output. This additional part of the circuit gives us the high impedence state. When the input to G is low then Q1 is saturated irrespective of the input to A, Q2 is turned off, the collector C of Q2 becomes high, Q4 is turned off and the diode D2 is forward biased. This forward biased diode D2 pulls the collector point C to a low voltage of the diode drop and bypasses the base current of Q3. So, Q3 will not be able to be turned ON. Thus, for the input G = 0, both the transistors Q3 and Q4 of the totem pole output are turned OFF and gives high impedence at the output Y relative to ground (as Q4 is off) and to Vcc (as Q3 is off). Different logic levels of this circuit are given in the TABLE 7.3. If the input G is held high then diode D2 is always reverse biased for logic low or high input to A. Under this condition the circuit acts as a normal TTL inverter with output Y = A–. The bottom two rows of the TABLE 7.3 give the states of the transistors of this circuit for logic high input to G. This control input G which controls the performance of the circuit is also called Enable Input. For this circuit in particular this enable input G is called Active High Enable Input because when G is high the circuit behaves as a normal inverter but when G is low the normal function of this circuit is disabled because the output Y can’t respond to the input A to give Y = A–. Logic symbol of a tristate inverter with active high enable input is shown in Fig.7.20(b). Note the triangular shape symbol pointing downward near the output. This symbol is used to indicate that the output has three states.

7.6 MOS LOGIC FAMILY

So far we have studied the logic gates which were all members of TTL family. But for large integration of the components the MOS logic family is very popular. A MOS circuit occupies typically one third or even less than the area of BJT. Most of the IC chips which have large number of components like memories, microprocessors and its support chips are fabricated using MOS technology. The logic circuits are based on the switching of Metal-Oxide Semiconductor Field Effect Transistor (MOSFET). The MOS family does not only saves space but it also saves power and reduces the production cost. Under dynamic condition the MOS devices dissipate less amount of power and almost negligible amount under static condition. Because of these reasons MOS LSI and VLSI circuits can be operated from battery and this leads to manufacture portable instruments.

A major drawback of MOS circuits is their relatively low speed of operation. But with the gradual improvement of the fabrication technology and the reduction in the chip dimension, the speed of the MOS circuit is increasing towards that of the TTL circuit. Another problem of the MOS circuit is low current drive capability. When the outputs of

the MOS circuit is used to drive high-current load then the performance is degraded. Some devices have been manufactured to drive highpower loads sacrificing its speed.

MOS uses Gallium Arsenides (GaAs) technology instead of Silicon technology, which helps to increases the speed of operation because of higher mobility of electrons. Depending on the type of carriers causing the currents to flow in the MOS transistors we can classify these transistors into following two types.
(i) PMOS and (ii) NMOS

Both of them are unipolar carrier devices. In PMOS and NMOS the carriers are holes and electrons respectively. These carriers are restricted to flow within a narrow path called channel from one end called “Source” to other end called “Drain”. Therefore, the PMOS and NMOS transistors are also called P-channel and Nchannel respectively. Depending on the ways the flow of carriers are controlled in the channel of MOS transsitor we can catagorise these transistors again into following two types.

(i) Enhancement MOSFET (E-MOSFET) and (ii) Depletion MOSFET(D-MOSFET).

We will concentrate on the enhancement MOSFET devices, as they are mainly used to manufacture the digital circuits. Details of physics of the enhancement and the depletion transistors can be found in any good textbook on electronic devices and will not be discussed in this text.

Another class of logic circuits are constructed combining both Nchannel and P-channel MOSFET. This class of circuit is called CMOS circuit. CMOS (complementary MOS) refers to the complementary operation of N and P channel transistors.

7.6.1 Structure and Operation MOSFET
The simplified structure and symbol of the widely used enhancement NMOS (E-NMOS) is shown in Fig.7.21(a) and (b) respectively. Fig. 7.21(a) shows that the device is built on a p
Fig 7.21(a)

type semiconducting substrate with two heavily doped n-type wells at a distance L apart. These two wells are called source and drain respectively. The “source” and the “drain” are roughly equivalent to emitter and collector of a bipolar NPN transistor. The subtrate is shown as a terminal with an arrow in the device symbol in Fig.7.21(b) and (c). The direction of this arrow points inwards for an Nchannel device. But for a P-channel device the arrow points outwards. For most of the cases the substrate (B) is connected to the source (S) or to the most negative potential in the circuit. In circuit symbol in Fig.7.21(d) shows the simplified version of the symbol of a NMOS transistor. The arrow at source terminal in this figure indicates the direction of positive flow of current.

In enhancement NMOS mode a feable current flows towards the drain along the channel when the gate terminal (G) is left open and a positive bias is applied to the
Fig 7.22(a)
Fig 7.22(b)

drain with respect to the source. An electric field is created between the gate (G) and the substrate (B) when a positive voltage is applied to the gate terminal with respect to the substrate. This electric field increases with a positive gate bias and the electrons starts accumulating below the SiO2 layer when the gate voltage exceeds some threshold voltage VT. These accumulated electrons form a conducting layer and the flow of electrons towards the drain starts when the drain is made positive with respect to the source. IF we go on increasing the positive gate voltage keeping the drain voltage fixed then the channel resistance RDS falls to a low value due to the heavy accumulation of electrons in the channel. The above a certain voltage called threshold voltage mode of operation of ENMOSFET changes. The increase of gate voltage above the threshold voltage (VT) causes an increase in the drain current for a drain voltage less than the threshold voltage (VT) is called Cut-off mode. The equivalent circuits for the two cases are shown in Fig.7.22(a) and (b). The Fig. 7.22(a) and (b) show that for a bias voltage to the gate VGS<VT. Thus, the ohmic and the cut-off regions are analogous to the saturation and cut-off of the bipolar NPN transistor. So, the E-NMOS can be used as the positive logic inverter as we did with NPN transistor.

Fig 7.23(a)

For negative logic design the P-channel MOS are used ususally. The structure of the E-PMOS and its circuit symbol are shown in Fig.7.23(a), (b), (c) and (d). The symbol in Fig.7.23(d) is simple in nature. The arrow at source indicates the positive flow of current.

7.7 NMOS INVERTER

The underlying principle of an NMOS in a circuit used as an inverter is identical to that of a bipolar transistor because the MOS device can be used either in cut-off or in ohmic region by changing the gate voltage with respect to the source. The ideal situations of the NMOS inverter actions are shown in Fig.7.24(a), (b) and (c) with a fixed load current resistor R connected between the drain (D) and the power supply VDD. No external resistor is used at the gate because the input impedance of the gate is very high. In reality, the use of the passive load resistor R to drain of the MOS transistor is avoided while fabricating the ICs because the diffused resistor occupies areas on the silicon chip which are proportional to the value of resistor. The MOSFET load canbe fabricated in integrated circuits which occupies much smaller area. The reduction in the area of the fabrication reduces the distributed stray capacitance. Fig.7.25 shows the inverter circuit replacing the load resistor by an NMOS enhancement type MOS transistor Q2. The gate G2 of this transistor Q2 is connected to the drain D2 of Q2. Thus, the condition VGS = VDS is always satisfied and hence the condition of saturation VDS ☐ VGS – VT. This saturation gives a fairly constant current, increase very slightly with increasing VDS. The DC circuit operation is explained as follows : Fig 7.24(a)

(a) when Vin = VLow , (VLow< VTQ1) the
driver MOS is off, I☐0 and Vout = VHigh =

VDD – VTQ2. The output Voutcan’t reach VDD.

This is the limitation of the enhancement

type active load.

(b) When Vin = VHigh , (VHigh > VTQ1), the

driver operates in the nonsaturation region,

the load in saturation and therefore V

out
drops to a very low value.

Another popular type of NMOS inverter

circuit makes use of a depletion mode MOS

transistor (D-MOSFET) as the load device. For

depletion load VT< 0. Fig.7.26 shows that V

GS

= 0 for the load transistor Q2 as the gate G2 of

load transistor Q2 is connected to its source

S2. The substrate B2 of the load is again
Fig 7.25

electrically connected to the ground potential.

Note the absence of the broken line between
drain and source for this depletion MOS
transistor.

For Vin ☐ VTQ1 the enhancement driver

transistor Q1 is cut-off, and no drain current

exists. So, for the depletion load transistor the

drain-to-source voltage will be zero to give zero

drain current. Hence, for Vin☐ VTQ1, Vout = VDD.

This makes the difference between the inverter

with enhancement saturated loas and depletion

load. There is no threshold voltage drop from VDD

for logic high logic high output. For logic low

input Vin may be 0V for the depletion load.

It is also claimed that the depletion MOSFETS

have better transient characteristic than

enhancement devices. Further, enhancement/

depletion combination tend themselves to efficientFig 7.26

use of chip area are therefore favoured for largescale integration.

7.8 LOGIC GATES USING N-CHANNEL MOSFET (NMOS)
NAND Gate : The circuit for a 2-input NAND gate using NMOS transistors is shown in Fig.7.27(a). In this circuit two enhancement NMOS transistors Q2 and Q1 are connected in

Inputs Output

A B Y

<VT <VT High

<VT >VT High

>VT <VT High

>VT >VT Low

Table 7.4 : Truth table

of the 2-input NMOS

NAND gate circuit.

Fig 7.27(b)Fig 7.27(a)

series and their gates are driven by the external inputs A and B respectively. The load gate QL is also an NMOS transistor hardwired in saturation mode. When the inputs A or B or both

are less than the threshold voltage VTN of the transistors then one of the two transistors or both will be at cut-off state and hence the output Y will be near to VDD leading to a logic high voltage. But when both the inputs A and B are driven by a voltage greater than VTN then both the driver transistors Q2 and Q1 will be ON. The ON resistance of the transistors

Inputs Output

A B Y

<VT <VT High

<VT >VT Low

>VT <VT Low

>VT >VT Low

TABLE 7.5 : Truth table of the 2-input NMOS Fig 7.27(c) :Fig 7.27(d) : NOR gate circuit. NMOS circuit of a 2-input NOR gate Equivalent circuit of a two input NOR gate will be low and hence the output Y will be pulled down near to the ground. This gives us a logic low output at Y. The mechanical switch equivalent circuit of the 2-input NMOS N AND gate is shown in Fig.7.27(b). The truth table TABLE 7.14 describes the function of a 2-input NAND gate. Multiple input NAND gate can be obtained by connecting more driver NMOS transistors in series.

NOR Gate : The circuit for a 2-input NOR gate is shown in Fig.7.27(c). This current uses NMOS transistors Q1 and Q2 in parallel and this parallel combination is in series with a common load transistor Q1. All the transistors in the circuit are enhancement NMOS type. If either of the two inputs or both inputs are high (VA or VB>VTN), the corresponding transistor conducts and pulls the output Y to nearly ground level. The output Y jumps near to voltage level of VDD only when both the inputs A and B are in the low level (VA, VB<VTN) which cut off Q1 and Q2 simultaneously. The mechanical switch equivalent circuit of this 2-input NOR gate is shown in Fig.7.27(d). The function table of this circuit is given TABLE 7.5.

The circuit of Fig.7.28 represents a logic gate. Determine what type it is. Each rectangular box represents an enhancement NMOS transistor where the terminals G,S and D indicate Gate, Source and Drain respectively.

Fig 7.28
This circuit is a combination of NAND gate with output Y1 followed by an
–
Inverter with output Y2. The output Y1 = AB = Y2= Y1=AB. So, this circuit is equivalent to a 2-input AND gate.
This circuit in Fig.7.29 represents a logic circuit. Determine the output at Y. This circuit has a depletion load and enhancement drivers. The output is
Y = (B+C)·A = B + C + A
Fig 7.30Fig 7.29 :
Draw the NMOS logic circuit for an EX-OR gate
Y = AB + AB = (AB)☐(AB) .
The logic circuit for the Ex-OR gate using NMOS transistors is shown in Fig.7.30.
7.10 COMPLEMENTARY MOS LOGIC

The complementary MOS logic is caled in short CMOS logic. In this logic family both Nchannel and P-channel MOS transistors are used and they are connected as shown in Fig.7.31(a). This basic current forms an inverter. In general the CMOS circuit looks complex compared to the circuit designed only with NMOS or PMOS transistors still the CMOS circuits have become popular due to the following reasons.

(i) The CMOS circuit draws negligible current either in low or in High output state. (ii) The CMOS circuit allows the full power supply voltage VDD to be available at the output in logic high state.

(iii) The power supply voltage (VDD) can be changed to any value between 3V and 15V without changing the logic operation of the circuit. The higher power supply voltage provides larger noise margin and faster switching time while the lower power supply voltage results in lower dissipation during the transition of logic states.

(iv) High fan-out.
(v) The output impedance of CMOS in both the states is same and lies between 100☐ to 400☐. The source and sink current of the CMOS device are same.
In the circuit of the CMOS inverter shown in Fig.7.31, the PMOS transistor Q1 acts as a variable load to the NMOS driver transistor Q2. The input voltage Vin is common to the
Fig 7.31
gate inputs of both transistors, the output and Vout is taken from a point where the drains of Q1 and Q2 are connected together. The source of Q1 is connected to VDD and the source of
Fig 7.32
Fig 7.33

Q2 is connected to ground. To understand the operation of this current we assume that the threshold voltages to be VTP and VTN for the PMOS and NMOS transistors. So, for Vin = 0V (or < VTN), Q2 is OFF while Q1 is ON because VGS2 = 0V and VGS1 = –VDD more negative than VTP). So, the output Vout will be equal to VDD . The switch equivalent of the current is shown in Fig.7.32(a). When Vin increase to VDD or atleast to VDD – VTP then VGS2 becomes more positive than VTP, so Q1 is off. But, VGS1 = +VDD, so Q2 is ON. This is illustrated in Fig.7.32(b). The output voltage Vout is at 0V. The truth table of the circuit is shown in TABLE 7.6. and its voltage transfer characteristics is shown in Fig.7.33. It may be noted that the changeover from High to Low or from Low to High is very sharp and occurs nearly at Vin = 1 VDD.2
Vin Vout
OV VDD VDD OV
Table : 7.6 : Truth table of the CMOS inverter.

1. An XOR gate is used as a controlled inverter as shown in figure below. When the switch Sw is open Y= A and when it is close Y= A. The upper limit of the pull-up resistor R and the power dissipation when the switch is open and close are (a)☐75 k☐, 0.12 mW, 0.66 mW;; (b)☐75 k☐, 0.12 mW, 0.33 mW;; (c) > 75 k☐, 0.12 mW, 0.33 mW; (d) > 75 k☐, 0.12 mW, 0.66 mW.

2. Both transistors T1 and T2 have a threshold voltage of 1 volt. The device parameter k1 and k2 of T1 and T2 are respectively 36 ☐A/V2 and 9 ☐A/V2. The output voltage V0 is [GATE 2005]
(a) 1V; (b) 2V;
(c) 3V; (d) 4V

3. The specifications given for a TTL logic family gate are as follows: IOH= -400 mA, IOL = 8 mA, IIH = 20 mA, IIL = - 0.36 mA. Fan out is [DRDO 2009] (a) 10; (b) 18; (c) 20; (d) 22

4. The CTL, TTL, ECL, and CMOS families of digital ICs are compared in the following 4 columns.

(P) (Q) (R) (S) Fan out DTL DTL TTL CMOS Power consumption is minimum TTL CMOS ECL DTL Propagation delay is minimum CMOS ECL TTL TTL The correct column is (a) P; (b) Q; (c) R; (d) S
8.1 MULTIPLEXERS
8.1.1 Introduction Multiplexing means transmitting a large number of information units over a small number of channels or lines. The multiplexer is a combinational circuit which serves this purpose. A mutliplexer circuit, in general, may have M data inputs and one output line. The selection of input to output transfer path is controlled by set of N select lines. The select lines are also called the address of the inputs. The relationship between these N address lines and the M data input lines is M = 2N. Because, using N-bit binary inputs to the select lines we may
generate 2N address codes and

each code addresses one data

input line out of M. The

multiplexer in short is called

MUX. The MUX with M inputs

and 1 output is mentioned in

the literature as (M☐
1) or as M

0-1 MUX. For example, a MUX

with 4 data inputs and 1

output is called 4☐
1 or 4-to-1
MUX. Besides these inputs and
output, usually, for all kind
215

literature at least one input line is available which is known as Enable line. This enable line is either active low or active high type. If the enable input is kept inactive then the mutliplexer circuit becomes inactive. Commercially available MUX’s usually come with active low enable lines. This means that the mutliplexer circuit will be active i.e. will follow its functional behaviour if the enable line is made logic low otherwise there will be no variation at the output though the different inputs are selected using variation select codes applied to the select inputs. Under disabled condition the output will show either a logic-0 or logic-1 irrespective of the select inputs. Whether the state of the output will be logic-0 or 1 under disabled condition of the multiplexer depends on the internal circuit design of the multiplexer.

The block diagram for a 8-to-1 MUX is shown in Fig.8.1(a) and (b) are two alternative logic symbols that are used for the 8-to-1 MUX. In the logic symbol we can see that there are 8 data input lines (I0, I1, I2....I7), three select lines (S2, S1,S0), one activelow enable line (EN ) and one output line Y. Out of these 8 data inputs, any one input is selected at a time by the select code for receiving digital data and for transmission of the data from the selected input to the output Y. The selection of the particular input is done by setting the proper select codes to the select inputs S2, S1 and S0. For example if S2S1S0 = 010 then the I2 input will be selected for receiving digital data i.e. the binary bit 1 or 0 through the input I2 will be passed to the output Y and at this time all other input lines I0, I1 and I3 to I7 will remain deselected i.e. no digital signals will be able to pass through them to reach the output Y. That is, the selection of input is done one at a time. The function table (TABLE 8.1) explains the complete behaviour of a 8-to-1 MUX. For this illustration, the enable input (EN) is assumed to be activelow and under disable conditions (EN = 1) the output (Y) is assumed to be low.

From this function table we may write down the logic equation for the output Y in terms of the inputs (I0,I1....I7) and the select inputs (S2,S1
and S0) and the activelow enable input (EN). The logic

equation for the 8-to-1 MUX using the TABLE 8.1 is

– – – – –
Y = (S

– – – I0 + S2S1S0I1 + S2S1S0I2 + S2S1S0I3
2S1S0
+ S
– – – –
2S1S0I4 + S2S1S0I5 + S2S1S0I6 + S2S1S0I7) EN
☐7 ☐
☐
m Ii i☐ EN ...(8.1)
=☐
➔0 ☐
where mi represents ith minterm of select variable S2S
1

– – – = m0, S2S1S0 = m1, S2S1S0 = m2 etc.), Ii is
and S0 (e.g. S2S
– – – –
1S0

the ith data input line and EN is the acitve low enable input.

In general the logic equation for a MUX with n number of

select inputs and active low enable input may be written as

☐2n-1 ☐
Y = ☐ ☐m Ii i☐ ...(8.2)➔ 0 ☐

From the above discussions we may view one MUX as a rotary mechanical switch with select inputs determining the position of the switch arm to the appropriate input Ii. This is shown in Fig. 8.2.

8.1.2 Design of 4-to-1 Multiplexer

The Equation 8.2. is for 2n to 1 MUX and this equation represents a sum of product form. Therefore, Eqn. 8.2 can be realised using a 2-level AND-OR logic circuit. For 4-to-1 MUXthere

will be 4 data inputs, 1 output and optionally there may be one enable input. The enable input may be active low or active high type. Also, some MUXs give output polarity inverse of the selected input. Let us design a 4-to-1 MUX with active high enable (EN) input and one output (Y). The function table of such MUX is shown TABLE 8.2(a). Using this table, the logic equation for a 4-to-1 MUX can be written as – –
Y = (S1S0
– – I0 + S1S0I1 + S1S0I2 + S1S0I3) EN ... ...(8.3)

where S1 and S0 are the select inputs, I0, I1 and I2 are the 4

data inputs and EN is the active enable input. When this enable

input is made logic-1 then the output Y follows the first 4 rows

of the functional table of 4-to-1 MUX as shown in TABLE 8.2(a).

Otherwise for EN = 0 the output Y remains as logic-0 ignoring

of select and data inputs. The 2-level AND-OR logic circuit for

the Eqn(8.3) is shown in Fig 8.3(a) and the block diagram

representation is shown in Fig.8.3(b).

From this logic circuit it is seen that we need four 4-input

AND gates to generate the product terms of Eqn(8.3), two
inverters to get S– and S– from S1 and S0 respectively and one 4-input OR gate to get the1 0
final output (Y). In general, to design a MUX with n select lines and one enable line, we need 2n number of AND gates each with (n+2) inputs, n number of inverters and one OR gate with 2n number of inputs.

From the circuit of Fig. 8.3(a) we can easily understand how this MUX works. For S1= 0, S0 = 0 and EN =1 the outputs of all the AND gates of this MUX circuit are logic-0 except the output of AND gate-1. The output of the AND gate -1 is I0. Thus, the OR gate which

collects the outputs of all the AND gates gives an output Y = I0. Following the similar analysis it is easy to show that for S1S0 = 01 and EN = 1, the output Y is I1. This happens

because the AND gate -2 gives an output I1 with all other AND

gate outputs logic-0, for S1S0 = 10 and EN = 1, the output Y is I2

as the AND gate -3 gives an output I2 with all other ANDgate

outputs at logic-0, for S1S0 = 11 and EN = 1, the output Y is I3 as

the AND gate -4 gives an output I3 with all other AND gate

outputs at logic-0. But, for EN = 0 all the AND gates will give

logic-0 output irrespective of the different select inputs on S3, S2

and S0. This leads to the logic-0 output at Y for all times so long

as EN is low. This is indicated in the last row of the TABLE

8.2(a).

The logic circuit of a 4-to-1 MUX with active low enable input is shown in Fig.8.3(c) and its logic symbol is shown in Fig.8.3(d). The function table of the circuit in Fig.8.3(c) is shown in TABLE 8.2(b). The output Y of –
–
this MUX can be written from the TABLE 8.2(b) as Y = (I
– – + I1S1S0 + I2S1S0 + I3S1S0)EN.0S1S0
8.2 DECODER
8.2.1 Introduction A decoder is a combinational circuit with n-Bit input ans m number of mutually exclusive outputs. The mutually exclusive output means that the decoder circuit makes only one output active(active low or active high) among the m possible outputs and this output is unique and depends on the input code applied to the n-Bit input. We know that using nbits we can have maximum 2ncodes, so the maximum number of mutually exclusive outputs may be m = 2n. The function tables shown in TABLE 8.3(a) and TABLE 8.3(b) are the examples of a 2-input 4-output decoder circuit. In TABLE 8.3(a) one of four outputs (Y0,Y1,Y2 and Y3) is high for each 2-Bit input code; all the other outputs are low for each 2-Bit code input. But in TABLE 8.3(b) one of four outputs is low, all other three outputs are high for the same 2-Bit code input. These decoders having 2 inputs and 4 outputs are called 2-to-4

decoder. In general a decoder with n inputs and m outputs is called n-to-m decoder. The inputs B and A are also called the address inputs of the decoder.

The block diagram representation of 2-to-4 decoder with active high and active low outputs are shown in Fig.8.4(a) and Fig.8.4(b) respectively. Note the bubbles attached to each output in the Fig.8.4(b). This indicates that all the outputs are active low type. Also, it may be noted from the function tables that any active high or low output of this 2-to-4 decoder circuit corresponds to a 2-Bit minterm code of the input B and A.

For example,
If BA = 00 = 2-Bit minterms code of m0 at the input then only Y0= 1(for active high(output).
–
Y0 = 0(for active low output) BA = 01 =2 Bit minterm code of m1 at the input then only Y1 = 1(for active high output)
–
Y1 = 0 (for active low output) BA =10 = 2 Bit minterm code of m2 at the input then only Y2 = 1 (for active high output)
–
Y2 = 0 (for active low output) BA = 11 = 2 Bit minterm code of m3 at the input then only Y3 = 1 (for active high output)
–
Y3 = 0 (for active low output) Thus by looking at the logic state and the position of the outputs we may at once understand the presence of the minterm code at the input. Hence we may write the functional relationship of input and output as Yi = mi for a decoder with active high output,
––
and Yi = mi for a decoder with actie low output where mi = m(B,A).
As each output Yi of a decoder represents a minterm mi or the inverse of the minterm so the decoder circuit may be called a Minterm Generator or Minterm Indicator.

A decoder circuit with N inputs and 2N outputs is called Binary Decoder because these type of decoder generates all the minterms which are possible with the N bit binary inputs. The 2-to-4, 3-to-8 and 4-to-16 decoders are the examples of the binary decoders. But the decoders can be designed and are also commercially available for which the number of outputs are less than 2N with N-Bit code as the input. For these type of decoders the number of outputs depends on the number of possible valid minterm codes at the input. For example,

if BCD codes are used as the inputs then the maximum number of outputs will be tend to indicate ten valid input minterm codes of the BCD though the total number of possible input codes are 16 with 4 input bits. This 4-Bit input would generate 6 possible outputs if all the combinations of 4 Bits are considered. This particular decoder is called as 4-to-10 decoder or may be called BCD decoder or decimal Decoder. To a BCD decoder if non-BCD codes (1010 to 1111) are used as inputs then this BCD decoder will not respond to them. All the ten outputs for six non -BCD inputs will remain in the active state i.e. all ten outputs will remain in the low state i.e. all the ten outputs will remain in the low state for a decoder desgined for active high outputs and on the other hand all the ten outputs for six nonBCD codes will remain in the high state for a decoder designed for active low outputs.

Besides the N-Bit input, the commercial decoder IC chips are provided with one or more additional inputs called enable input. The enable inputs may be all active low or may be partly active low and partly active high. It may be mentioned here that these enable inputs help to cascade many decoders to increase the input and output capacity or to use a decoder as demultiplexer.

8.2.2 Decoder Design

(a) 2-to-4 Decoder : The function table of 2-to-4 decoder is shown in TABLE 8.3. Two tables show the logic state of the decoder outputs as a function of the two inputs B and A. Using these tables we may write down the logic equations for the outputs as follows : – – – –
(i) Y0 = B A , Y1 = B A, Y2 = BA and Y3 = BA; for a 2-to-4 decoder with active high outputs. This follows from the TABLE 8.3(a).
(ii) Y0 = B.A , Y1 = B.A , Y2 = B.A and Y3 = B.A ; for a 2-to-4 decoder with active low outputs. This follows from the TABLE 8.3(b).
If the enable input is included in the decoder circuit then the above equations are modified to
–– – –
(A) Y0 = BA·EN,Y1 = BA·EN, Y2 = BA · EN and Y3 = BA· EN for a 2-to-4 decoder with four active high outputs and active low enable input, EN.
– – – –
(B) Y0 = B.A·EN,Y1 = B.A·EN, Y2 = B.A·ENand Y3 = B.A·EN for a 2-to-4 decoder with four active high outputs and active low enable input,EN.

Using the above equations for the outputs we may easily draw the logic circuits for the decoders. These circuits are shown in Fig.8.5. In these two decoder circuits when the enable input is made low i.e. active then and only then the four outputs of the decoder circuits follow the function table (Table 8.3) otherwise for logic high input to the enable input all the outputs will go to inactive state (all the outputs will be low for a decoder having active high outputs, [Fig.8.5(a)], all the outputs will be high for a decoder having active low outputs, [Fig.8.5(b)].Two inverters in series for each decoder input B or A have been used to reduce loading to the external circuit driving the B and A inputs.

(b) 3-to-8 Decoder : The logic circuit for this decoder can be implemented using all discrete logic gates following the approach of the design of the 2-to-4 decoder. The function table of 3-to-8 decoder is shown in TABLE 8.4 with one active low enable input – – (EN), three active high address inputs (C,B,A) and eight active low outputs (Y0 through Y7). The block representation of the 3-to-8 decoder is shown in Fig.8.6.

From the function table we may write the following logic equations for eight active outputs. Y0 ☐ (CBA)·EN = m · EN0 Y4 ☐(CBA)·EN = m · EN4 Y1 ☐(CBA)·EN = m · EN1 Y5 ☐ (CBA)·EN = m · EN5 Y2 ☐(CBA)·EN = m · EN2 Y6 ☐ (CBA)·EN = m · EN6 3Y = (CBA)·EN = m · EN3 7Y = (CBA)·EN = m · EN7
where mi = m(C,B,A).The above equations can be summerised as follows: When the 3-bit code of the minterm mi is present at the input (C,B and A) and if the circuit is enabled (EN = 0) then we may write for the outputs as follows.
–
YK = 0 for K = i where i is the suffix of the input minterm code mi = 1 for K☐ i where i, K = 0,1 .....7
–
and YK is always 1(K = 0 to 7) for all possible 3-Bit minterm codes when the enable input is kept inactive i.e. the input EN in the above equation is not low.

The logic circuit based on the above logic equations is shown in Fig. 8.7. In this logic circuit six inverters (No.1 to 6) have been used instead of three to generate the true and– – –
complement form of the inputs address C,B and A (i.e. C,C,B,B,A and A) which are used as NAND gate inputs. This has been done to reduce the effect of loading to the external circuit driving the decoder inputs C,B and A. All the inverters in this circuit are buffer type inverters.

8.2.3 Demultiplexer

This is a logic circuit functionally reverse of a multiplexer. This circuit receives data on an input line and routes this received data on one of 2n possible output lines. The output line through which this data will be routed is determined by the n-Bit select code applied to the select inputs. The block diagram representation and the mechanical rotary switch equivalence is shown in Fig. 8.8 (a) and (b) respectively.

– – – –As an illustration let us consider a function table (TABLE 8.5) of a demultiplexer having 4 active low outputs Y0, Y1, Y2 and Y3. Two select codes (B and A) are required to route the received data (Din) through one of the four outputs. Following logic equations for the four outputs can be obtained by drawing K-map for each output separately as a function of Din, B and A.

Y
0
= D
in
☐
· BA
☐
= D
·m ; Y
in 0 1 = Din ☐· BA☐= Y2 = Din ☐· BA☐= Din·m2
and Y3 = Din ☐· BA☐ = Din· m3 Thus, In general for a demultiplexer with n select inputs and 2n outputs we may write
–
Yn–1 and mi is the minterm of n select input variables.i = Dm·mi , i = 0,1,....,2

The logic circuit of the 1-to-4 demultiplexer based on the above four equation is shown in Fig.8.9. Comparing this circuit with that of a 2-to-4 decoder as shown in Fig.8.5(b) we can see that these two circuits are exactly identical except for the fact that the active low enable input of the 2-to-4 decoder is used as the data input for a demultiplexer. It is always true that any decoder can be used as demultiplexer if the active low enable input of the decoder is used as the data input. So, a decoder having enable input is also called as decoder/ demultiplexer.

Some commercial decoder ICs have more than one enable input. Out of the mutliple enable inputs a few may be active high or low. Active high enable input of a decoder can be used as the input but the routed data at the output will be complemented.

4-to-10 Decoders : TABLE 8.6 gives a brief description of the widely used TTL 4-to-10 decoders. Out of these decoders 7442 and 7445 respond to BCD input, 7443 is used with Excess-3 code as input and 7444 is used for decoding Gray code. Each IC mentioned here generates ten mutually exclusive active low outputs. 7442 (or 7445), 7443 and 7444 are also called BCD-to-Decimal, Excess -3-to-Decimal and Excess-3 Gray-to-Decimal decoder respectively. The 7445 IC is similar to 7442 but each output of 7445 decoder is open collector type and is designed with high performance n-p-n transistor having high breakdown voltage (30V) and with capacity of sinking 80mA current. So, the outputs of 7445 are able to drive relays or indicator lamps etc. The power dissipation of 7445 IC is typically 215 m watt. TABLE 8.7 gives the functional descroption of these ICs.

7442 7443 7444 Outputs
7445 Excess-3 Excess-3 Gray
BCD input code input code input

– – – – – – – – – – D C B A D C B A D C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9

0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1
0 0 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1
0 0 1 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1
0 1 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1
0 1 0 1 1 0 0 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0
1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

TABLE 8.7 :Function table of 7442,7445, 7443 and 7444 ICs.
4-to-16 Decoder/Demultiplexers TABLE 8.8 describes the salient features of some commercially available and widely used 4-to-16 decoder/demultiplexer IC chips. All the IC chips mentioned in the table receive 4-Bit binary inputs and generates 16 mutually exclusive outputs.

8.2.5 Cascading of Decoders/Demultiplexers It was shown earlier that commercially available decoders/demultiplexers have number of outputs = 2N for N address inputs to the decoder. The number of the outputs can be increased by cascading the decoder/demultiplexer ICs. In this section we shall see how the decoders can be cascaded by the following two methods – (i) utilising the enable inputs of the decoders and other necessary logic gates. (ii) with the help of other suitable decoder.

Some examples will be considered here to

understand these two technique of cascading of

commercially available decoders.

Let us design a 5-to-32 decoder by cascading 74138
decoders and other necessary logic gates.

To have 32 outputs we need four 74138 IC chips

and to address 32 outputs one at a time we need 5

address inputs. The cascaded circuit is shown in

Fig.8.10. The three address inputs C,B and A of the 4

decoders are connected in parallel as shown in the

diagram. In this figure, C is the most significant and

A is the least significant address bit of the individual

decoder IC chip. The 2 extra inputs D and E are used

along with the enable lines of the four 74138 ICs in

such a way that for

(a) E = 0, D = 0 : The 74138-1 IC is only enabled
and all other 74138 ICs are disabled because the enable

– – – –

inputs G2A, G2B and G1 of this IC chip are G2A= 0, G

= 0, G1= 1. The mutually exclusive eight active low

2B – through Y–

are available from 74138-1 and

output Y0 7

other 24 outputs from 74138-2 to 74138-4 are high

when the inputs to E,D C, B and A varies from EDCBA

= 00000 through 00111.

(b) For E = 0, D = 1 : Only 74138-2 IC is enabled

because the three enable inputs of this IC chip are

active. The mutually exclusive eight active low

– –

outputs Y8 through Y15 are available from this chip

when the inputs to E,D,C,B and A are varied from

01000 to 01111.

(c) For E = 1, D = 0 : Only 74138-3 IC is enabled
because the three enable inputs of this IC chip are

– –

only active. The mutually exclusive eight active low outputs Y16 through Y23 are available from this chip when the inputs to E,D,C,B and A vary from EDCBA = 10000 through 10111. The outputs of the other decoders IC chips will remain in high state for these inputs to E,D,C,B and A.

(d) For E = 1, D = 1 : Only 74138-4 IC is enabled because the three enable inputs of this– – IC chip are only active. The mutually exclusive eight active low outputs Y24 through Y31 are available from this chip when the inputs to E,D,C,B and A vary from EDCBA = 11000 through 11111. The outputs of the other decoder IC chips will remain in high state for these inputs to E,D,C,B and A.

From the above discussions it is clear that if the inputs to E,D,C,B and A are varied from 00000 through 11111 then we get 32 active low outputs Y– through Y– from the cascaded0 31
circuit one at a time. Therefore, this cascaded circuit is equivalent to a 5-to-32 (or 1-of 32) decoder.

Implementation of 5-to-32 decoder can also be done using four 74138 ICs and one 2-to-4 decoder 74139 as follows. The circuit diagram is shown in Fig. 8.11. In this circuit the 74138
– – – – ICs are enabled by the active low outputs (1Y0,1Y1,1Y2 and 1Y33 to-4 decoder 74139. This unit of 74139 is enabled by grounding the enable input EN1. The address input C,B and A of all 74138 ICs are made common. Therefore, for EDCBA = 00000

– – –

the output Y0 – of 74138-1 is only low among 32 outputs. Y0 through Y31. This happens because for ED = 00, the output 1Y0 of 74139 is only low and hence 74138-1 is only enabled because this IC receives G
– – = 0, G1= 1. Under this condition if CBA = 000 then the Y–
2A= G2B 0

output of 74138-1 becomes low only. In this way the generation of the active low outputs from the other 74138 IC chips can be explained for different combinations of E,D,C,B and A. The response of this circuit towards different inputs of E,D,C,B and A has been summerised in TABLE 8.9. As a general rule a decoder in level-1 with N address inputs can be utilised to cascade 2N decoders placed in level-0. If each decoder in level-0 has M address inputs then the total number of outputs and the address inputs for the equivalent decoder will be 2N x 2M= 2(M+N)and (M+N) respectively. This technique is used whenever large number of decoders are to be cascaded.

EN1 E D Low output of 74139

—

0 0 0 1Y0—
0 0 1 1Y1—
0 1 0 1Y2—
0 1 1 1Y3

1 x x all four outputs are high

Enabled 3-to-8
decoder

74138-1
74138-2
74138-3
74138-4

No one is enabled
Low output from 74138 decoder chips for inputs to CBA 000 001 010 011 100 101 110 111
– – – – – – – – Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7– – – – – – – – Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15– – – – – – – – Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23– – – – – – – – Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31

TABLE 8.9 :Function table for the circuit in 8.11
8.3 PARITY GENERATORS AND CHECKERS

Whenever data is sent from a transmitter to a reciever, data transmission error may occur. The errors take the form of undesired changes in the bits that make up the coded information, that is a bit “I” may change to “0” or a bit “0” may change to “I”. These changes may be due to high current or voltage switching in nearby equipments, lightning, signal distortion due to long cable length, or inductive coupling (crosstalk) between adjacent conducting BCD Code Parity wires. Less frequent but more obvious and more permanent errors Bit (p) can result from components failing due to age, overheating,
0 = 0 0 0 0 0 mishandling etc. Transmission of binary information over a distance
1 = 0 0 0 1 1 is done either serially or in parallel fashion. Thus, a piece of
2 = 0 0 1 0 1 information contains a group of transmitted bits. This group of bits
3 = 0 0 1 1 0 may also be called a word. A word contains either an even or an odd
4 = 0 1 0 0 1 number of 1’s. Therefore, if there is no change in any bit of a word
5 = 0 1 0 1 0 during transmission then the odd or even number of 1’s in each
6 = 0 1 1 0 0 word should remain unchanged both at the transmitter and at the
7 = 0 1 1 1 1 receiver end i.e. a word with odd number of 1s from the transmitter
8 = 1 0 0 0 1 should reach the reciever with same odd number of 1s if there is no9 = 1 0 0 1 0 error. (Errors in more than one position will not be considered).TABLE 8.10 : BCD code Similar situation will happen for the even number of 1s.with even parity The transmission system which maintains even number of 1s in data word is called an even parity system and similarly the system which maintains odd number of 1’s is called an odd-parity system. In both cases the extra bit required to maintain the total number 1s as odd (in case of odd parity system) or even (in case of even parity system) in the data word is called the parity bit. The parity bit may be either 0 or 1 depending on the number of 1’s that are contained in the transmitted word.

Consider the BCD codes in the TABLE 8.10. In the table extra parity bit has been appended to each BCD to make the total number of 1s in each code even. Thus the total number of bits including the parity bit in the BCD is 5. Using 5 bits we may generate 25 = 32 codes but in this particular case only 10 codes are useful in BCD and the remaining 22 are non code word and therefore are ignored.

8.3.1 Parity Generator/Checker Circuit

Simple parity generator/checker circuit can be designed using EX-OR gates. We know that the EX-OR operation (MOD-2 sum) of all the bits of n-bit word gives “0” if the total number of 1 bits in the word is even and gives ‘1’ if the total number of 1 bits in the word is odd. The MOD-2 sum of two bits X1 and X2 means X1☐ X2 and in general for n-bits it is X1☐ X2☐ X3 ☐ ......☐ Xn. Based on this we can design a parity bit generator/checker circuits using all EXOR gates. Circuit in Fig.8.12(a) uses (n–1) EX-OR gates to generate a parity bit p for n-Bit word. This circuit outputs p = 1 if the number of 1’s is in n-bit word (b0b1...bn–1) is odd, and ‘0’ if the number of 1’s in the output word is even. The bit p generated by this circuit is called partiy bit. When this parity bit, p, is transmitted along with the information bits b0 through bn–1, then the total number of 1’s will be always even. Hence this circuit is called an “Even-Parity Generator Circuit”.The way in which the EX-OR gates have been connected in Fig.8.12(b) is called a “Daisy chained connection”. If an inverter is used at the output of this circuit then the Even Parity generator circuit will behave as an odd-parity generator circuit. In case of odd-parity generator circuit the output will be 1 only if the input bits b0

b1.....bn–1 contain even bits will maintain odd number of 1s. Hence, this parity bit along with the total number of 1’s of the information bits will maintain odd number of 1s.

The circuit in Fig.8.12(b) is also an Even

parity generator circuit. In this figure the

EX-OR gates are connected in a tree like structure.

In the tree like structure the maximum

propagation delay is equal to the number of levels

mutliplied by delay time in each level. The delay

time in each level is equal to the one gate delay

of EX-OR gate. But in case of daisy chained

connection the maximum propagation delay is

equal to the sum of gate delay of (N-1) EX-OR

gates. For the parity generator circuit shown in

Fig.8.12(a) the propagation delay is linear and

the number of layers is N–1 for N number of

bits. On the otherhand for the circuit shown in

Fig.8.12(b) the number of layers is log2N for N number of bits.

The parity generator circuit shown in Fig.8.12(a) and (b) can also be used as the “ Parity Checker Circuit” and this is true always. The circuit is shown using block diagram in Fig. 8.12(c).

If the even number of 1’s (including the parity bit) is maintained all through during transmission (error free transmission) then the even parity generator circuit in Fig.8.12(c) will product LOW output at X and hence

HIGH output at Y. In case of any single

bit fault during transmission the total

number 1’s to the input of this even parity

generator becomes odd then this even

parity generator circuit produces HIGH

output at X and hence LOW Y-output.

Thus, for an even parity transmissionFig. 8.12 (c) Block diagram of even parity generator

a HIGH output at Y indicates an error free transmission. Similarly, for an odd parity transmission system if the inverter at the output X is omitted then a HIGH output at X indicates an error free transmission. Thus, the parity generator circuit can be used at the receiving end of the transmission system for parity checking i.e. to detect any bit-fault during transmission.

The even parity generator circuit with an inverter attached to the output can be used as an odd parity generator circuit also. Therefore, we may conclude that “For an even parity transmission system an even parity checker circuit is nothing but an odd parity generator circuit and for an odd parity transmission system an odde parity checker circuit is nothing but an even parity generator circuit”.

8.4 4-Bit Magnitude Comparator

To compare the magnitude of two numbers A and B having larger number of bits, the comparison can be performed lexiographically. In this method, one has to start the comparison of the bits of identical positional weight of the two multibit numbers from left to right(i.e. from the most significant bit position) until we reach a bit position where they are not equal. If there is mismatch in any position) until we reach a bit position where they are not equal. If there is mismatch in any position of the two numbers then the two numbers A and B can’t be equal. A will be greater than B (i.e. A>B) if we find that Ai>Bi when the first mismatch occurs in the i-th position while scanning from left to right. A will be less than B (i.e. A<B) if we find Ai < Bi when the first mismatch occurs in the ith position scanning from left to right and A and B will be equal if Ai = Bi for all i, where i = 0 to (n–1) for a n-bit number.

In general, n-bit comparator can be designed to compare two numbers A = An–1 An– 2....A2A1A0 and B = Bn–1, Bn–2....B2 B1 B0. Commercially 4-bit and 8-bit comparator IC chips are available and the cascading these IC modules we may expand the capacity of the comparators. In this section, the design procedure of the 4-bit magnitude comparator will be described.

Let the two 4-Bit numbers be A3 A2 A1 A0 and B3 B2 B1 B0 where A3 and B3 are the MSB and A0 and B0 are the LSB.
(a) Two numbers A(☐ A3 A2 A1 A0) and B (☐ B3 B2 B1 B0) are equal in magnitude if and only if the output
(A = B)out = (A3 = B3) AND (A2 = B2) AND (A1 = B1) AND (A0 = B0) is HIGH. The equality of any two bits Ai and Bi can be determined using the equivalence function
– –
Xi = Ai Bi + Ai Bi = Ai☐Bi
Thus, the equality output of two 4-bit numbers from the 4-bit comparator can be expressed as
(A = B)out = X3 · X2 · X1 · X0 This output will be logic HIGH if the two numbers A and B are equal i.e. if X3 = X2 = X1= X0 = 1.
(b) A will be greater than B i.e. (A>B)out will be HIGH if and only if
–
(i) A3 > B3 i.e. A3 · B3 is HIGH
–
OR (ii) (A3 = B3) AND (A2 > B2) i.e. X3 (A2· B2) is HIGH
–
OR (iii) (A3 = B3) AND (A2 = B2) AND i.e.(A1> B1) i.e. X3·X2 · (A1B1) is HIGH
–
OR (iv) (A3 = B3) AND (A2 = B2) AND (A1 = B1) AND (A0 > B0) i.e. X3X2X1 (A0·B0) is HIGH.
The logic diagram for the 4-bit comparator circuit is shown in Fig.8.13. Combining the above four conditions the output (A>B)out of the 4-Bit comparator can be expressed as– – –
(A > B)out = A3·B3 + X3 (A2·B2) + X3·X2 (A1·B1) + X3·X2·X1 (A0·B0)
(c) Similarly, A will be less than B i.e. (A < B)out will be HIGH if and only if
–
(i) A3 < B3 i.e. A3 · B3 is HIGH
–
OR (ii) (A3 = B3) AND (A2 < B2) i.e. X3 (A2· B2) is HIGH
– OR (iii) (A3 = B3) AND (A2 = B2) AND i.e.(A1< B1) i.e. X3·X2 · (A1B1) is HIGH
–
OR (iv) (A3 = B3) AND (A2 = B2) AND (A1 = B1) AND (A0 < B0) i.e. X3X2X1 (A0·B0) is
HIGH. Combining the above conditions the output (A<B)out comparator can be expressed as
– – – –
(A < B)out = A3·B3 + X3 · (A2· B2) + X3·X2(A2·B2) + X3· X2 · X1(A0 · B0).

The above expressions can easily be generated to compare the magnitudes of two n-bit numbers A = An–1 An–2 .....A2 A1 A0 and B = Bn–1 Bn–2 ... B2 B1 B0 as
– – – – (A > B)out = An–1 Bn–1 + Xn–1An–2 Bn–2 + ....+ Xn–1 Xn–2 ....X2A1B1 + Xn–1Xn–2 ... X2X1A0B0.
– – – – (A < B)out = An–1Bn–1 + Xn–1An–2Bn–2 + ....+ Xn–1 Xn–2 ....X2A1B1 + Xn–1Xn–2 ... X2X1A0B0. (A = B)out = Xn–1 Xn–2 .....X2X1X0.
Using the equations which are developed for the 4-bit comparator show that B>A where B = 1110 and A = 1101.

A = A3 A2 A1 A0 = 1101
and B = B3 B2 B1 B0 = 1110.
In this example, A3 = 1, A2 = 1, A1 = 0, A0 = 1; B3 = 1, B2 = 1, B1 = 1 and B0 = 0. Therefore, X3 = X2 = 1 and X1 = X0 = 0.

– – – –
(A>B)out = A3B3 + X3 A2B2 + X3 X2 A1B1+ X3X2X1 A0B0.
= 1.0 + 1.1.0 + 1.1.0.0 + 1.1.0.1.1 = 0
– – – – (A< B)out = A3B3 + X3 A2B2 + X3 X2 A1B1+ X3X2X1 A0B0.
= 0.1 + 1.0.1 + 1.1.1.1 + 1.1.0.0.0 = 1
(A = B)out = X3 X2 X1 X0 = 1.1.0.0 = 0
(A <B)out is only logically HIGH therefore, B > A.

8.5 CODE CONVERTERS
Different computer codes are possible. In chapter - 2 a few of the useful codes have been described. The usefulness of the the codes depends mainly on two factors : (a) How efficiently these codes satisfy the need of machine -to-machine or human-to human communications.

(b) How less complex hardware is needed to generate these codes, decoding these codes and to convert from one code to another.
In this section a few useful circuits will be discussed and developed for converting one code to another. The circuit which converts one code to another are called “CODE CONVERTER”.
The design of a code converter is not usually complicated. The design process may start from the truth table of the Input/Output codes or using a conversion algorithm. For a design with minimum number of logic gates we may use the minimisation techniques as described in the earlier chapter.

Following are some examples for the design of some common code converter circuits. 8.5.1 Gray-to-Binary and Binary -to-Gray Code Converter In chapter-2 the Gray code has already been defined and also the relationship between the Gray bit of the Gray code and the Binary bit of the Binary code has been developed. Using those relationship we may now draw the gate level circuit for the two types of the code converters, The inter relationship between the bits of the two codes are repeated and the code converter circuits are shown in Fig.8.14.

Fig.8.14: (a) Block diagram of Gray-to-Binary and Binary-to-Gray code converters Logic circuit of (b) Gray-to-Binary (c) Binary-to-Gray Code converters From the above two circuits it may be observed that for Gray-to-Binary code converter each output from B0 to Bn–3 depends on the previous output of the XOR gate but it is not the case for Binary-to-Gray code converter. Therefore, the Gray-to- Binary code converter circuit is slower compared to Binary-to-Gray code converter circuit.

8.5.2 BCD-to XS-3 and XS-3 to -BCD Code Converter

The conversion table to convert 8-4-2-1 BCD code to XS-3 code is shown in the TABLE 8.11. Each variable of the XS-3 code can be written in terms of the four variables B8,B4,B2 and B1 of the 8-4-2-1 BCD code as follows Y3 = ☐m(5,6,7,8,9) + ☐☐(10 –15)
Y2 = ☐m(1,2,3,4,9) + ☐☐(10 –15)
Y1 = ☐m(0,3,4,7,8) + ☐☐(10 –15)
Y0 = ☐m(0,2,4,6,8) + ☐☐(10 –15) where mi = m(B8,B4,B2,B1) and☐10 to☐15 are don’t care terms corresponding to the NonBCD inputs.
Drawing K-maps for each variable of the XS-3 code we get the following simplified logic expressions
Y3 = B8 + B4B2 + B4B1 = B8 + B4 (B2+ B1)
– – – –
Y2 = B4B1 + B4B2 + B4B2B1 =B4☐(B2 ☐ B )
– –1
Y1 = B2B1 + B2B1 = (B2☐B )
–1
Y0 = B1.
The logic circuit using these expressions is drawn in Fig.8.15.

XS-3 to BCD code converter can be designed following the similar approach. To get the logic expressions for the four outputs of this code converter we can use the TABLE 8.12 where Y3,Y2 Y1 and Y0 will be used as inputs and B8,B4,B2 and B1 as ouputs. Each output of this code converter can now be written as the canonical SOP form.

B8 = ☐m(11,12) + ☐☐(0 –2,13 –15)
B4 = ☐m(7,8,9,10) + ☐☐(0 –2,13 –15)
B2 = ☐m(5,6,9,10) + ☐☐(0 –2,13 –15)
B1 = ☐m(4,6,8,10,12) + ☐☐(0 –2,13 –15) Following simplified expressions can be obtained for B8, B4,B2 and B1 using K-maps.

B8 = Y3 Y1 Y0 + Y3Y2 = Y3 (Y1Y0+ Y2)
– – –
B4 = Y2Y1 + Y3Y1Y0 + Y2Y1Y0

B2 = Y0 ☐ Y1–
B1 = Y0
The logic circuit for the XS-3-to-BCD code converter is shown in Fig.8.16.
8.5.3 Binary-to-BCD and BCD-to-Binary Code Converter Binary-to-BCD conversion is necessary where a digital system works primarily on a straight binary format but the output is to be translated into a format that is suitable with BCD oriented output devices like different displays. Therefore, we need a circuit to convert binary data into BCD form. On the otherhand, many peripherals generate BCD input to the digital circuits for mathematical or logical processing. For a digital circuit it is easier to handle the binary number instead of BCD. Therefore, some circuits are needed to translate BCD inputs into binary. Following two subsections describe the algorithm for the above two conversions and the logic circuit based on the algorithm.

8.5.3.1 Binary-to-BCD Code Converter
For a n-Bit binary number NB = bn–1 bn–2 .....b1b0 , the decimal equivalent value of the binary number is ND = bn–1 2n–1 + bn–22n–2 +....+ b121 + b020.

This can also be expressed using nested Mutliplication as follows
ND = (((.....(((bn–1)☐ 2 + bn–3)☐ 2 + bn–3)☐ 2 +.....+ b1)☐ 2 ) + b0).

For a binary number system, multiplication of a bit by 2 means shifting of that bit once towards left with reference to its present position. The multiplication by 2 can be done

using a logic circuit module called shift register where the binary bits can be shifted into it one by one. Fig. 8.17 illustrates how the bits can be shifted into the register starting with MSB of the 5-Bit binary number b4b3b2b1b0 through the least significant position of the shift register and how the bits are doubled each time due each left shift. In this process the MSB (b4) of the 5-Bit number is entered through the least significant position (positional

weight = 20) and is shifted 2 times, b1 is shifted once and no shift to b0 with respect to 20 to get the sum of weighted value of the 5-Bit number. The values after each shift are indicated on the left side of shift register in this figure. This process of shifting can be also allowed to convert a N-Bit binary number into its BCD equivalent. But we need some intermediate corrections during shifting. The need of the corrections are due to two reasons as described below.

(1) Any 4-Bit group exceeding 1001 upto 1111 does not represent correct BCD form.

This needs a correction when it occurs within a decade due to the left shift. (2) The second correction is needed when a Bit-1 from the MSB position of a decade
is shifted to the LSB position of the next higher decade adjacent to it.

Fig 8.18 shows that the positional weight of the four bits within the i th decade are (23– 22–21–20)☐ 10i. Thus, due to left shift the value of 1-Bit is doubled like the binary number system within a decade but does not follow this rule when a 1-Bit shifts from the MSB position of one decade to the LSB position of the adjacent decade.

For the correction of the first type mentioned above we have to add 0110 ( ☐ 6) to that decade which becomes NON-BCD after 4 shifts. This addition converts a NON-BCD 4 Bit group to a correct BCD form. This can be illustrated as follows with a few examples.

The operation equivalent to above correction is to add 0011 ( ☐3) after 3 shifts instead of addition of 0110 (☐ 6) after 4 shifts. The addition of 0011 is to be done if the 4-Bit number within a decade becomes equal to 0101 (☐ 5) or greater than 0101 after 3 left shifts. This can be done because the addition of 0011 to a shifted 3-Bits group 101 through 111 is equivalent to the addition of 0110 to the NON-BCD (1010 through 1111) after 4th shift. This may be illustrated with two examples as shown in Fig.8.19.

The BCD decades in Fig.8.19 shows that the weight of a bit is doubled when it is shifted each time to left within a decade but the positional weight of Bit-1 changes from 8 ☐100(☐ 8) to 1☐101(☐1010) whenever it crosses the boundary of decade-0 to decade-1 instead of from 23(☐ 8) to 24(☐ 16) as we saw in case of binary. So, there is a loss of 6 due to a shift from decade-0 to decade-1. Similarly, there will be a loss of 60 when a Bit-1 crosses the boundary of decade-1 and decade2 because for normal shift it should be 80 to 160 but it becomes 100 and a loss of 600 when a Bit-1 crosses the boundary of decade2 to get the correct BCD from binary these losses should have to be compensated by adding 0011(☐☐ Bit of the decade whenever a bit 1 leaves that group and moves to the higher decade on left. Alternately, 0011(☐ 3) can be added prior to the shifting whenever 1 is found in the MSB of a decade prior to shifting. The weight 3 is doubled in the left shifting operation which is equivalent to the addition of 6 after the left shift.

Thus, it turns out that all the necessary corrections will take place automatically if, prior to shifting, 0011 is added to the values of those decades which contain a number of greater than 0100. The value of any decade may exceed 0100 just after 3 shifts or at the end of 4 shifts. This algorithm is called “Add and shift algorithm”. Following are some examples to illustrate the above algorithm.

8.5.3.2 BCD-to-Binary Code Converter

The algorithm used in this conversion process is reverse to that we followed in case of Binary-to-BCD code conversion. This conversion process is based on the repeated application of “Shift right and subtract 3”. We know that each shift right operation of a binary number is equivalent to division by 2. Check the Fig.8.18 which represent the positional weights of the bits of a multiple decade BCD number. From this figure it may be noted that whenever a ‘1’ crosses the boundary of decade-1 and decade-0 during a right shift the positional weight changes from 20☐ 101 = 10 to 23 ☐ 100 = 8 instead of a change from 10 to 5. So, the resulting in a value 3 higher than it should be. Similarly, a gain of 30 occurs when ‘1’ enter into decade-1 from decade2. For this reason, a correction is to be done by subtracting 3(☐0011) from the value of those decades to which a ‘1’ is shifted from its adjacent higher decades due to a right shift. It may be noted here that the subtraction of 3 from decade-0 means a subtraction of 3☐100, but subtraction of 3 from decade-1, decade2.....decade-i means a subtraction of 3 ☐101, 3☐102 ,....., 3☐10i from those decades respectively. Consequently, if a 4-Bit group of any decade is found to contain ‘1’ in its most significant position after the completion of a right shift then 3(☐ 0011) is to be subtracted from that decade. Instead of subtracting 0011 we may also add the 2’s complement of 0011

i.e. 1101 to such decade for correction. When 2’s complement operation is done then the carry-out, if any has to be discarded. This correction is made only after a right shift. The new number after the correction may be greater than or equal to 1000 but must not be

corrected again without performing

the next right shift. The process of

right shift and subtraction of 3 should

have to be terminated after several

right shifts and necessary corrections

when the contents of all the decades

except decade-0 become all 0s and

decade-0 contains a number less than

1000. If the contents of decade-0 is

greater than 1000 then another right

shift is required.

Here is one illustration shown in

Fig.8.20 to convert (1001 1000 0110)BCD

☐ 98610 into its binary equivalent. The

process of conversion in step-by-step

is shown in this figure. The shifted ‘1’

into the lower decade from its adjacent

higher decade has been marked with

‘* ’. This process of conversion has

been terminated when the contents of

decade2, decade-1 are all 0s and

content of decade-0 is less than 8. The

binary number for the given BCD is

equal to the content of decade-0 and

the shifted out bits. In this particular

illustration the content of decade-0 is

0111 and the shifted-out bits are

1011010 so the binary number

equivalent to given BCD is

01111011010.

Convert (01110101)BCD = 7510 into

binary using shift-right and subtract

3 algorithm.

The solution for this problem is shown step-by-step in Fig.8.21. The binary number equivalent to the given BCD is (01001011)2. The last right shift in this example can be avoided.

The above algorithms for the BCD to Binary

conversion can be implemented using combinational

logic circuit. Like binary-to-BCD conversion we can

now develop a correction circuit as an unit cell which

will detect any 4-Bit number greater than or equal to

1000 in any decade after a right shift operation and

subtracts 0011 from that decades as a correction. The

block diagram representation of the unit cell of the

correction circuit is shown in Fig.8.22. In this figure

D0 C0 B0 A0 representing bits of decade-0 and A1 is the

least significant bit of the adjacent upper decade. This

bit enters from upper decade-1 into the input D of the

correction circuit after a right shift and the four bits of

decade-0 are shifted one position right. So, A0 is the

shifted-out bit which becomes equal to the binary bit

b0. TABLE 8.13 shows different possible combinations

of A1D0C0B0A0 and their corresponding binary outputsFig.8.21

b4b3b2b1b0 after correction. First ten inputs need no correction because ‘1’ is shifted into the D input of the correction circuit from the adjacent upper decade. Second ten lines of this table need correction because ‘1’ is shifted into the D input of the circuit. The entries in the last three rows never occur because D0C0B0A0 are not valid BCD. For this condition A1 may be either 0 or 1. So, the binary output on b0 to b4 are all don’t care type.

From this function table we may get the logic expressions for the outputs W,X Y and Z of the correction circuit as shown below.
W = DC + DBA = DC· DBA

– – ––
X= DC + DBA + DCA
= DC· DBA· DCA

– – –
Y= BA + DB + DBA
Fig 8.22
= BA· DB· DBA

Z= D ☐A

To get the above expressions we may use four 4-variable k-maps for W,X,Y and Z with four map variables D,C,B and A. Using the above expressions we may now draw the logic circuit for the correction as shown in Fig.8.23.

Fig 8.23
By cascading such unit cell of the correcting circuit a BCD number of any length can be converted into binary.
8.6 DISPLAY AND DISPLAY DRIVER

It is now a common practice in the field of instrumentation and even in the entertainment electronic to show the results or to indicate the variation of the value of parameters using some solid state optoelectronic visual display instead of old electromechanical indicator or gas discharge displays. Now-a-days all most all display units are fabricated using Light Emitting Diodes (LED) or liquid Crystal Display (LCD). These LED or LCD can be used as a single unit or the LEDs or LCDs can be arranged in segment form or in matrix form or are arranged in the form of a bar (bar graph display). All these display units are available in the form of a package covered with transperent material. Physical appearance of the display units is shown in Fig.8.24. In the display units each dot or segment means an LED or LCD.

Fig 8.24
Fig 8.24 Fig 8.24 Fig 8.24
Fig 8.24

For the single LED package shown in Fig.8.24(a) the two legs mean two electrode connected to the anode and cathode ends of the LED. Conventionally, the longer leg (A) and the shorter leg(c) represent the anode and cathode respectively. The internal connections of the LEDs of the display modules (dot matrix [Fig.8.24(b)] are such that each dot or the segment or a bar can be accessed seperately through the external pins available on the package. By selective forward biasing the individual dot or the segment, one can display an illuminated shape of numeric and alphabetic character on the display modules. Alphanumeric characters can be displayed on the dot matrix display, digit symbols 0 through 9 and the upper case English alphabets ‘A’ through ‘F’ and a few other alphabetic character can be displayed on the 7-segment display unit [Fig.8.24(c)] and digit symbols 0 through 9 and all the upper case English alphabets can be displayed on the 16 segment display shown in Fig.8.24(d).

8.6.1 LED Display

The widely used visual indicator in the electronic circuits is the single LED or the collection of LEDs. The LED is PN junction diode fabricated with different semiconducting materials

like Gallium Phosphide, Gallium Aluminium Phosphie and Gallium Nitride etc. dopped with different dopents of different concentrations to get the different coloured visible light and infrared emission when the

PN junction in forward biased.

The colour output of the visible

light and the forward voltage

drop of the LEDs are tabulated

in TABLE 8.14. Most practical

LEDs have maximum reverse

voltage ratings in the range of

3 to 5 Volts. Commercially the

package of a single LED or two

LEDs are available. The circuit symbol of a single LED indicator is shown in Fig.8.25(a). To make difference between the LEDs and the other diodes two arrow headed lines are attached to the normal symbol of a diode to indicate the rays of light emitted from the LED. In a bi Fig 8.25 Fig 8.25
Fig 8.25

colour LED package two LEDs of colours RED and GREEN are housed in a single package and are connected as shown in Fig.8.25(b) & B.25(c). So, in bi-colour package only one LED can be illuminated at a time

by changing the polarity of the

power supply. This package of bi

colour LED is useful for polarity,

indication or null detection. In the

tri-colour configuration, both

LEDs can be illuminated at the

same time, generating a mixture

of the two colours in addition to
only RED and GREEN. This package is also called a common cathode package because the cathode ends of the two LEDs are connected together. The mixed colour output depends on the current passing through the two LEDs. A rough estimate of the current is given in the TABLE 8.15 for the different colours from a tri-colour package.

Driving Circuit for LED : Light emission occurs when the PN junction of LED is forward biased and it needs approximately a forward operating voltage of about Vf☐2.0V and a forward current Id between 10mA and 20mA for reasonable
brightness. Therefore, if we drive the LED with a DC voltage Vdc

greater than Vf shown Fig.8.26(a) then the voltage Vdc – Vf should

have to be dropped across one resistor R which is connected in

series with the LED. The current through LED is assumed to be

within a limit of 20mA. From this figure we may write

VR = Vdc – V
f Fig.8.26(a)
or, IdR = Vdc – Vf
-Vfor, R = Vdc
Id If we assume that Vf = 2.0V and Id = 15mA then R☐ 200 ☐ when Vdc= 5V. Similarly, for the same value of Vf but Id = 10mA the value of the series resistor R will be 300 ☐. It is a common practice to use 270☐ ☐ R☐ 300 ☐ in series with a LED for reasonable brightness.

We may use several LEDs in series as shown in

Fig.8.26(b). For this connection the value of series

resgistor R may be computed from the formula.

Vdc -(Vf1☐Vf 2 ☐Vf3)
R = Id
where Vf1, Vf2 and Vf3 are the forward voltage Fig 8.26
drops of their LEDs L1L2 and L3. In this case Vdc should be greater than the sum of the forward voltage drops of the individual LED.

If more LEDs are to be illuminated using the above then a limitation will come when the sum of the forward voltage drops of the LEDs is nearly equal to or greater than the driving voltage Vdc. Under this condition we can distribute the LEDs into two or more branches as shown in Fig.8.26(c) so that the sum of the forward voltages of the LEDs in series in each branch is less than Vdc. Current limiting resistor has to be used for each branch seperately, In this way almost any number of LEDs can be connected provided the driving voltage Vdc has sufficient current drive Id to satisfy the sum of the branch current Id1,Id2 etc.

The circuit Fig.8.26(d) is another connection for simultaneous glowing of LEDs. This circuit is not economic because each LED draws its own forward current. Also, each LED in Fig.8.26(d) needs its own current limiting resistor.

The circuit in Fig.8.26(e) may be attempted to glow the LEDs simultaneously. But all the LEDs may not have exactly equal forward voltage drop therefore unequal current through LEDs leading to the unequal brightness of the LEDs. Even, it may so happen that some LEDs will not glow due to insufficient current because the LEDs with low forward voltage drop will allow the maximum current through it.

Fig 8.26

When the driving current is not sufficient to drive even a single LED then we may use the driving circuit as shown in Fig.8.26(f). This circuit uses a transistor Q1 in switched mode. When Q1 is switched ON then the collector current flows through the LED and this current should be sufficient to glow this LED to the desired brightness and when Q1 is switched OFF then LED will not glow. In this circuit the driving voltage Vi should be enough to saturate the transistor Q1. Assuming VBE(Sat)☐ 0.6VCE(sat)☐ 0.2V, hfe(min) = 100, Vi = 2V, IC(max) = 50mA, Vcc = 9V, forward voltage drop of the LED Vf = 1.6V and limiting collector current IC flowing through the LED to be 15mA.

we get R15☐10-3
V 2-0.6
I
VCC -Vf -VCE(sat) = 9-1.6-0.2 = 400☐C = IC Vi -VBE(sat) = (15☐10-3/ 100)= 93.3K☐and RB = i -VBE(Sat) = (IC / hFE)B

Fig 8.26
The LED can also be driven by the output of a logic gate as shown in Fig.8.26(g) and Fig.8.26(h). LED connected at the output of a gate is used to indicate the logic state of the output of a gate. The LED can be connected either in a sink mode or source mode.

Fig 8.26
Fig 8.26

In the sink mode the LED glows when the output is at logic low and the current passing through the LED is the sink current of the driving logic gate. In the source mode the LED glows when the output of the driver gate is at logic high and the source current passes through the LED. In source mode no current limiting resistor is required because the internal pull-up resistor at the collector of the ON transistor of the totem-pole circuit limits the current of the LED. This is shown in Fig.8.26(h). In the sink mode the external resistor is to be adjusted so that the forward current Id = (VCC– VOL– Vf– VR)/R is smaller than IOL(max) of the driver gate otherwise the lower transistor of the totem pole circuit of the driver gate will come out of saturation and the voltage level of VOL will rise above the upper limit VOL(max) and also an excessive sink current this transistor will be damaged. For example, the sink current of the 74LS logic gates should not be above 15mA and actually be limited to around 10mA in practice. For this current, VOL lies between 0.4V and 0.5V. But 74LS buffers can be operated at sink current around 20mA. It is better to use LED in the sink mode because the source current is much smaller than the sink current.

8.6.2 7-Segment Display

The simplest means to indicate the numerals ‘0’ through ‘9’ by the illuminated display is to arrange seven LEDs in the shape of figure-of-eight within a package as shown in Fig. 8.27(a). Each segment has a rectangular transparent opeing beneath which one LED is placed. Segments are optically isolated from each other.

Besides the seven segments as shown in Fig.8.27(a), two

LEDs are also provided in the package to indicate the right and left decimal points (Rdp, Ldp) for displaying multidigit

numberic result containing fractional part. The segments

are conventionally desginated by the lowercase letters ‘a’ through ‘g’ beginning with ‘a’ at the top and progressing clockwise. Illuminating the segments ‘a’ through ‘g’

Fig 8.27 selectively we can have the 7-segment display font as shown in Fig.8.27(c) but the most popular use of this display module is for nummeric display from ‘0’ through ‘9’. Dot versions of 7-segment display is also available.

Fig 8.27(c)
Fig 8.27(d)

The dot version contains 20LEDs excluding two LEDs for the decimal points. This is shown in Fig.8.27(b).The dot version has a somewhat more legible font and allows display of a few alphabetic characters. The font of this display is shown in Fig.8.27(d). This dot version of the 7-segment display needs a complex driver circuit which is not so readily avaialble commercially. Normally this type of display is drived using memory chips.

Following two types of 7-segment LED display modules are manufactured (a) Common Anode Type (CA type) and
(b) Common Cathode Type (CC type).

Fig 8.28(a)
In common anode type 7-segment display all the anode ends of the internal LEDs of the package are tied up to a common terminal as shown in Fig.8.28(a) and in common Fig 8.28(b)

cathode type 7-segment display all the cathode ends of the internal LEDs of the package are tied up to a common terminal as shown in Fig. 8.28(b). Though the LEDs in these two figures are arranged in figures are arranged in segment display and two decimal points ‘Rdp’ and ‘Ldp’. In most of the cases only one LED is provided for the decimal point.

The common anode type 7 segment display is also called pull-down display. This is so called because for glowing one LED from the group of LEDs of this configuration one has to pull down the cathode of that LED to a low voltage via current limiting resistor and to connect the common anode terminal to a sufficiently positive voltage such that the voltage drop across the LED is enough to forward bias the LED. Thus, the circuit driving the cathodes of the common anode display should be able to sink the forward current of the forward biased LEDs.

In common cathode type display, the cathodes of all the LEDs internal to display modules are connected to a common point called common cathode point. This common cathode point is accessible to the user which is brought out on a pin external to the display module.

The common cathode display are also called a pull-up display. This is so called because to glow one or more LEDs of this type of display the anodes of the selected LEDs should be pulled up to a positive high voltage via the current limiting resistor such that the selected LEDs become forward biased. Thus, the circuit drivign the anodes of the common cathode

type has to source currents to the LEDs. TABLE 8.16 shows the fonts of the different number and alphabetic characters which depends on the different forward biased segment –LEDs ‘a’ through ‘g’. The ON LEDs and the OFF LEDs are indicated using ticks and cross marks respectively.

8.6.3 7-Segment Diaplay Driver

From the above discussion it is clear that for different display characters (numeric and a few alphabetic) on a 7-segment display module we have to switch-on (forward bias) the LED according to the TABLE 8.16. So, we need an interface circuit which receives the codes of the characters and generates 7-segment code corresponding to that received code Fig 8.29(a)

to illuminate the proper segments ‘a’ through ‘g’ of the 7-segment display so that we can see the illuminated shapes of the received characters. Normally, the received codes for the numerals for ‘0’ to ‘9’ are in BCD. The main use of 7 segment displays is for numeric display. The driver interface circuit which is used to interface the source generating the BCD code of the numerals and the display module is called “BCD-to-7 segment decoder driver”. Some decoder/driver allows non-BCD codes like 1010, 1011, 1100, 1101, 1110, 1111 as the 4-Bit input and displays segmented fonts of A,b,c,d, E, and F respectively. The display correspondong to 1011 and 1101 are the lower case alphabets ‘b’ and ‘d’ respectively, because the fonts of ‘B’ and ‘D are indistinguishable from the fonts of ‘8’ and respectively, because the fonts of ‘B’ and ‘D are indistinguishable from the fonts of ‘8’ and segment codes for the numerals ‘0’ through ‘9’ and for alphabets A,b,C,d,E and F is called ‘hexadecimal decoder/ driver’.
Commercially, BCD-to-7 segment decoders are available in IC chip form to drive either Common Anode (CA) or Common Cathode (CC) type 7-segment display. Besides the 4-Bit BCD code inputs and the 7-segment code outputs the commercial decoder/driver ICs have some additional control inputs for blanking the display leading or trailing zero in case of multidigit display and for testing all segment LEDs of the display simultaneously etc. All the features will be considered during the description of the individual chip. Simple block diagram representation of the two types of decoder/drivers and their connections to segment LEDs of the two types of 7-segment display modules are shown in Fig.8.89. The truth table showing the logic levels of the outputs for different BCD and Non-BCD inputs from the decoder/driver is shown in the TABLE 8.17. The outputs of the decoder/driver driving the Fig 8.29 (b)

common anode display are active low type so each output of this decoder should be able to sink current coming through the ON segment LEDs. The current flowing through the LEDs should be limited within the maximum allowable sink current of the output of the decoder/driver by connecting the current limiting resistor to each cathode end of the segmentLEDs of the common anode display module. The direction of the current flow is shown in Fig.8.29(a). Normally, the display drivers for the common anode type display have open collector type outputs.

The common cathode type diaply driver IC sources the current through the segment LEDs and does not require any use of the current limiting resistors (fig. 8.29b) at its outputs because the resistor connected at the collector of the internal transistor of the decoder/ driver limits the source current through the LEDs connected at the outputs. As the source

current is smaller compared to the sink current so the decodes/driver ICs driving common cathode type display need current boosting using the external transistors or buffer external transistors or buffer ICs. This will be discussed next.

TABLE 8.17 shows the seven outputs ‘a’ through ‘g’ of the decoder/driver having active low and high outputs only for BCD inputs DCBA= 0000 through 1001. The NON-BCD inputs have not been considered in the table because the outputs for the NON-BCD inputs may not be standard for the commercially available decoder/driver manufactured by the different manufacturers. This table also shows that for the BCD code 0110 (☐6) and 1001 (☐9) there may be two possible outputs on ‘a’ through ‘g’ of the decoder/driver to have two types of display fonts for 6 as or as and for 9 as or as .

In principle, it is possible to design a BCD-to-7 segment circuit using standard SSI IC chips, but the final circuit will be too much complex and expensive also. But without question, the wise approach is to use the commercial ICs available for this purpose. Almost all the IC manufacturers produce the BCD-to-7 segment decoder/driver ICs with some additional features.

Decimal Active high digit Code input D C B A 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0

7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Active low 7-segment outputs (CA display)
a b c d e f g
0 0 0 0 0 0 1
1 0 0 1 1 1 1
0 0 1 0 0 1 0
0 0 0 0 1 1 0
1 0 0 1 1 0 0
0 1 0 0 1 0 0
1 1 0 0 0 0 0 or
0 1 0 0 0 0 0
0 0 0 1 1 1 1
0 0 0 0 0 0 0
0 0 0 1 1 0 0 or
0 0 0 0 1 0 0

Active high 7-segment Display outputs (CC display) Font
a b c d e f g
1 1 1 1 1 1 0

0 1 1 0 0 0 0

1 1 0 1 1 0 1

1 1 1 1 0 0 1

0 1 1 0 0 1 1

1 0 1 1 0 1 1

0 0 1 1 1 1 1
or
1 0 1 1 1 1 1
1 1 1 0 0 0 0

1 1 1 1 1 1 1

1 1 1 0 0 1 1
or
1 1 1 1 0 1 1

Table 8.17 : Truth table of the common anode (active low output) and common cathode (active high output) display decoder/driver.
8.7 Encoders and Priority Encoders An encoder performs the opposite function of a decoder. Thus, an encoder is a logic circuit whose each input is a piece of information and the outputs are the uniquely coded representation of these inputs. The number of bits required for such encoding depends on the number of elements of inputs. For n elements of information to be uniquely encoded, the output code of width m must satisfy the following relation 2m n. For example, to encode 10 decimal digits distinctly we need a group of 4 binary bits. Here m = 4 and n = 10. The distinct codes may be arbitrarily assigned to the inputs. In case of simple encoder the drawback is that this circuit cannot encode properly if more than one input are active simultaneously. To prevent this odd situation a new type of encoder circuitis designed which is called “Priority encoder,” A Priority encoder responds only to one input when more than one input are simultaneously active, in accordance with some priority. The most common priority system is based on the relative magnitude of the inputs. For example, a decimal-to-BCD priority encoder will encode the input for 7 if two inputs 5 and 7 are used simultaneously to this type of encoder. This happens because 7 has the higher priority than 5.

Designan encodercircuit which has 4 active high inputs I3, I2, I1 and I0. This circuitneeds to produce 6-bit distinct code for each input as shown in the Table - 8.39. The restriction regarding the inputs is that only one input may be active at a time.

The block diagram for the requiredcircuit is shown Fig 8.30(a). In this diagram there are 4 inputs. For any single active high input the circuit output is a 6-bit code on Y0 throughY5 output lines.

Input Output

I3 I2 I1 I0 Y5 Y4 Y3 Y2 Y1 Y0

1 0 0 0 1 0 1 1 0 1

0 1 0 0 1 1 0 0 1 0

0 0 1 0 0 1 0 1 0 0
0 0 0 1 0 1 1 0 1 1

Table 8.18
Fig 8.30(a) Fig 8.30(b) : Encoder Circuit for the example 34.

This encoder can be designed by looking at the output coloumns for Is in Table 8.18. We may write Y5 = I3 + I2, Y4 = I2 + I1 + I0, Y3 = I3 + I0, Y2 = I3 + I1, Y1 = I2 + I0 and Y0 = I3 + I0, The logic circuit based on these 6 equations can be drawn as shown in Fig. 8.30 (b).

8.7.1 : Decimal-to-BCD Encoder The logic symbol of this encoder is shown in Fig. 8.31.
In this encoder three are 10 inputs, I0, I1, ..., I9 each representing an input for a decimal digit. The output of this encoder has 4 parallel outputs (D, C, B and A). Each 4-Bit output corresponds to BCD code of the input line. For example, When only I5 input is active out-of ten inputs then the BCD output of this circuit will give BCD code of 5 i.e. 0101. Similarly, for input I8 the output will be 1000. We assume all inputs are active high. The input / output relationship of this encoder is shown in Table 8.19.

Fig. 8.31 : Logic Symbol for a
Decimal-to-BCD encoder
Table 8.19 : Function table of the Decimal-to-BCD encoder The table shows that the output bit D of the output BCD code becomes 1 only when the input I8 or I9 is high otherwise it is always 0. So, we may write.

D = I8 + I9

Similarly, the other output bits, C, B and A can be written as
C = I4 + I5 + I6 + I7, B = I2 + I3 + I6 + I7 and
A = I1 + I3 + I5 + I7 + I9.
Now, we can implement the required logic circuit for encoding each decimal digit to a BCD code by using the above logic expressions. We need to OR the appropriate inputs to form BCD output. The logic circuit for decimal to BCD is shown in Fig. 8.32. The inputs to all the OR gate are normally low but when a

Fig. 8.32 : Logic circuit of Decimal-toBCD encoder
HIGH input appears then the outputs of the OR gates become High depending on the input For example if I7 is HIGH the outputs are D = 0, C = 1, B = 1 and A = 1. The I0 is input is not needed because the BCD output bits are all 0 which is same when no inputs are used.

8.7.2 : Octal-t0-Binary Encoder

Using the same approach followed in the case of Decimal-to-BCD encoder we can design an Octal-to-Binary encoder. In the octal encoder there are 8 inputs. To encode these 8 inputs in an unique way we need at least 3-bit output. In this design we take 3-bit output. The inputs and the outputs of an encoder may be either active high or low. For this particular case we consider all active low inputs and three active high outputs. Block diagram representation of such an encoder is shown in Fig. 8.33 (a). The Table 8.20 describes the function of such an encoder. From this

table it is seen that when no inputs

are used (first row of Table 8.20)

or when the input line 7 is nade

active then the output code

becomes CBA = 111. But for the

inputs other than the first row of

this table we get the octal code at

the output corresponding to the

input used. Also, it may be noted

that the inputs are active low one

at a time.

From this table we m ay write the following logic equations Table 8.20 : Function table of the Decimal-to-BCD encoder
for the outputs considering 0s of the inputs.

Fig. 8.33
The logic circuit for the Octal-to-Binary encoder is shown in Fig. 8.33 (b). In this case the input I7 is not used.
Design a Decimal-to-XS3 encoder with active high inputs and outputs.
The function table of such an encoder is shown in Table 8.21. From this table we may develop the following logic equations describing the inputs and outputs.
Fig. 8.34 : Logic circuit for the
Decimal-to-XS-3 encoder
A = I0 + I2 + I4 + I6 + I
8
B = I0 + I3 + I4 + I7 + I
8 Table 8.21

C = I1 + I2 + I3 + I4 + I9
D = I5 + I6 + I7 + I8 + I9
The logic circuit based on these equations are shown in Fig. 8.34.
8.7.3 : Priority Encoder In the previous design of the encoders it has always been mentioned that the input should be active (may be either HIGH or LOW) one at a time otherwise the code which will be produced may or may not correspond to the input. This statement may be verified considering any one of the encoders designed so far.

Consider a Decimal-to-BCD encoder (not priority encoder) with all active HIGH inputs. What will be the output code if the input lines I5 and I6 are used simultaneously?

From the Table 8.21 we may write the following :
For I5 the code is DCBA = 0101

For I6 the code is DCBA = 0110, if they are used separately. But these inputs are used simultaneously then the code at the output will be DCBA = 0111 which is a code of input I7 and not a code for either I5 or I6.

From the example it is noted that a faulty code is generated at the output if more than one input are active at the same time. A modified version of this type of encoder circuit avoiding this drawback is the Priority Encoder that ensures that when two or more inputs are used, the output code will correspond to the highest numbered input. For example, in Example-36 the output code will be for I6 only, though the two inputs I5 and I6 are used, in case of the primary encoder because the input I6 has higher priority over I5.

Design a four input priority encoder such that when two inputs, Ii and Ij are high simultaneously, Ii has priority over Ii when i > j. The encoder should produce the following 2-bit code for the four inputs I0, I1, I2 and I3 : I0 ☐ 00, I1 ☐ 01, I2 ☐ 10 and I3 ☐ 11.
From the statement of the problem we may I0 I1 I2 I3 Y1 Y0 develop the function table (Table 8.22) for this encoder. 1 0 0 0 0 0 This table shows that Y1 is true when I2 = 1, I3 = 0, I1
= I0 = ☐ or when I3 = 1, I2 = I1 = I0 = ☐☐ The logic☐ 1 0 0 0 1 equation of Y1 as a function of I3, I2, I1 and I0 can be ☐ ☐1 0 1 0 obtained using the K-map as shown in Fig. 8.35. ☐ ☐ ☐
1
1
1

Similarly, Y0 is true when I1 = 1, I2 = I3 = 0, I0 =☐or when I3 = 1, I2 = I1 = I0 = ☐. The output Y0 can be expressed Table 8.22 in terms of I3, I2, I1 and I0 from the K-maps we get Y1 = I 3
+ I
2
, Y
0
= I
3
+ I
-
2I1.
The logic circuit for this encoder is shown in Fig. 8.35.
Fig. 8.35 (a) K-map for Y1 Fig. 8.35 (b) K-map for Y0 Fig. 8.35 (c) Logic circuit for the Example 37.

(a) Develop a truth table for a priority encoder with 3 active high inputs (A, B and C) such that the input C with least priority produces an output code 01, input B with next higher priority produces a code 10 and the input A with higher priority input produces code 11. This circuit should have another active low output called ‘INACTIVE’ output which indicates that no inputs have been used i.e., A = B = C = 0.

(b) Implement the encoder circuit with a 3-to-8 decoder (74318) and other necessary logic gates.
(c) Implement the same encoder circuit using a 4-to-1 MUX and other necessary logic gates.
(d) Compare the economy of the two designs.

(a) The truth table for this encoder is
shown in Table 8.23.A B C Y1 Y0 INACTIVE (b) It is easy to find the logic equations for Y1, Y0 0 0 0 0 0 0and INACTIVE considering 0s of the 0 0 1 0 1 1

table. So, we may write1Y = (A.B.C).(A.B.C) . 0 1 0 1 0 1 Y = (A.B.C).(A.BC).(A.B.C)
and
INACTIVE
=
0 1 1 1 0 1 0 1 0 0 1 1 1(A.B.C). The decoder 74138 produces all active1 0 1 1 1 1low outputs so that the above logic equations for Y1, Y0 and INACTIVE can be implemented using 1 1 0 1 1 1 the suitable outputs of the decoder as shown in 1 1 1 1 1 1 Fig. 8.36(a).Table 8.23

(c) The encoder circuit is designed using the partitioning method of the truth table Table 8.23. With the help of dual 4-to-1 MUX, the two outputs 1Y and 2Y of MUXs by using
Fig. 8.36 (a) Fig. 8.36 (b)
suitable logic inputs to the MUX. The inactive output can be obtained using an OR gate with inputs Y1 and Y0. The logic circuit is shown in Fig. 8.36 (b).
(d) The design with the decoder needs two AND gates at the output and the design with multiplexer needs only one OR gate at the output.
8.7.4 : Commercially Available Priority Encoder
Table 8.24 shown a list of a few commercially availablew priority encoder IC Chips along with the btief input/output features.
IC Chip No. of Pins Technology No.
74417 16 Std TTL, LS, HC
74148 16 Std TTL, LS, HC
74348 16 LS
Functional It has nine-active low inputs representing the nine decimal digits 1 to 9 and produces the inverted BCD code corresponding to the highest-numbered activated input.

It has eight activelow inputs, one activelow enable input, three encoded inverted octal code corresponding to the highest numbered activated input. It has one activelow enable output and activelow group select output.

Similar to 74148 but the outputs are tristated.
Table 8.24 : Commercially available priority encoders
1. A 4:1 Multiplexer is used to implement a 3 input Boolean function as shown in figure below. The Boolean function F(A, B, C) implemented is [GATE 2006]
(a) F(A, B, C) = ☐(1,2,4,6);
(b) F(A, B, C) = ☐(1,2,6); (c) F(A, B, C) = ☐(2,4,5,6); (d) F(A, B, C) = ☐(1,5,6).

2. A 3 line to 8 line decoder with active low outputs is used to implement a 3 variable Boolean function as shown. The simplified form of Boolean function F(A, B, C) implemented in POS form will be [GATE 2008]

(a) (X + Z)(X + Y + Z)(Y + Z);
(b) (X + Z)(X +Y +Z)(Y + Z)
(c) (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z)
(d) (X + Y +Z)(X + Y + Z)(X + Y+ Z)(X + Y + Z) 3. The output of a two bit comparator is logic 1 whenever the 2-bit input A is greater than 2-bit input B. The number of combination for which the output is logic 1 is [GATE 2012] (a) 4; (b) 6; (c) 8; (d) 10

4. Consider the 4 to 1 MUX with two select lines S1 and S2 given below. The minimal SOP form of Boolean expression for the output F of the multiplexer is

[GATE 2014]

(a) PQ + QR + PQR; (b) PQ + PQR + PQR + PQR; (c) PQR + PQR + QR + PQR; (d) PQR
5. In given combinational logic, X is given by [ISRO 2016]
(a) X = ABC + ABC + ABC + ABC; (b) X = ABC + ABC + ABC + ABC; (c) X = AB + BC + CA; (d) X = AB + BC + CA.
6. In the following circuit, Y can be expressed as [ISRO 2014]
(a) Y = BC + A; (b) Y = C; (c) Y = AC + BC; (d) Y = B
7. For the multiplexer shown in figure, the Boolean expression for the output Y is [DRDO 2008]
(a) AB + BC + AC;
(b) AB + BC + AC; (c) AB + BC + AC; (d) AB + BC + AC;
8. Following circuit implements a [ISRO 2017]
(a) De-Multiploexer; (b) Multiplexer; (c) Y = Io(Ao + A1); (d) Y = Io(Ao + A1)
9. The minimum number of 2:1 MUX required to realize a 4:1 MUX is [GATE 2004]
(a) 1; (b) 2; (C) 3; (d) 4

10. The following multiplexer have I0, I1, I2, I3 are four data input lines selected by two address line combinations A1Ao = 00, 01, 10, 11 respectively and f is the output of the multiplexer. EN is the enable input. The function f(X, Y, Z) implemented by the circuit is [GATE 2002]

(a) XYZ; (b) XY + Z; (c) X + Y; (d) None of these.
11. The output F of the following multiplexer circuit is [GATE 2011]
(a) F = AND (P,Q); (b) F = OR (P,Q); (c) F = XNOR (P,Q); (d) F = XOR (P, Q)
9.1 BASIC MEMORY DEVICES - LATCHES AND FLIPFLOPS

In the earlier section we have seen that memory devices are required in the sequential logiccircuits. It was also mentioned that the memory devices may be of clocked or unclocked-type. In this section we shall see the different types of basic memory devices and their circuits. The basic memory devices may be of two types – Latches and FlipFlops. Either of the two memory device can store a single binary bit i.e. 1 or 0 in it and can be cascaded to form a memory of larger storing capacity can be designed. Commercially such basic memory units are available in the form of IC chips.

9.2 LATCH

It is an asynchronous sequential logic circuit which can store either of the two binary information – Logic-1 or Logic-0 under the control or some other suitable external inputs. Once a bit is stored in it, it will store this forever until we try to change it by some external controlling input or if the power supply for the memory unit goes off. The controlling input or the inputs of the latches may be level or pulse sensitive and the latches do not use any synchronizing clock for storing a bit or changing the stored bit.

Usually for a latch there are two external inputs – one for SETTING and the other for RESETTING the output. Setting and Resetting means to store a Logic-1 and Logic-0 respectively. Hence, the two inputs are called S ET or RESET inputs. These two controlling inputs may be either active High or activeLow. For a latch there are two outputs and these outputs are complementary in nature. The universal label for these outputs are Q and Q .

265
S Q
R
Q
(a)
QS
R
Q

(b) Fig. 9.1 : Graphic Symbols of the S-R latches (a) Latch with activehigh inputs (b) Latch with activelow inputs S-R-Latch : This latch is so called because of its two inputs – S (SET) and R (RESET). The graphic symbols for the S-R latch are shown in Fig. 9.1. Fig.9.1(a) and Fig. 9.1(b) are for SRlatches with activehigh and activelow inputs respectively. The input/output behavior of these two types of S-R latches are described below.

(a) S-R latch with activehigh S and R inputs
(i) To set the output of this type of latch (in short the action is called “SETTING A LATCH”) i.e. to make the output Q = 1 or Q= 0 the Set (S) input should be active i.e. High. To make Q=1 or Q= 0, the S-R-inputs of the activehigh S-R latch should be S =1, R= 0
This mode of operation in called Set Mode.
(ii) To reset the output of this type of latch (in short the action is called “Resetting a latch”) i.e. to make Q =0 or Q=1, the Reset (R)-input should be active i.e. high.

To make Q=0 or Q= 1, the S-R-inputs of the activehigh SR latch should be R=1, S=0
This mode of operation is called Reset Mode.

(iii) For nochange of output i.e. no change in Q or Q the Set and Reset-input should be both inactive, i.e. both of them should be Low.
For nochange of Q or Q, the S-R-inputs of the activehigh SRlatch should be S=0, R=0
This mode of operation is called Hold mode or, Memory Mode or No Change Mode.

(iv) Simultaneous activehigh inputs to S and R for the activehigh SRlatch are not allowed because this will try to make both the outputs Q and Q high. (i.e. Q=1, Q= 1) simultaneously which contradicts the basic assumption that the outputs are complementary. Thus, The input S=R=1 is not allowed for the activehigh SRlatch. In other words the condition S.R.=0 or S.R☐1 should always be maintained for an activehigh SRlatch
In short, for an activehigh SRlatch the inputs S and R are normally in low state and requires a logic-high state either at the S or R-input to have required change at the outputs Q and Q .
(b) SR latch with activelow S and R-inputs
(i) To set the latch of this type we need to apply low input to S.

To make Q =1 or Q= 0, the S and R-input of the activelow SRlatch should be S = 0 and R =1
This mode of operation is called a Set Mode.

(ii) To reset the latch of this type we need to apply low-input to R. To make Q = 0 or Q =1, the S and R-input of the activelow SRlatch should be S =1 and R =0
This mode of operation is called a Reset Mode.
(iii) For a nochange at Q or Q outputs of the activelow SRlatch the S and R-inputs should be both High.
For nochange at the outputs for an activelow SRlatch the S and R inputs should be Highi.e., S =R = 1. This is calledHoldMode or NoChange Mode orMemoryMode.

(iv) Simultaneous low-inputs to S and R-inputs are forbidden because under this condition both Q and Q will be high simultaneously which is contradictory to our basic assumption that the two outputs of a latch should be complementary.

This inputs S =R=0 are not allowed for the activelow SRlatch. In other words the condition S.R = 0 should always be maintained for an activelow SRlatch. Inshort, for an activelow SRlatch the inputs are normally kept inhigh states and require a logiclow state either at S or at R -input to have required change of the output Q and Q .
9.2.1 Characteristic Table of SR Latch The table which describes the above statements in tabular form called the Characteristic Table or simply the Function Table of the SRlatch. Table 9.1 shows the characteristic table for activehigh and activelow SR latch. In this table Q(t) represents the output of the latch at time t before the application of any active inputs to S or R and Q(t+1) is the output of the latch at time (t +1) i.e. after the application of active-inputs to S or R. Q(t) and Q(t+1) are called the Present State and the Next State respectively. The change of state from Q(t)-to-Q(t+1) occurs under the influence of S and R-inputs after a propagation delay of the gates used in latch measured from the time of application of inputs to S and R.

Inputs Output Inputs Output R Q(t) Q(t+1) 0 0 – }Forbidden 0 1 – condition S R Q(t) Q(t+1) S
0 0 0 0}Nochange 0
0 0 1 1 Q(t+1)=Q(t) 0

0 1 0 0}Reset condition 0 0 1 1 0 Q(t+1)=0 0 1 0 0 1 }Set condition 1 1 0 1 1 Q(t+1) =1 1

1 1 0 –}Forbidden 1
1 1 1 – condition 1
1 0 1 }Set condition 1 1 1 Q(t+1) = 1

0 0 0}Reset condition 0 1 0 Q(t+1)=0

1 0 0 }Nochange
1 1 1 condition Q(t+1)=Q(t)

(a) Characteristic table of activehigh SRlatch (b) Characteristic table of activelow SRlatch Table 9.1
9.2.2 Gated SR-Latch From the discussions of the earlier section it is evident that the output of a crosscoupled NAND or NOR-latch changes whenever the SET or RESET inputs change their logic states. Sometimes it is desired that the change in the output of a latch should occur in synchronization with some external command. This idea can be implemented if some extra logic circuit called “Steering Circuit” is attached to the inputs of the basic crosscoupled NAND or NOR-latches.

Fig. 9.2(a) shows how two ANDgates can be connected to steer the inputs S and R to the SET and RESET input of the NOR-latch and one external synchronizing input, EN. This synchronizing input is also called the Enable Input. This enable input either blocks or allows the S and R inputs to reach the SET and RESET input of the basic NOR-latch. When EN=0, the NOR-latch receives X= 0 and Y= 0 as its SET and RESET inputs respectively. Therefore, this latch remains in the HOLD state or Nochange state for EN = 0. Under this condition the latch is unable to respond to the S and R-inputs. But, for EN=1 the latch receives S and R through the steering circuit to its SET/RESET inputs and hence the Q and Q outputs of this NOR-latch can change according to the function table which is shown is Table 9.2(a). For this circuit the input S=R=1 is not allowed when EN=1.

S S.EN = X SET
Q
EN
Q R
R.EN = Y RESET
Steering
SR latch with NOR gatesCircuit
Fig.9.2(a) : Gated SRlatch using NOR-latch
Inputs Outputs Q QEN S R SET(=X) RESET
0 ☐ ☐ 0 0 Nochange
1 0 0 0 0 Nochange
1 0 1 0 1 0 1
1 1 0 1 0 1 0
1 1 1 1 1 – – Table 9.2(a) : Function table of gated SR NOR-latch shown in Fig. 9.2(a).

Fig.9.2(b) shows gated NANDlatch. In this gated latch the steering circuit is designed with two NANDgates instead of using ANDgates. The steering circuit designed with two AND gates for the circuit with cross coupled NANDlatch would produce the Logic-0 at X and Y for EN=0. This becomes the forbidden input combination for a crosscoupled NANDlatch. The appropriate steering gates are therefore two NANDgates for an activehigh enable action. The function table of this gated NAND SR latch is shown in Table 9.2(b). Here also the condition S.R=0 should have to be maintained for EN=1 to avoid the forbidden inputs S=1, R=1.

S
S.EN=X Set
Q
EN
Q R
ResetR.EN=Y

Steering
Circuit

SRlatch with
Nor gates

Fig. 9.2(b) : Gated SRlatch using NANDlatch The circuit of the crosscoupled NOR-gate based gated SRlatch with enable-input can be obtained after finding the characteristic equation with the help of the characteristic table and K-map. For this purpose we assume that the enable input is active high. The chacteristic table is shown in Table 9.2(c). The logic equation for the next state Q(t+1) as a function of Set (S), Reset (R), Enable input (EN) and the present state Q(t) can be obtained from the K-map shown in Fig. 9.2(b). The input EN=S=R=1 is forbidden and therefore the Q(t) and Q(t+1) may be assumed to be don’t care.

Inputs Outputs EN S R SET(=X) RESET (=Y) Q Q 0 ☐ ☐ 1 1 Nochange 1 0 0 1 1 Nochange 1 0 1 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 – – Table 9.2(b) : Function table of gated SR-NAND-Latch

Inputs Present Next state state EN S R Q(t) Q(t + 1) 0 ☐ ☐ 0 0

0 ☐ ☐ 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 ☐ ☐

☐ = don’t care input
Table 9.2(c) : Characteristic table of a crosscoupled NOR-gate latch with activehigh enable input (EN).

R.Q(t)
10EN.S 00 01 11
00 0 1 1 0
01 0 1 1
0
11 1 1 ☐
☐
10 0 1 0 0
Map for Q(t + 1)
Fig.9.2(c) : K-map for Q(t+1) of Table 9.2(c)
From the K-map Fig. 9.2(c) we get the characteristic equation
Q(t+1) = EN.S + EN . Q(t) + R . Q(t)
= EN.S + ☐EN . R☐ Q(t). ... ... 9.1 The characteristic equation with activehigh set (S) and reset input (R) without enable input (EN) is
Q(t+1) = S + R . Q(t) ... ... 9.1(a) Comparing Eqn. 9.1 with Eqn. 9.1(a) we get
SET = S.EN
RESET = R.EN.

Therefore, the modified circuit for the cross coupled NOR-gate latch with activehigh nable input is as shown in Fig. 9.3.
F ig.9.3: Cross coupled NOR gate latch Fig. 9.4 : Cross couped NAND gate latch In the same way one can design S-R latch using cross coupled NAND gates as shown in Fig. 9.4.

Timing diagram of the gated latch of Fig. 9.4 is drawn in Fig. 9.5. From this figure it appears that upto time t = t4 from t = 0 the enable input EN=1 and output Q follows the Table 9.2(b). For t > t4, EN= 0, the latch circuit does not respond to any variations of S and R-inputs because both X and Y become 1 for EN=0 and Q remains unaltered. The logic state of this unaltered Q for t>t4 depends on the inputs S and R just at t= t4. when the enable input changes from EN=1 to EN=0. The time t=t4 is called the latching point. In otherwords we may say that the values of S and R at latching time t4 (when enable input changes from EN=1 to 0) will decide the actual latched value of Q after tn. Thus, we have two possible distinct modes of operation of a latch. (i) Transparent mode (for time t=0 to t4 when the latch remains enabled) (ii) Latch mode (for time t > t4 when the latch goes from enabled to disabled state). For the latching action to become effective the enable line should go from high-to-low for an activehigh enable input.

1

EN

0
t 1 0t4
S

0
t 10
R

0

t 0

Q
t0 t1
t2 t3 t4
The latch is transparant Q unaltered as EN-1 as EN=0 F ig. 9.5
S Q S Q
EN EN EN EN
R
QR Q
(a) SRlatch with activelow enable input
(b) SRlatch with activehigh latch enable input
Fig. 9.6 : Graphic Symbols of the SRlatches

Fig.9.6 shows two graphic symbols of SRlatches. In Fig.9.6(a), the bubble symbol at the enable input means that the latch will remain transparent when EN = 0 and will go to the latch mode when the enable input makes a transition from 0-to-1. The enable input of Fig. 9.6(b) is without bubble. This means that this SRlatch remains transparent so long as EN=1 and enters the latch mode when EN input makes a transition from 1-to-0.

1

EN

0
1

S

0

1

R

0

1

Q

0
T T T T
Fig.9.7 : Enable input used as a synchronizing signal.

Fig. 9.7 shows the action of periodically pulsed enable-input to a SRlatch with activehigh enable-input. The previously latched value of Q changes as a fuction of S and R when the enable-input EN becoms active (i.e. goes from 0 to 1) because of the transparentmode. This is shown with upward arrow of the enable line. The actual latching of a new value of Q is latched in the SRlatch when the EN-input goes from 1-to-0 i.e. when the SRlatch enters the latchmode. This is shown by the downward arrows in Fig. 9.7. As the enable input is applied periodically so any change in the output Q occurs only at fixed intervals. Thus the Q-output is synchronized with the enable-input. The output may go out of synchronization if S or R changes when enable is high. This happens during the second transition (1☐0) of the enable-input.

9.2.3 SRlatch with Preset and Clear

In a simple SRlatch or in a gated SRlatch, the initial-output (Q or Q) of the latch could not be predicted when power supply is made ON to the latch-circuit. The initial logicstate of Q may be either in set (Q=1) or reset (Q=0). But in many applications it is desirable that the initial state of Q should start either from set or reset state depending on the demand of the other circuit to which this latch is connected. This initial Q output is fixed by the users with the help of some additional control-inputs regardless of the S,R and the enable-inputs, EN. The control-input by which we can set (Q = 1, Q= 0) the

latch is called the PRESET OR DIRECT SET-input and the control input by which we can RESET (Q = 0, Q=1) the latch is called CLEAR or DIRECT RESET-input. These two inputs are asynchronous in nature because the setting or resetting does not occur in synchronization with the other inputs of the latch. One possible circuit of a gated SRlatch with one preset (PRE in short) and clear (CLR is short) is shown in Fig.9.8(a). The function table for the circuit is shown in Table 9.3. From this table we may observe that— (i) The circuit behaves as a normal gated NAND SRlatch if PRE = CLR = 1 and enable (or clock) input is High (see the rows of Block IV of the Table 9.3). (ii) Using PRE and CLR inputs the latch can be forcibly set or reset overriding the set (S) or reset (R) inputs of the latch when the enable input (or clock) is low. These inputs are—
(a) PRE = 0, CLR = 1 for setting (Q = 1, Q = 0)
(b) PRE = 1, CLR = 0 for resetting (Q = 0, Q = 1)
These two modes are popularly called “PRESET” and “CLEAR” mode as indicated in two rows of Block–V of Table 9.3.

(iii) The preset and clear inputs can’t be low at the same time because it gives Q = 1, and Q=1 which is contradictory with respect to the complementary nature of output of the latch (see the rows of Block-I of the Table 9.3).

(iv) The low preset or clear inputs give erroneous output if they are used when the enable input is High. See rows of Block-II and III of Table 9.3.
Preset (PRE)PRE
CLR S
1 A S EN3
Q PRE S S.EN Q Enable (EN)
S S QEnable

Enable
or

Clock

oror

ClockEN
Q R
2
☐
B R.EN Q CLR Q Clock
4 R R R R.EN PRE Clear (CLR)
CLR
(a) (b) (c) Fig.9.8(a) : Gated SRlatch with activelow preset and clear inputs (b) Graphic symbol of the SRlatch with activelow preset and clear input (c) Modified circuit of Fig.9.7(a) with complete override of asynchronous activelow preset and clear inputs.

Input Enable (EN) PRE CLR or Clock
I X 0 0

0 1
1 0 1
II 0 1
0 1

1 0
III 1 1 0
1 0
1 0

1 1
IV 1 1 1
1 1
1 1

V 0 1 0 0 1
Output Comment S R Q(t+1) Q t☐ 1)
X X 1 1 Not used 0 0 1 0 Does not give
0 1 1 1 normal latch
1 0 1 0 output as
1 1 1 1 Q(t+1) and

0 0 0 1 Q t☐1)
0 1 0 1 are not always
1 0 1 1 complementary
1 1 1 1

0 0 Q(t) Q t( ) Normal output
0 1 0 1 similar to gated
1 0 1 0 NANDgate SR
1 1 – – Latch

X X 0 1 Clear Mode X X 1 0 Preset Mode

Table 9.3 : Function table of the circuit of Fig.9.8(a)
(v) The action of the preset (PRE) or the clear (CLR) input becomes proper if a logiclow signal is applied to them when EN-input is low (see Block-V). For this circuit both the preset and clear inputs are activelow. The graphic symbol of this circuit is shown in Fig. 9.8(b) where the bubble signs indicate the activelow inputs for the preset and clear.

From the above discussions it appears that for the circuit of Fig. 9.8(a) the preset and clear inputs do not function properly when the enable input is high. To have the complete overriding power of the preset and clear inputs regardless of the enable (or clock), S and R-inputs, the above circuit should be modified. One modification is shown in Fig. 9.8(c). In this circuit two extra 2-input ANDgates are used in the feedback path. The preset and clear inputs are attached to the ANDgates but their positions are interchanged. In this circuit the preset and clear-inputs are completely asynchronous in nature because these inputs can be made active at anytime and the action of the preset and clear completely overrides the inputs S,R and EN.

9.3 FLIP FLOPS

The last section was devoted to the latches, where we noted that the latches could not be synchronized with other parts of a logic circuit or system. Therefore, those devices are

not suitable memory element for using in a synchronous sequential logic circuit where we need to operate the memory elements in pace with some external timing signal. These timing-signals may be periodic or aperiodic. The periodic timing-signal is known as the “Clock”. The clock (CLK), as the name implies, is usually thought of as a regular, rectangular, logic waveform having specific duty cycle, however, regularity need not be an essential requirement. The clock pulses may be quite irregular.

1
0
TCLK
(a)
1
0
(b)
Fig.9.9: Periodic pulse or clocks (b) Aperiodic pulses The waveform of clocks are shown in Fig.9.9. In this figure the edges of the waveform are shown with the arrowheads. The edge with upward arrowhead (☐) is called the rising edge of the waveform. It shows a sharp transition of the waveform from Logic0 to Logic-1. Similarly, the edges marked with the downward arrowheads (☐) are called the falling edges. The falling edges indicate a sharp change of logic-levels from 1-to-0. The flipflop is a memory element whose change of states (change in Q) occur at the instant of the appearance of the clock edges. The change of states may occur at the rising edge or at the falling edge. Thus, a flipflop is basically an edge-sensitive latch.

9.3.1 Type of FlipFlops

The classification of flipflops can be done in two ways depending on (a) the clocking mechanisms and (b) the types of control-inputs of the flipflop. Based on the clocking mechanism of the flipflop (clocking of a flipflop is also commonly called triggering) we can have 4 types of flipflops—(i) Pulse Triggered FlipFlop, (ii) Master-Slave FlipFlop, (iii) Edge Triggered FlipFlop, (iv) Data lock-out FlipFlop and based on the control inputs used for setting and resetting purpose we can have 4 types of flipflops—(i) SR FlipFlop (ii) JK FlipFlop (iii) T FlipFlop (iv) D-Flip-Flop.

9.3.2 Pulse Triggered FlipFlop In case of pulse triggering, narrow pulses are used to get a change of state at Q or Q . These pulses may be periodic or aperiodic as shown in Fig. 9.9. The circuit of the pulse triggered flipflop is exactly similar to the gated latch and the pulses can be applied either to activehigh or activelow enable input (enable inputs were discussed in the earlier section) of the latch. Thus, these type of flipflops may be positive-pulse flipflop, latching A B C D
SET Q
CLK RESET Q
(a) Positive pulse triggered flipflop
SET Q
CLK A’ B’ C’ D’
RESET Q (b) Negative pulse triggered flipflop Fig. 9.10 Pulse Triggered FlipFlop occurs at the falling edge of the input pulse but remains transparent during the high time of the pulse and remains disabled during the low time. Similarly, for negative-pulse flipflop the latching occurs at the rising edge of the pulse and remains transparent during the low time of the pulse. The graphic symbols of the pulse triggered flipflops and the corresponding clocks are shown is Fig. 9.10. The instants of latching are shown by the arrowheads in the clock signal in Fig. 9.10 It may be noted that the negative-pulse triggered flipflop has a bubble symbol at the clock input. This bubble indicates that the flipflop’s SET/RESET inputs become active when the pulses are low. Similarly, the clock input without the bubble means that the setting or resetting can be done when clock goes high.

9.3.3 Master-Slave FlipFlop

The master-slave flipflop (MSFF) uses both the rising edge and the immediately next falling-edge of a pulse for a state (Q output) to change in the flipflop. This MSFF was an early attempt to lock-out the unwanted oscillations in the simple JK-latch. In the MSFF two gated latches are used with one inverter in between the two enable inputs of the latches so that two latches cannot be enabled simultaneously. The logic diagram of a SRMSFF designed using two SRlatches is shown in Fig. 9.11. Out of the two SR latches, the latch which receives its SET/RESET inputs (SM and RM) from an external source is called the Master latch and the latch which receives its SET/RESET inputs from the QM/ QM-outputs of the master is called the Slave latch.

Master Slave
LatchQ Latch
M S QQS S Q

SM S Q
InputCLK

ClockEN
EN
R Q QM R Q QS CLKRM
t0 t1 t2
Q R
t0t1t2
Fig.9.11:
Master-Slave SR flipflop
Fig.9.12 : Master-Slave SR flipflop sensitive positive pulse During the high time (t0 to t1) of the input clock as shown in Fig. 9.11 the master latch becomes active but not the slave and the situation gets reversed when the input clock becomes low i.e. during the time t1 to t2 of the input clock. So, the output of the master latch (QM or QM )
SM S

Q QM S Q responds to the inputs, SM and

RM so long as the clock remains

EN EN high (t0-to-t1). It behaves as a

Q M R Q QS transparent latch for this time RM R Qt1 t2

duration and the logic value of

Q will be latched at QM at the

instant the clock changes state

from high-to-low at t1. After t1

any variation at SM and RM will

t0 t1 t2 not affect QM further. As the Input clock clock becomes low at t1 and
remains low up to t2; so the(a) slave becomes active for this
S

Q period of time (t1 to t2) and the

previously latched master ’s CLK output at QM and QM are

transferred to QS and QS . This R transfer occurs at after t1 i.e. at (b) the falling edge of the input clock Fig. 9.13(a) : Negative pulse triggered master-slave SR-flip-flop.(or at the rising edge of the (b) Graphic symbol. inverted clock). Though the slavelatch remains enabled during the time t1-to-t2 of the input-clock, QS or QS will not be disturbed due to any variation at SM and RM because, these variations are locked-out by the disabled master

latch for this time duration. From this discussion we may conclude that for a complete flipflop action a complete positive pulse (i.e. a time from t0 to t1) is required. Rising edge of the pulse is used by the Master and the falling edge of the same is used by the slave.

The symbol for the master/slave SR-flip-flop is shown in Fig. 9.12. Note that there is a postponed symbol ( ) at the Q-outputs. This postponed symbol indicates that the slave output does not change until the falling edge of the positive input pulse comes at the input of the master.

The master-slave SR-flip-flop can also be designed where the master latch is active during the low time of the clock and the slavelatch becomes active at the rising edge of the clock. The logic circuit of this type of flipflop and its graphic symbol are shown in Fig. 9.13(a) and (b) respectively. Note the bubble symbol at the clock input of this type of flipflop.

9.3.3.1 Master-Slave JK-Flip-Flop

The master-slave JK flipflop (MSJK) can be configured by using two gated SRlatches whose enable inputs are connected by an inverter as shown in Fig. 9.14(a). The master and slave SRlatches are shown as dotted. The feedback connection is established from QS and QS -outputs of the slave SRlatch to the inputs of the NANDgates 3 and 1 of the master SR latch. The graphic symbol MSJK is shown in Fig.9.14(b). It is evident from the circuit that two latches cannot be active simultaneously because of the inverter J
Q
1 2M
Q 5 7 QS CLK
Master Slave
SR Latch SR Latch
3 4 6 8K QM
QS Q
t0 t1 t2
(a) t0t1t2
J
Q
CLK
K
Q
(b)
Fig. 9.14( a) Fig. 9.14( b) between two enable inputs of the SRlatches. The master latch output QM and QM will be updated depending on the inputs to J and K at time t0 i.e. at the positive going edge of the clock and are held constant if we assume that there is no variation of J and K so long clock input at the master remains high (time t0 to t1). After the time t1 the slavelatch becomes enabled and the latched output of the master will be passed to the slave output at QS and QS . If the J and K inputs did change during the high clock level (time t0 to t1) the master latch would respond to that variation and the final result at the output of slave would depend upon the inputs of J and K at the time of falling edge clock at t = t1. These are called the phenomena of 1’s catching and 0’s catching in master-slave

JK flipflop. This is one

PRE drawback of the circuit.

Q MAnother disadvantage is JQSthat to get the Q-outputs at the slave output we needCLK
a complete pulse.
The main advantage ofK
QS

this master-slave JK flipflopQM

over the simple JK-latch is

that there will be noCLR

oscillations at QS or QS

even if the enable input Fig.9.15: Master Slave JK-flip-flop with preset and clear inputs (activelow)remain, high by the clock pulse for a long time with J=K=1. This oscillation is prevented because the master latch will toggle once if J=K=1 and clock pulse high but this toggled output of the master will not be fed back to master’s input so long as the clock input remains high because the feedback path can’t be completed by the disabled slave during the clock high time.

As described in case of master-slave SR flipflop, the circuit for Master-Slave JK flipflop can also be constructed sensitive to negative pulse. This can be done simply by driving the slavelatch directly by the clock and the master latch by the inverted clock.

The action of the preset and clear can be added to the MSJK as shown in the Fig. 9.15. The preset and clear inputs are both activelow type.
The function table of the positive pulse sensitive master-slave JK flipflop is shown in Table 9.4.

Inputs Outputs Comment
J K CLK Q(t + 1) Q (t +1)

0 0 Q(t) Q(t) ☐ Nochange of Hold-mode
0 1 0 1 ☐ Reset-mode
1 0 1 0 ☐ Set-mode
1 1 Q t( ) Q(t) ☐ Toggle-mode TABLE 9.4 : Function table of positive pulse triggered master-slave JK-flip-flop.
9.3.3.2 Effect of Glitches in Master-Slave JK FlipFlop From the dicussions of the master-slave JK-Flip-Flop it is evident that the master-latch becomes transparent when it is enabled. During this time the master is sensitive to the noisy positive glitches appearing either to J or K-input, but the slave-unit remains unaffected.

The effect of the glitches is explained using the Fig. 9.16. From the Fig. 9.16(a) it may be seen that if the glitch was absent at time t = t2 then the output QM of the master latch

would have been 0 throughout the clock time and as a consequence the final output of the JK-flip-flop i.e. the output of the slave latch would have been 0. But the presence of the glitch at t= t2 on J-input set QM irreversibly and this set-value of QM is transferred to QS at t = t3. This undesired change of Q from 0-to-1 due to this glitch is called 1’s catching.

CLK1
0
glitch J 1
0

K1

Q
0

1
M0
Q=S1
0 t0t1 t2 t3
CLK0
11

J

0 glitch1

K
0

1

Q=Q
QM 0
1
S 0

t0t1 t2 t3
Fig. 9.16( a) Fig. 9.16( b) Similarly, is Fig. 9.16(b) it is seen that the presence of a positive glitch at K-input at time t= t2 forces QM to 0 and this value of QM is transferred to QS at t = t3. But without the glitch at K. The QM would remain 1 upto t = t3 and hence the final output of the JK flipflop would be 1. This undesired change of Q from 1 to 0 due to this glitch is called 0’s catching.

The 1’s catching and 0’s catching can be eliminated or the probability can be reduced if the clock pulse width can be made very narrow.
9.3.4 Edge Triggered FlipFlops All the pulse triggered flipflops discussed in the earlier section require a complete pulse for latching operation because with the rising edge of the pulse the master is loaded and the output of the master is then transferred to the slave at the falling edge of the pulse. The requirement of the two edges of the pulse triggered flipflop the inputs (R, S, J or K) must remain constant while the pulse is high otherwise some undesired and unpredictable data may be loaded at the output of the master due to the catching of noisy glitches during the high time of the pulse.

The above drawbacks can be removed if we can design a flipflop which responds only to the single edge of the input pulse i.e. either at the falling or at the rising edge of the pulse. These type of flipflops are called the “Edge Triggered FlipFlop”. Thus, the edge triggered flipflops are faster and the influence of the glitches on inputs can be drastically reduced.

The edgetriggered flipflops are so designed that they works on the edges of the input pulses or clock i.e. at the instant of rising or falling transitions of the input pulse or the clock. A transition is a change in state of the clock from one logic-level to another. The rising or the positive-transition is a change from Logic-0 to Logic-1 as shown in Fig. 9.17(a) and the falling or the negativetransition is a change from Logic-1 to Logic0 as shown in Fig. 9.17(b). These changes are shown with arrowhead.

J QJ Q
CLK
CLK
K QK Q
D Q
D Q
CLK CLK
Q
Q (b)(a) Fig.9.18 : Graphic symbols of JK and D-type edgetriggered filp-flop (a) Positive-edge triggered (b) Negative-edge triggered.

1
1
0
0
1
1
0 (a)0 (b) Fig. 9.17 : Clock transitions used in edgetriggered flipflop. (a) Rising or positive-transition (b) Falling or negativetransition The edgetriggered flipflop may be designed by using a pulse edge detecting or a pulse narrowing circuit followed by a simple SET/RESET latch. This extra edge-detecting circuit in front of the latch detects either the rising edge or the falling edge of the input clock pulse and allows the latch to go either to SET or to RESET state only at the pulse edge and keeps the latch in the Hold or Nochange mode either before or after the edge. It means that there will be no change at the output of the flipflop if there is no transition in the clock signal. Two following types of flipflops are available depending on the method of triggering the clock input of the flipflop. (i) positive-edge triggered, if the flipflops are sensitive to the rising edge of the clock (ii) negative-edge triggered, if the flipflops are sensitive to the falling edge of clock.

Edgetriggered flipflops have the same box-type graphic symbol as used for latches but with an important difference to indicate the two clocking modes. One arrowhead
-symbol at the clock input is used for indicating positive edgetriggering and a bubble before this arrowhead at the clock input is used for showing negative edge triggering of flipflops. The graphic symbols for the two types of edgetriggered flipflops are shown in Fig. 9.18(a) and (b) respectively. The clocking-modes can be changed from one type to the other by using one inverter at the clock input.

Four different types of flipflops can be introduced—the SR, the JK, the D and T but there is no commercial implementation of T-type flipflop. In this section, the discussion will be made for the JK and D-type edgetriggered flipflop because these two types of flipflops are commercially available with different added features. Conversion of one type of flipflop to another can easily be done. Also, these two flipflops can be converted to T flipflop.

9.4 T FLIPFLOP
Another common flipflop used in sequential logic circuit that counts pulses using single input line is the T-flip-flop where T stands for toggle or trigger. Though the
1 Vcc1
R
PREQ
PREQ J
T CLK
T CLK Q
QCLR K CLR
1
1 (i) (a)(ii) 1
1
TPRE QT J PRE Q
CLK
CLK
Q
K Q CLR
CLR
11
(i)(b) (ii) Fig. 9.19(a) : Negative edge triggered T-flip (i) Logic-Symbol (ii) Functional equivalent circuit using JK flipflop.
Fig. 9.19(b) : Gated T flipflop (i) Logic-symbol (ii) Functional equivalent circuit using JK flipflop T-flip-flops are not commercially available in the form of an IC-chips but this T-flip-flop can be designed using JK flipflop as shown in Fig. 9.19(a), (b) and (c). The T-flip-flops shown in Fig. 9.19(a) and (c) are called edgetriggered and that in Fig. 9.19(b) is called gated T-type flipflop. The characteristic equation for the two types of flip flops can be derived from the characteristic equation of JK flipflop as follows : Q(t + 1) = J.Q t( ) + K .Q(t)
= Q t( ) ; for J = K = 1 as in Fig.9.19(b)

Q(t + 1) = JQ(t) + KQ(t) = TQ(t) + TQ(t)
= T ☐ Q(t) for the Fig.10.67(b)

Thus, for T = 0, Q(t+1) = Q(t), nochange = Q t( ) , Toggling.
Thus, the T-input in gated T-flip flop Fig. 9.19(b) may be treated as the enable input for toggling.

Q(t + 1) = J. Q t( ) + K Q(t)
= Q t( ) . Q t( ) + Q t( ) . Q(t)
= Q t( ) ; for J = Q t( ) and K=Q(t) as in Fig.9.19(c) 1
1
PRE
Q
J PRE Q
T CLK
T CLK
K QQ
CLRCLR
1
1 (i) (ii) Fig.9.19(c) : Negative edgetriggered T-flip-flop (i) Logic-symbol (ii) Functional equivalent-circuit using JK flipflop The edgetriggered T-flip-flop has only one excitation input labelled as T. This is the clock input of the JK flipflop. The output Q-toggles at each falling edge of the clock applied to this T-input. The edge triggered T flipflop are widely used in the digitial logiccircuits for counting purpose. The function table, the excitation table and the timing diagram are shown in Table 9.5(a), (b) and in Fig.9.20 and Fig. 9.21 respectively.

Clock Input Q(t+1) Comment Required Change T input Comment (T) Q(t) ☐ Q(t+1)
☐ Q t( ) Toggle 0 ☐1 ☐ Toggle 1☐0 ☐ Toggle
Table 9.5(a) Function table of an Table 9.5(b) : Transition table of an edgetriggered T-flip-flop [Fig.10.67(a)] edgetriggered T-flip-flop [Fig.10.67(a)]
T
CLK
T
Q
Q
Fig. 9.20 : Timing diagram of an Fig. 9.21 : Timing diagram of edge triggered T flipflop. a gated T flipflop.[Fig.10.34(b)].

In case of gated T-flip-flop the clock input is excited using external clock as usual but the T-input is separate. The purpose of the T-input is to enable or disable the triggering action of the clock. When T = 0 this T-flip-flop remains in the hold state i.e. Q does not

change and for T = 1 this T-flip-flop acts as a normal T-flip-flop. The function table, the excitation table and the timing diagram are shown in TABLE 9.6(a), (b) respectively.

Input Clock Q(t+1) Comment (T) (CLK)

1 ☐ Q t( ) Toggle Mode
0 x Q(t) Hold Mode

TABLE 9.6(a) : Function table of a gated T-flip-flop
Required Change Input Comment Q(t) ☐ Q(t+1) T CLK

0 ☐1 1 ☐ Toggle
1☐0 1 ☐ Mode
0☐0 0 X Hold
1☐1 0 X Mode

TABLE 9.6(b) : Transition table of a gated T-flip-flop

An edgetriggered T-flip-flop can be converted to a gated T-flip-flop. The circuit for this conversion is shown in Fig. 9.22. In this circuit the input T=1 allows the clock pulses to pass to the clock input and when T = 0, the clocks are inhibited.

1 11
PREQ D PRE QT DPRE Q
T CLK T CLKCLKCLK
CLR
Q Q CLRQ CLR
1
11
F ig. 9.22: Fig. 9.23 : D flipflop Fig. 9.24 : D flipflop converted gated T.flipflop converted into T-flip-flop into a gated T-flip-flop.

A D-flip-flop can also be converted into a T-flip-flop. The characteristic-equation of a D-flip-flop is Q(t + 1) = D. If D is equal to Q t( ) then we get Q(t+1) = D = Q t( ) , which is the characteristic equation of a T-flip-flop. Therefore, by connecting the Q t( ) output of a D-flip-flop to its D-input we can get a T-flip-flop. This is shown in Fig.9.23.

Another way of converting a D-flip-flop into a gated T-flip-flop is to use the circuit shown in Fig.9.24 This interconnection can be predicted if we use the characteristic equations of D and T type flipflops. Q(t+1) = D ; characteristic equation of D-flip-flop and Q(t+1) = Q t( ) ; characteristic equation of T-flip-flop. If the D-input of a D-flip-flop is such that D=T ☐ Q(t) then for T=1, D=1☐Q(t) = Q t( ) and for T = 0, D = 0 ☐ Q(t) = Q(t). So, using EX-OR gate at the D input as in Fig.9.24 we can design a gated T flipflop.

Most important feature of the T-flip-flop is that it devides the rate of the input clock by 2 with T = 1 for a clock triggered T-flip-flop and the externalclock is connected to the T input for an edge triggered T-flip-flop.

9.5 D-Latch

In many applications of the digital circuits the two inputs for setting and resetting are not preferable for storing a single bit 1 or 0 at the Q-output of a latch and instead a single input is required for inputting data to a latch and to store a data bit in it. Keeping this requirement in mind a new type of latch has been developed having a single data input, called Data Latch or in short D-Latch. The characteristic table of the D-latch without any enable line is shown in Table 9.7. A 2-variable K-map for Q(t+1) is shown in Fig. 9.25 (a). This K-map gives us the equation relating the next state Q(t+1) and the data-input D of the data latch.

Q(t+1) = D 9.2(a)

Input Present Next

D State State

Q(t) Q(t+1)

0 0 0

0 1 0

1 0 1

1 1 1

Table 9.7 : Characteristic table Fig. 9.25 (a) : K-map of Fig. 9.25 (b) : SR latch of a D-Latch Q(t+1) of Table 9.7 converted to a D-latch One SRlatch can be converted to a D-latch using the characteristic equation of SRlatch. The characteristic equation of the SRlatch with activehigh S and R inputs using NANDgates and with NOR-gates without enable-input (EN) is Q(t+1) = S + R .Q(t) 9.2(b) If we substitute S = D and R = D in this equation then this equation becomes
Q(t+1) = D + D .Q(t) = D 9.2(b) which is the characteristic equation of the D-latch. Thus, one SRlatch shown in Fig. 9.25(b) and Fig. 9.8(b) can ve converted to a D-latch as shown in Fig. 9.25(c) and Fig. 9.25(d).

Fig. 9.25 (c) : D-latch using all NANDgates

Gated D-Latch
The gated SRlatch can be convereted to a gated D-latch as follows : The characteristic equation of a SRlatch with activehigh S,R and enable input (EN) is Q(t + 1) = EN. S + (EN .R) Q(t)

If we substitute D and D for S and R in this equation for Q(t+1) then the get

Q(t + 1) = EN.D + (EN. D) . Q(t) 9.3

= EN.D + EN .Q(t)+D.Q(t) 9.3(a)

= EN.D + EN .Q(t) 9.3(b)

If wThe Eqn. 9.9(b) becomes
Fig. 9.25 (d) : D-latch using allQ(t+1) = D for EN = 1 NOR-gates= Characteristic equation of D-Latch
and Q(t+1) = Q(t) for EN = 0
Fig. 9.25 (e) : Gated D-latch using crosscoupled NANDlatch
= Equation for the memory mode.
The Eqn. 9.3 can be implemented as follows either using NAND or NOR latch.

The gated D-latch using cross

coupled NANDgates can be

simplified further as follows :

From Fig. 9.25 (e)

Y = D. EN

= D + EN

= D.EN + EN

= X + EN; where X = D.EN

= X.ENFig. 9.25 (f) : Gated D-latch using crosscoupled NOR-latchThus, the circuit in Fig. 9.25(e) can be redrawn in a more simplified way as shown in Fig. The graphic symbol for the gated D-latch is shown in Fig. 10.18(h)
Fig. 9.25 (g) : Gated D-latch is shown in Fig. 9.25 (h) : Graphic symbols for the gated Fig. 9.25(h) D-Latch
The characteristic table and the excitation table for the gated D-latch are shown in Table 9.8(a) and Table 9.8(b).
Enable Input Present Next Comment Required change Required change EN D State State to Q(t) Q(t+1) Q(t) Q(t+1) EN D

0 ☐ 0 0 Nochange0 0 1 0
or
0 ☐ 1 1 Memorymode0 1 1 1
1 0 0 0 Reset
1 0 1 0 mode1 0 1 0
1 1 0 1 Set
1 1 1 1 mode1 1 1 1

Table 9.8 (a) : Characteristic table of a gated D-latch with Table 9.8 (b) : Excitation-table of a gated activehigh enable input D-latch with activehigh enable input.
The characteristic equations for a gated D-latch with activehigh enable-input are Q(t+1) = D for EN = 1
= Q(t) for EN = 0

Indicate two modes of operations (i) Transparent Mode, and
(ii) Latch Mode.
The equation Q(t+1) = D for EN = 1 indicates that the next state at Q i.e. Q)t+1) follows the logic state of D-input so long the latch is enabled. This mode of the latch is called the Transparent mode of the latch. This mode is so called because under enabled condition the path between D and Q as if remains transparent and any variation occurs at D-input becomes the variation at Q.
The equation Q(t+1) = Q(t) for EN=0 is called Latch mode or Memory Mode for a gated D-latch with activehigh enable input. The gated latch enters the latchmode from the transparent mode at the moment whenever the latch is diabled from the enable condition.

Under the latched conditionn the Q-output becomes fixed to the logic value which is detected by the latch at the moment when the latch is disabled from the enabled state. The transparent and the latchmode are depicted in the Fig. 9.25(i) and 9.25(j) for the gated D-latch with activehigh and active low enable inputs respectively along with the graphic symbol for latch and timing diagram.

Fig. 9.25(i) : Transparent and latch mode for a gated D-latch with activehigh enable input In Fig. 9.5(i), the transparent condition (EN = 1) is valid for the time duration t2-t1 because the enable-input is activehigh (shown in the graphic symbol) and therefore, the Q-output follows the variation at D-input. At t = t2 the enable input drops to EN = 0 and at this moment D = 1 and this value of D is latched at Q. The gated D-latch enters the latch mode at t = t2 when the enable input goes to the disabled state at t = t2. The latched value is maintained upto t = t3.

Fig. 9.25(j) : Transparent and latch mode for a gated D-latch with activelow enable input Fig. 9.25(i) shows the case of activelow enable input of a gated D-latch. In this case, the Dlatch remains transparent so long EN=0 and the latching occurs with the value of D = 0 at t2 when the enable-input goes to the Logic-1 state from Logic-0. Upto t = t3 this latched value is maintained and after t = t3 the latch again enters the transparent mode and Q follow D.

The graphic symbol for the D-latch with activelow enable input is shown in Fig. 9.25(j) with a bubble..
Fig. 9.26 : Timing diagram of gatred D-latch
The timing diagram of the gated D-latch in Fig. 9.26 clearly shows the latch mode and the transparentmode for an activehigh enable input.
9.5.1 Gated D-Latch with Multiplexer The Equation Q(t+1) = EN.D + EN. Q(t) is equivalent to the equation of a 2-to-1 MUX. If the enable input EN is used as the select input of a 2-to-1 MUX. If the enable input EN is used as the select input of a 2-to-1 MUX. Then a gated D-latch can be obtained as shown in the Fig. 9.27(a).

Fig. 9.27(a) : Gated D-Latch with multiplexer Fig. 9.27(b) : 4-bit gated D-Latch using 74LS257

In this circuit when EN=0 then the MUX selects the I0 and we get Q(t+1) = Q(t). This is the latch mode of the gated D-latch. When EN=1 then the input D is transferred to the output i.e. Q(t+1) = D. This is transparentmode.

Using quad 2-to-1 MUX 74LS257 we can design a 4-bit gated D-latch as shown in Fig. This circuit shows that when EN=0 then all Q-outputs circulate through A-inputs and hence there is nochange at the Q-outputs. i.e. Q(t+1) = Q(t) is maintained. This is latchmode of this latch. But, for EN = 1 the Q-outputs follow the D-inputs through B-inputs of the MUX i.e. Q(t+1) = D. This is the transparentmode. When EN-input falls from 1-to0 then all the inputs at that moment are latched at the output of the MUX.

Show that the circuit designed with A.O.I-gate (IC74LS51) as show in Fig. 9.28(a) is equivalent to a D-latch with activehigh enable-input.
The characteristic table for this circuit shown in Fig. 9.28 is developed as Table 9.9. The characteristic equation from the Fig. 9.28 is
Q(t+1) = D.EN + Q(t). EN .
From this equation we get Q(t+1) = Q(t) if EN = 0 and Q(t+1) = D if EN = 1
Fig. 9.28 : A.O-I-gates used as a D-latch Table : 9.9

Therefore, we may say that Q-output follows D-input when enable input is 1 and there will be no change in Q-output whenm enable input is 0. This resembles a D-type latch having activehigh enable input.

Derive the characterictic equation for the two latch circuits shown in Fig. 9.29(a) and 9.29(b).
Fig. 9.29(a) Fig. 9.29(b)
The characteristic table for Fig. 9.29(a) is shown in Table 9.10(a) and its characteristic equation is derived from the K-map as shown in Fig. 9.29(c). The characteristic equation from the K-map is Q(t+1) = BA + Q(t).B. From this equation we get
Q(t+1) = A if B =0
and Q(t+1) = Q(t) if B = 1

Comparing these equations with that of the D-type latch we can say thayt it is a data latch which stores the inverse of the data from input A at Q when B = 0 and for B = 1, Q(t+1) = Q(t) i.e. nochange at the output. This is the latch condition.

Table 9.10(a) Fig. 9.29(c) : Map for Q(t+1) of the Table 9.9(a)
The characteristic table for circuit in Fig. 9.29(b) is shown in Table 9.10(b) and the Kmap for Q(t+1) is shown in Fig. 9.29(d).
Table 9.10(b) Fig. 9.29(d) : Map for Q(t + 1) of the Table 9.10(b)
The characteristic equation is derived from the K-map [Fig. 9.29(d)]. This map gives us the equation as
Q(t + 1) = Q(t) + B + A Therefore, using the circuit in Fig. 9.29(b) one can set the Q-output i.e., can make Q(t + 1) = 1 if B = A = 0, B = 1, A = 0 and B = A = 1.
Also the Q-output can be in the nochange condition i.e., Q(t + 1) = Q(t) if B = 0 and A = 1
1. An X-Y Flipflop whose characteristics table is given below is to be implemented using a J-K Flipflop [GATE 2003]

This can be done by making
(a) J = X, K = Y ; (b) J =X , K = Y;; (c) J = Y, K =X ; (d) J = Y , K =X;

2. What is the frequency and duty cycle of output Y, when clock frequency is 1 MHz @50% duty cycle? [ISRO 2013]

(a) 500 KHz @50% duty cycle; (c) 250 KHz @50% duty cycle; (b) 500 KHz @25% duty cycle; (d) 250 KHz @25% duty cycle.

3. What is the functionality of the following digital circuit? A is input data, CLK is system clock and Y is output. [ISRO 2015]

(a) Falling edge detection of input A; (c) Rising edge detection of input A; (b) Clock division by 2; (d) Clock division by 4.

4. The following CMOS transistor based circuit with A, B, C as input and X, Y as output represents which circuit? (a) Positive Edge triggered JK flipflop; (c) Positive edge triggered S-R flipflop;
[ISRO 2017] (b) Negative edge triggered JK flipflop; (d) None of the above
10.1 INTRODUCTION

A register is a synchronous sequential circuit used to store bits and the shift register is also a synchronous sequential circuit where bits can be stored and can be shifted serially several flipflops and the storage capacity of the registers or the shift registers depends on a N-Bit register or N-Bit shift register. Therefore, basically there are two types of registers– (i) Parallel Registers and (ii) Serial register or shift registers.

10.2 PARALLEL REGISTERS

We know that a single flipflop can store only one bit of information. This bit of information can be logic high or logic low (1 or 0). To store multibit information, flipflops are used as a group and the number of flipflops in the group depends on the number of bits to be stored. Fig. 10.1 shows a 4-bit parallel register using four D flipflops for storing 4 bits. The 4 bits should be ready on D3, D2, D1 and D0. These 4 bits are clocked into the four D type flipflops simultaneously as their clock inputs are common to the external clock. Similarly, these flipflops can be cleared simultaneously using a common active low clear input, CLR .The bits which enter into the flipflops are retained until we modify the input bits and apply a new clock. The clocking of bits into the register is also known as the writing operation. Therefore, the CLK input can also be labelled with WR which is the abbreviation for WRITE.

The same parallel register can be designed using edgetriggered JK or SR flipflop. The circuits are shown in Fig. 10.2(a) and Fig. 10.2(b) respectively. Important point in these two circuits is that each SR and JK flipflop has been converted into a D flipflop. The registers as described above might cause some problems if these registers are used as part of a bit digital system where all other digital subsystems as well as the registers are 295

driven by a continuous train of common clock. Since the clock is common to all subsystem, the change of output data from any subsystem will be clocked into the register and the ouput of the register will always be changing with clocks. To avoid this problem, one extra control input called LOAD input is provided to the registers circuit. The purpose of this LOAD input is to keep the SR, JK and D flipflop in the nochange mode (S=R=0, J=K=0 and D=Q in case of D flipflop) when the changes in the flipflops are not desired in the presence of continuous clocks. The LOAD input may be activehigh or low type and abbreviated as LD or LD. One such circuit with four JK flipflops is shown in Fig. 10.3(a) with activehigh LOAD input. In this circuit the transfer of data into the flipflops is load input. If the load input (LD) is low then the ANDgates in front of J and K are disabled, which means that the J and K inputs of each flipflop are low, and as a result the output of the register cannot change D3 D Q Q3
CLK
CLR
D2 D Q Q2
CLK
CLR
D1
D Q Q1
CLK
CLR
D0
D Q Q0
Ext. CLKCLK
CLR
Clear
Fig. 10.1 : 4-bit parallel register.
D3
S QQ3 CLK
R CLR
DQ22 S Q
CLK
R CLR
D1 S Q Q1 CLK
R CLR
D3
J QQ3 CLK
K CLR
D Q22
J Q
D0
S Q Q0 CLK
CLKR CLR
CLR
Fig. 10.2(a) : 4-bit parallel register using SR flipflop.
CLK
K CLR
D1 J Q Q1 CLK
K CLR
D0
J Q Q0 CLK
CLK
K CLR

CLR
Fig. 10.2(b) : 4-bit parallel register using JK flipflop.

state though there is a continuous clock. On the
D3

J Q Q3 other hand if the LD input is high then the ANDCLK gates are enabled and the data D3, D2, D1 and D0

K CLR will enter the register at the rising edge of the clock

D2

immediately next to the instant of LD going high. Q2 Once new information is written into the register,J Q

CLK the old stored information will be lost. In the K CLR circuit in Fig. 10.3(a), the clear inputs of the JK flip

flops are connected together to make a commonD1

J Q Q1 activelow clear input. This common active low CLK clear input should be kept high to keep the register

KCLR circuit in operation, otherwise, the register output D0

will be cleared if clear input is low. It may be noted J QQ0 in the circuit that the LD input has to drive eight CLK ANDgates, the CLK input has to drive four clock LD
K CLR inputs and the CLR input has to drive four clear
CLK
inputs. To reduce the fan-out or to increase theCLR driving capacity of the external circuit, buffersFig. 10.3(a) : Register with Load input. should be used for driving these three inputs. LD
D3
D
D Q Q3
D3
CLK
CLK Q3 Q3 CLR CLRQ
D2 D
D Q Q
D
2
2
CLK Q2 Q2 CLK
CLR Q CLR
D1 D
D1
D Q Q1
CLK
CLK Q1 Q1 CLR CLRQ
D0
D
Q0
D0
D QCLK QQ0 Q0 CLK CLK(or WR)
CLR CLR CLR
CLK
OE (or RD)
CLK
Fig. 10.3(b) : Register using D flipflops. Fig. 10.3(c) : 4-Bit Bus Register.

If the register is designed with all D flipflops and with the facility of LOAD input then problem arises because the D flipflops do not have any nochange mode like JK and SR flip-flops. Therefore, an extra hardware is required for removing this problem. The circuit of a 4-bit register using D flipflops is established when LOAD=0, so that there is a recirculation of same data in the presence of the clocks. This is equivalent to the nochange mode. But when LOAD=1, then this feedback is disabled and the D input of each flipflop is connected to the external data input so that these D inputs enter the register with the clock.

Another vital category of parallel registers are the BUS REGISTERS. These registers are called BUS REGISTERS because they are specially useful in the bus oriented digital circuit for handling the data transfer operation among the groups of registers connected to a common data bus. The logic circuit for a 4-bit bus register is illustrated in Fig. 10.3(c). The block diagram representation of the circuit in Fig. 10.3(c) is shown in Fig. 10.3(d). It may be seen that structurally the bus register is the same as the other parallel register described so far except for a difference in the output circuit. In this circuit one inverting tristate gate has been used at (OE ) output of each flipflop. Therefore, by controlling the logic state of the control inputs of all the tristate gates simultaneously, the data which are loaded into the four D flipflops are made available at Q3 Q2 Q1 Q0, i.e.

at the outputs of the tristate gates. For this circuit
D3 D3 Q3
D2 D2
Q2

if the tristate control inputs are kept at Logic-0 then the high impedance state of the gates practically isolate the flipflops from the outputs D1 D1 Q1

D0 D0 Q0

CLK or WR
RD CLR
Clear
Fig. 10.3(d) : Block diagram of
4-bit Bus Register.

Q3 Q2 Q1 Q0. The tristate controls inputs are tied together to a common input called output Enable (OE). This output enable may be activelow or activehigh. For the present circuit the output OE or RD enable input is activelow ( OE ) because of one inverting buffer has been used to drive all the control inputs of tristate gates. This input may also be called as Read Input ( RD ) since the enabling of the tristate gates is equivalent to a read operation.

Now let us see how the parallel registers, which do not have the tristate outputs, create hazards in bus oriented circuits and how the hazards can be removed by using the bus registers.

Consider the circuit in Fig. 10.3(e) in which three 4-bit registers
, , and are connected to the 4-bit wide common data bus B3 B2 B1 B0. If output bits of Reg. and

connected to the same bus line and are in opposite logic states then a bus conflict occurs. The term bus conflict means that the bus line to which two outputs of opposite logic states are connected cannot attain either Logic-1 or Logic-0 simultaneously. Under REG A
B3B2B1B0

D3 D3 Q3

D2 D2 Q2

D1 D1 Q1

D0 D0 Q0

REG C CLKCLR
D3 Q3

D2 Q2

D1 Q1

D0 Q0

REG B
CLK CLR

D3 D3 Q3

D2 D2 Q2

D1 D1 Q1

D0 D0 Q0

CLK CLR
Fig. 10.3(e) : Registers connected to a 4-bit bus. this situation if a clock is applied to Reg
then the
inputs connected to the bus line may receive some spurious data. This situation can be avoided if only one register is allowed to be connected to the bus at a time keeping all other registers electrically isolated from the bus the registers with tristated outputs.

Bidirectional Registers :

We have seen, so far, the parallel registers where the data input lines and the data output lines were completely separate. But registers can also be designed to load and retrieve data using the same lines. These type of registers are called Bidirectional Registers or Common I/O Register. The earlier registers may also be called Registers with Separate I/O.

Fig. 10.4(a) shows the logic circuit of a 4-bit parallel bidirectional register and the logic symbol for the same is shown in Fig. 10.4(b). Fig. 10.4(a) shows that the 4-bit data can be loaded into the Dlatches by applying a logiclow to the input-enable ( IE ), provided, the data is ready on the four inputs D3, D2, D1 and D0 and the tristate gates are kept in the high impedance state. The tristate gates of this circuit go to the high impedance state if OE input is at logic-high. The input G of each D latch is the enable input which is activehigh. All the G inputs of the four Dlatches are driven by an inverting buffer whose input is IE . This is done to reduce fan-out on the source
D3 D2 D1 D0
OE or RD
D QQ D Q D Q D Q 3 Q2 Q1 Q0
G G
G G CLR
CLR CLR CLR CLR
IE or WR
Fig. 10.4(a) : Logic circuit of a 4-bit bidirectional register. generating this IE signal. As the loading operation is equivalent to the writing operation in the register, some manufacturers use the abbreviation WR instead of IE. In this circuit the input-enable ( IE ) is activelow hence abbreviation WR has been used in the logic symbol [Fig. 10.4(b)].

To retrieve the stored data from the D latches of the

register, the output-enable ( OE ) input should be at logiclow so as to pass the Q outputs of the D latches through the tristated buffers to D3, D2, D1 and D0. The output operation from the register is equivalent to the reading D3 D2 D1 D0
RD
WR

Bidirectional register
CLR

Fig. 10.4(b) : Logic symbol of a

bidirectional register.
operation. Thus the OE input is sometimes labelled using RD.
While using the bidirectional registers the users should be careful not to allow reading and writing operation at the same time. i.e. RD and WR should not be low at the same time.
D3D2D1D0
RD
R/W
CLRCLR

In some bidirectional registers instead of two separate inputs for Read and Write, the manufacturer provide a single input with the lable R/W low we can write into the register and making R/W high we can read the WR content of the register. For this purpose the circuit should be modified to generate RD and Fig. 10.4(c) : Logic symbol of a
bidirectional register.

WR signal from the external R/W input. The circuit it shown in Fig. 10.4(c).
10.3 SHIFT REGISTERS

A shift Register is a serial storage register or simply a serial register. In this type of register, the data can be entered either in a parallel or in serial manner. But after the data is entered into the shift register circuit, they can be shifted towards the right or left. Similarly, the data

canbe retrieved from the shiftregistereitherseriallyorparallely. Like parallelregisters discussed in the earlier sections of this chapter, the shift registers are a collection of flipflops. If there are N flipflops in the shift register, the circuit transfers its stored bit of information (either 1 or 0) to its adjacent (i.e. either to its left or to its right) flipflop coincident with each clock pulse. External command input is provided to the circuit to shift the position of the information bits either to the right or left depending upon the design of the circuit.

The shift register circuits can be classified into the following categories depending on the way of input or output of the data.

(a) serial-In SerialOut (SISO). (b) Serial-In Parallel-Out (SIPO). (c) Parallel-In-SerialOut (PISO). (d) Parallel-In-Parallel out (PIPO). (e) Bidirectional shift register. (f) Universal Shift Register.

The shift register circuit is a synchronous sequential circuit because all the flipflops of this circuit are driven by a common clock and hence any change in the circuit occurs only at the clock edges. Any type of flipflop can be used for the design of the shift register. Following is the description of the actions of different shift register circuits.

(a) Serial-In-SerialOut (SISO) Shift Register
1011 A B C D Serial Output
Serial Input X X X X
CLK
101
X
Serial Input 1 X X X
CLK1
10
XX
Serial Input 1 1 X X
CLK
2
1 0 1 1 XXXX
Serial Input

CLK3

XXXX
Serial Input 1 0 1 1

CLK4

1
Serial Input X 1 0 1

CLK5 11
Serial Input X X 1 0Serial Input
CLK6
Serial Input
X X X 1011

Serial Input CLK7

Serial Input X X X X1011
Serial Input CLK8
Fig. 10.5(a) : Data movement in a SISO.

To understand the basic circuit action of a SISO, we take the help of Fig. 10. 5(a). In this figure each box represents a storage unit and all the storage units are driven by a common clock. The storage units are connected in such a way that when they are simultaneously clocked a binary input 1 or 0 enters into the storage unit A and the previous content of A is transferred to B, content of B is transferred to C, content of C is transferred to D and the content of D comes out of output. This means that each stored bit of the storage unit is shifted towards the right by one bit position and a new external bit enters A if one clock pulse is applied. The movement of data towards the right with each clock is shown in Fig. 10.5(a) by using arrowheads. This figure shows how the external four bits 1, 0, 1 and 1 enter the storage units one garbage data (X = 1 or 0) of the storage units. We need altogether 4 clock pulse to load 4 external bits in the 4 storage units. If clock is applied after the filling up of the storage units with external serial data, the stored data in D will comes out and the unit A will be filled up either with 1 or 0. Hence, this way we need 4 clocks for complete retrieval of the stored data.

Each storage unit can now be replaced by any type of flipflop like JK and D during the circuit implementation.
u Design Using D flipflops : For this design each storage unit of Fig. 10.5(a) is replaced by a D flipflop as shown in Fig. 10.5(b). This flipflop may be either positive or negative edgetriggered. The clock inputs of all the flipflops are tied up together for simultaneous clocking. The D input of FFAis connected 1
Serial Input Q1 D2 Q2 D3 Q3 D4
Serial Output 1011
Q4CLK FFA
CLK FFBCLK FFCCLK FFD CLR CLR
CLR CLR Clock
Clear
Fig. 10.5(b) : 4-bit Serial-in SerialOut shift register.
to the external source of serial bits for receiving the serial data and the Q output of each is connected to the D input of the adjacent flipflop for transferring the stored data Before the clock pulse After the clock pulse Serial Clock Q1 Q2 Q3 Q4 Clock Q1 Q2 Q3 Q4 Input No. No.
1 1 X X X X 1 1 X X X

1 2 1 X X X 2 1 1 X X
0 3 1 1 X X 3 0 1 1 X
1 4 0 1 1 X 4 1 0 1 1 Table 10.1 : Function table for the Fig. 10.5(b).
of one flipflop to its adjacent one with the1 2 3

4

clock. The circuit for the 4-bit SISO is shown

in Fig. 10.5(b) and its function table is Clock
shown in Table 10.1. This table shows thatSerial 1 1 0 1

the initial content of the flipflops before anyInput

clockpulseis don’tcare type(X) andthe serial

data is 1011 assuming that the LSB of theQ1

clock, the serial data enters the circuit bitQ2
0 1 1 1 1 0

by-bit removing the don’t-cares. Timing

diagram has also been drawn in Fig. 10.5(c)Q3

to show the bit flow in the circuit with

clocks. While drawing the timing diagramQ4we have assumed for the sake of simplicity Fig. 10.5(c) : Timing diagram of a 4-bit SISO.

0 1 1 1 1 0 0 1
serial data is to be entered first. With each
0 0
0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 1
that all the flipflops initially start from the reset state i.e. Q1 = Q2 = Q3 = Q4 = 0 before the first clock. This can be done by using logic-0 voltage to the common CLR input. The waveform for the serial input in this figure shows that it remains high during the 1st and 2nd falling edges of the clock, goes low after the 2nd clock and remains low during 3rd falling edge of the clock but goes high before the 4th clock edge comes. This indicates that the bit which is to be entered in the shift register should be made ready just before a clock edge.

u During Using JK FlipFlops :
Designing of the same circuit using all JK flipflops can be done easily by converting each JK flipflop to a D flipflop. This can be done by connecting one inverter between J and K

input of each JK flipflop. But, as Q and Q outputs are available from each JK flipflop so we do not need to use inverter in the JK flipflops except for the first JK flipflop which receives the serial bits from the external source. The circuit for a 4-bit SISO using all JK flipflops is shown in Fig. 10.5(d).

1
Serial Input
PREQ J PREQ
J
PRE
Q
J
PRE
Q Serial Output J
CLK
CLK CLK CLK
K CLRQ K
K CLRQ K CLRQCLRQ
CLR
CLK
Fig. 10.5(d) : 4-bit SISO using JK flipflops.
(b) Serial-In-Parallel-Out (SIPO) Shift Register In a SISO register, we have seen that the serially input data can be accessed one-by-one through the Q output of the flipflop which is placed in the rightmost position which makes the read/retreival operation show and at the Q0 Q1 Q2 Q3 same time after retreival whole string of data Serial
will geterase. Butto retrieve the serially loaded
Input

A B C D data of the shift register in a parallel fashion,

the Q output of each flipflop should be made

available to the user. Fig. 10.6(a) shows the

CLK block diagram representation of a 4-bit SIPO Fig. 10.6(a) : Block diagram of a 4-Bit SIPO. shift register where O0, O1, O2 and O3 are the outputs of the storage units of A, B, C, and D respectively. Corresponding circuit implementation using D and JK flipflops are shown in Fig. 10.6(b) and Fig. 10.6(c) respectively. In these two circuits the serial data can be pushed into the circuit bit-by-bit with the application of simultaneous clocking of the flipflops in a similar fashion as we did in the case of SISO but the serially loaded data in the circuit are available from the Q outputs of the flipflops. Thus, for a N-bit SIPO shift register we need N number of clocks to load N-bit data serially Q0 Q1 Q2 Q3 1
Serial Input
PREQ J PREQ J PREQ J PREQJ
CLK
CLK CLK CLK
CLR Q CLR
CLR CLR Q CLR
CLK
Fig. 10.6(b) : 4-Bit SIPO using D flipflops.
and to get the complete N-bit data from Q outputs in parallel. This type of shift register is very useful for the conversion of serial data into the parallel form.
Q0 Q1 Q2 Q3 1
Serial Input
J PREQ
J PREQ J PREQ J PREQ
CLK CLK CLK CLK
K CLRQ
K CLRQ K CLRQ K CLRQ CLR
CLK
Fig. 10.6(c) : 4-Bit SIPO using JK flipflops.
(c) Parallel-In-SerialOut (PISO) Shift Register The parallel-in-serial-out (PISO) shift register acts in a way opposite to that of a serial-inparallel-out shift register. In PISO shift register, the external data is loaded in parallel utilizing the preset and clear inputs of all the flipflops. After the loading is complete the preset and clear actions are disabled and the shifting action is invoked after it. For this purpose, one external control input is provided to this circuit to control the shifting and loading operations. The logic circuit for a 4-bit PISO is shown in Fig. 10.7 where IA, IB, IC and ID are the parallel inputs and SH/LD is the control for loading the parallel data and shifting the serial data. The logic equations for the preset and clear input of any flipflop in terms of control input
SH/LD and the parallel data input bit Ii can be written as: PRE ☐iI .(SH/LD and CLR ☐ I .(SH/LD

Therefore, for SH/LD =0, PRE ☐ ☐ CLR= Iiand hence for Ii= 0, PRE = 1 and CLR = 0. This will make the Q output of i-th flipflop 0 as if the parallel input bit Ii = 0 is loaded in the i-th

flipflop. Similarly, for Ii = 1, PRE = 0 and CLR= 1 which will set the Q output of the i-th flipflop 1 as if the parallel input bit Ii = is loaded in the i-th flipflop. Similarly keeping SH/LD =0 we can load any bit pattern to the flipflops simultaneously. During this time i.e. when either the preset or clear input of flipflop is active the clock input cannot play its role.

IAIBICID SH/LD
Serial Input
Serial OutputD PRE Q D PRE Q
DPRE Q DPRE Q FFA FFB
FFC FFD
CLRQ CLRQ
CLRQ CLRQ
CLK
Fig. 10.7 : 4-Bit parallel-in-serial-out shift register using D flipflops.

On the otherhand if SH/LD = 1 then PRE =CLR=1 and the preset and clear actions will be disabled. Due to this, the flipflops will not be influenced by the external parallel input bits anymore but the clocking action will come into play. Now, this circuit will behave as a SISO i.e. serial data will be picked-up by the D input of FFA and the Q bit of any flipflop will be transferred to its adjacent flipflop as explained earlier in case of SISO. This PISO shift register can also be designed using JK flipflops. The parallel loading is also called Broadside Loading.

(d) Parallel-In-Parallel-Out (PIPO) Shift Register
The parallel-in-parallel-out shift register is the simplest and fastest shift register. In this shift register the data is loaded in parallel with the help of the preset and clear inputs of the
I0I1I2I3
DPRE Q DPRE Q
DPRE Q DPRE Q
CLK CLK
CLK CLK
CLRQ CLRQ
CLRQ CLRQ
QA QB QC QD Fig. 10.8 : 4-Bit parallel-in-parallel-out shift register.
flipflops and the loaded data are available also in parallel form at the Q outputs of the flipflops.
Fig. 10.8 shows a 4-bit PIPO shift register. As there is no shifting operation hence Q to D

connection between two neighbouring flipflops and the SH/LD input are not used in the circuit. This circuit does not need any clock input and thus this circuit is asynchronous in nature, if we assume the PRE and CLR inputs are independent of clocks. Therefore, to make it synchronous, we may either use the circuit as shown in Fig. 10.3(a) and Fig. 10.3(b) or we may choose the flipflops having synchronous preset and clear inputs. In that case the clock inputs of all the flipflops should be connected together for simultaneous clocking.

Design a 4-bit shift register circuit using D flipflops and multiplexers with the following facilities.
(i) Data can be input in serial form
(ii) data can be input in parallel form (iii) data can be output in serial form
(iv) data can be output in parallel form.
The required circuit is shown in Fig. 10.9(a).
X
Parallel Input
I0I1
I2I3
Or
Serial
2-to-1 2-to-1 2-to-1
Input
MUX MUX MUX
X0 Y D Q X1 S D Q X1 S D Q D Q X
X0 Y0 Y
1 S
CLK
CLK CLK CLK
CLR
CLR CLR CLR
CLR
CLK
SH/LD Q0 Q1
Q
2
SerialQ3
Output or
Parallel Output
Fig. 10.9(a) : Circuit for the example 4 using MUXs.
If SH/LD =1, then the parallel inputs I0, I1, I2 and I3 can reach the D inputs of the flipflops and no data flow will occur from Q output of any flipflop to the D input of the following flipflop since the select input (S) of the MUX is 0 and the input X0of the 2-to-1 MUXs is selected for input SH/LD =0. Therefore, the parallel data which are ready at inputs will reach the D inputs of the flipflops and will be loaded in the flipflops if a clock is applied and these parallel input data will also be available in parallel at the outputs Q0, Q1, Q2 and Q3.

If SH/LD = 0, then the link between Q output of one flipflop with the D input of the next flipflop is set-up through X1 input of the MUXs. The I0 input can be used as the serial input and Q3 output can be used as the serial output. The serial data can be shifted towards the right, bit-by-bit with each clock. The three inverting type buffers are used for buffering CLR, CLK and SH/LD inputs.
The 2-to-1 MUX between flipflops can also be replaced using AND-OR circuit as shown in Fig. 10.9(b).
2-to-1MUXQi–1 Ii
Ii X
0 SH/LD=S
Y Di
Qi–1 X1 S
Di Fig. 10.9(b) :
(e) Bidirectional Shift Registers
The circuit shown in Fig. 10.10(a) represents a 4-bit bidirectional shift register using four D flipflops and four 2-to-1 MUXs. The bidirectional shift register is one in which the data
Serial Input Right (SIR)
MUX
InputLeft 0 Y X0 Y X0 Y SerialX0 Y X
D Q X1S D Q X1S D Q X1S D Q(SIL)
X1S
CLK CLK CLK CLK FF0 FF1 FF2 FF3 CLK
R/L
Q0 Q1 Q2 Q2 Or Serial out (SOL) Or Serial out (SOR) Left Right Fig. 10.10(a) : Bidirectional 4-Bit shift register.

can be shifted either to the left or right. The direction of data movement in the bidirectional shift register can be controlled by the logic level of a control input R/L as shown in the figure.

This input is buffered using a non-inverting buffer. The control input ( R/L ) is the select input of all the 2-to-1 MUXs used in the circuit. In this circuit there are two serial input lines.

(i) SIL – Serial input from left
(ii) SIR – Serial input from right
and two serial output lines: (i) SOL – Serial output on left
(ii) SOR – Serial output on right.
This circuit uses four 2-to-1 MUXs whose select inputs are connected together to the output of a non-inverting buffer and the input of this buffer is the control input R/L so that whenR/L = 0 then the MUXs select X0 input and for R/L = 1 the MUXs select X1 input.

If R/L = 0, then the serial data input line (SIR) on the right hand side is connected to the D input of FF3 and the Q outputs of FF3, FF2 and FF1 are connected to the D inputs of FF2, FF1 and FF0 respectively via X0 inputs of the MUXs. Therefore, for R/L = 0 the data on SIR can move towards left bit-by-bit when clocks are applied. Similarly, if R/L = 1 then the serial data from SIL input can move towards right via the X1input of the MUXs when the clocks are applied.

The data which are shifted towards left can be received from Q0 output of FF0 and the data which are shifted towards right can be received from Q3 output of FF3. Also, the data which are serially loaded from either directions can be retrieved from the Q0, Q1, Q2 and Q3 outputs in parallel everyafter four clocks. The block diagram representation of the 4-bit bidirectional shift register is shown in Fig. 10.10(b), and Fig. 10.10(c) shows how to cascade two 4-bit bidirectional shift registers to make an 8-bit bidirectional shift register.

SIR
SOR

SOL

SIL 4-Bit
CLK bidirectional shift register
R/L
Fig. 10.10(b) : Block diagram representation.
SIR
SOL SIR SOR
SILSOL
4-Bit SIR SOL 4-Bit
CLK bidirectional
bidirectional CLK shift register
CLK shift register R/L
R/L
R/L
Fig. 10.10(c) : Cascading of two 4-bit bi-drectional shift registers.
(f) Universal Shift Register A universal shift register is a bidirectional shift register whose input and output can either be in serial or in parallel form. The logic circuit for a 4-bit universal shift register is shown in Fig. 10.11(a) using D flipflops and 4-to-1 MUXs. The mode of operation is selected using two control inputs, M1 and M0, common to four multiplexers as select inputs. In this circuit if the mode control input is M1 M0, common to four multiplexers as select inputs. In this circuit if the mode control input is M1M0 = 00, then the Q output of any flipflop is connected to its D input of the same flipflop via the X0 input of the multiplexers because, for each multiplexer the X0 input is selected when M1 M0 = 00 and the output Y of each multiplexer is connected to the D input of the flipflop. Hence, if clocks are applied then there will be nochange in the content of the flipflop. This mode of operation is called NOCHANGE mode because Qi output of FFi will pass through the X0 input of MUX to the Di input of the same flipflop and will be loaded back into it where i = 0-to-3.

I0 I1 I2 I3
SIR
SIL
X3 X2 X1 X0 X3 X2 X1 X0 X3 X2 X1 X0 X3 X2 X1 X0S1 MUX-0
1 MUX-1 1 MUX-2 1 MUX-3 S0 Y
S
0 YS0 YS0 Y M1
M
0
D0 Q0 D1 Q1 D2 Q2 D3 Q3
FF0
FF1 FF2 FF3
CLK
Q0 Q1 Q2 Q3 or SOL
Fig. 10.11(a) : 4-bit universal shift register.

If M1 M0 = 01, then the X1 input of each MUX is selected and this circuit is configured as left shift register. The serial input bit from SIL input line enters D input of FF3. The Q output of any flipflop is connected to the D input of the flipflop adjacent to its left via X1 input of the MUX. Therefore, whenever a clock is applied a new bit enters FF3, previously stored bits in the four flipflops shift towards left by one bit position and the serially shifted bits towards left are available on Q0 output one by one. This mode corresplnds to the SHIFT LEFT MODE. At any time the user may also read the shifted bit from all the flipflops simultaneously from Q0, Q1, Q2 and Q3 output.

If M1 M0 = 10, then all the MUXs select the X2 inputs. Hence, it is possible to load the four bits using the parallel input lines I0, I1, I2 and I3 to the flipflops. These bits will be available at Q0, Q1, Q2 and Q3 simultaneously when the flipflops are clocked simultaneously. This mode corresponds to PARALLEL LOAD MODE.

If M1 M0 = 11, the X3 input of each MUX is selected and the circuit is configured as right shift register. The D input of FF0 receives serial bits from SIL input and the D input of any of the following flipflops receives the bits from the Q output of the just preceding flipflop. Due to this the whole bit pattern stored in the D flipflops shifts towards the right with a new bit in Q0 from the serial input SIL. The shifted bit towards right can be obtained from the output Q3. This mode of operation is called SHIFT RIGHT MODE.

The block diagram representation of a 4-bit universal shift register is shown in Fig. 10.11(b) and its function table is shown in Table 10.2.
I3 I2 I1 I0 Mode Control M1 M0 SIL
D3 D2 D1 D0 SIR 0 0 SOL
CLK 4-bit universalSOR 0 1shift register
M1
1 0 M2
Q3 Q2 Q1 Q0 1 1
Clock Action ☐ Nochange ☐ Shift left ☐ Parallel load ☐ Shift right

Table 10.2 : Function table of the Fig. 10.11(b) : Block diagram representation of Universal shift register. 4-Bit universal shift register.
The 4-to-1 MUXs used in this circuit can be replaced by the AND-OR circuit as shown in Fig. 10.11(c).
Qi+1Qi+1
(or, SIL for MUX-0 only)Ii (or, SIL for MUX-3 only)Qi
M1
M0
X3
X2 X1 X0
Y Di
Fig. 10.11(c) : AND-OR equivalent for a 4-to-1 MUX.

1. For the circuit shown in the figure below, two 4-bit parallel-in serial-out shift registers loaded with the data shown are used to feed a data to a full adder. Initially all the flipflops are in clear state. After applying two clock pulses the output of the full adder should be [GATE 2006]

(a) S = 0, Co = 0;
(b) S = 0, Co = 1;
(c) S = 1, Co = 0;
(d) S = 1, Co = 1.
3. Consider the shift register [ISRO 2017]
The frequency, of signal x is fs and the shift register is clocked at the positive edge of 2fs. The time offset between A and B is
(a) 1/(2fs); (b) 1/fs; (c)3/(2fs); (d) 1/(4fs).

4. The shift register is loaded with bit pattern 1010. With clock the bit will shift from left to right. After how many clocks the content of the shift register become 1010 again? [GATE 2003]

(a) 3; (b) 7; (c) 11; (d) 15.
5. What is the value of the register formed from D flipflops using Q0, Q1, and Q2 as output (Q0Q1Q2) after 14 cycles [ISRO 2017]
(a) 110; (b) 000; (c) 001; (d) 011.
6. The greatest negative number which can be stored in a 8-bit register using 2’s complement arithmetic is [ISRO 2011]
(a) – 256; (b) – 255; (c) – 127; (d) – 128
7. In a JK flip flop we have J = Q, and K = 1. Assuming that the flip flop was initially cleared and clocked for 6 pulses, the sequence at the output Q will be [ISRO 2011]
(a) 010000; (b) 011001; (c) 010019; (d) 010101
313
11.1 INTRODUCTION

A counter is a class of sequential circuit that generates a predetermined binary number sequence over and over again. The counter circuits are designed by cascading several flipflops and some extra logic gates or combinational logic modules if necessary. The bits of the binary sequence are nothing but the Q output of the flipflops and change of the binary sequence from one to another is controlled by the clock input to the flipflops. The flipflops in a counter may be so connected, that at any time the bit outputs taken together represent an equivalent decimal number equal to the number of clocks that are applied at the clock inputs of the flipflops. Hence, this class of sequential circuit is named as “Counter”. For example, if a counter designed with four flipflops shows an output Q3Q2Q1Q0 = 1001 at any time starting from Q3Q2Q1Q0 = 0000 without missing any state from 0 to 9 then it means that it has reached to this state Q3Q2Q1Q0 = 1001 due to 9 clock pulses. Thus, a counter counts the number of clocks and if each clock is produced due to some event then a counter may be called an “Event Counter”. Normally, for an event counter, the clocks arrive the counter circuit, may not periodically change i.e., at regular interval of time.

Counters are widely used in a digital system for the division of rate of the input clocks. Frequency division is possible because each Q output of the flipflop of a counting circuit is a specific fraction of the input clock frequency. This will be clear from the timing diagram of the counter.

Counters can be used for timing functions, as in digital watches and in the creation of timedelays, as well as to produce non-sequential binary counts, such as Gray code counters whose output follows the sequence of the Gray code.

Another use of counters may be the periodic waveform generators using counters. In this chapter following three types of counters will be discussed—
313

(i) Asynchronous (ii) Synchronous and (iii) Hybrid

11.2 ASYNCHRONOUS COUNTERS

In asynchronous counters all the flipflops used in the counter are not triggered by the same source of clock and thus do not change their state (Q-output) in synchronization with one another. A special class of these asynchronous counters are called Ripple Counters where one flipflop is triggered by the external clock and the other flipflops are triggered not by the external clock but by the transition of the Q outputs of the adjacent lower significant flipflops. The position of the flipflop which is driven by the external clock or pulses proportional to event is the least significant position.

The asynchronous counters can be divided into following four major categories (i) Binary Counter or Full Sequence Length Counter.
(ii) Truncated Binary Counter or Modulo Counter.
(iii) Bidirectional Counter or UP/DOWN Counter.
(iv) Presettable Counter.

Out of these counters the binary counter is very simple to design. The modulo counters need some feedback logic circuit to truncate the count sequence before the counter circuit reaches its maximum count. The bidirectional counters either counts up from a lower count value to the higher value or counts down from a higher count value to the lower value. The direction of counting depends on the connection of Q output of one flipflop to the clock input of the next flipflop. The presettable counters start their counting from any predefined starting count value and follow the binary sequence either in the UP or DOWN direction.

11.2.1 Asynchronous Binary Ripple Counters

The simplest asynchronous counter is the Binary Ripple Counter. We may design this type of counter using either JK or D flipflop and the clock input of the flipflops may be positive or negative edge sensitive. All the Q outputs of the flipflops used in the counter circuit taken together are called the output of the counter or State of the Counter. The state of the counter can be changed in a predefined manner with a clock. If the change of states of a counter follows the sequence of binary number in the increasing order then that counter will be known as Binary UpCounter and if the change of states of a counter follows the decreasing order of the binary number then that counter will be called Binary DownCounter. The total length of the count sequence depends on the number of flipflops used in the counter circuit. If a counter is designed with N number

of flipflops then the maximum number of states in the count sequence will be 2N. For example, for a 4-bit binary counter the number of flipflops required is 4 and the maximum number of states will be 24 = 16. If the Q outputs of the 4 flipflops of a counter circuit are Q3, Q2, Q1 and Q0 then the count sequence of UpCounter will be as follows.

Q3Q2Q1Q0 = 0000☐ 0001☐ 0010 ☐ 0011 ☐ 0100☐ 0101 ☐ 0110☐ 0111 ☐ ☐ 1111☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐

and the count sequence of a 4-bit binary downcounter will be
Q3Q2Q1Q0 = 1111 ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐ ☐ ☐☐☐☐
☐ ☐ 0000☐ 0001☐ 0010 ☐ 0011 ☐ 0100☐ 0101 ☐ 0110☐ 0111

From the above count sequence it may be noted that the counter (Up and Down) may start from any state but comes back to the starting state and the counter circuit has to pass through 24 = 16 states.

It has been stated that we can use either JK or D type flipflops for the design of the counter but for most of the asynchronous designs, the flipflops (JK or D) should be converted into T type so that the flipflops may toggle with each clock. In chapter 9 if is uillustrated that how the JK and D flipflops can be converted into T type.

In Fig. 11.1(a) the J and K inputs of the JK flipflop are connected to a common point called T. If the T input is HIGH then the JK flipflop will behave as T flipflop and the Q (or Q ) output will toggle with each clock. But for T = 0 the Q (or Q ) output will not change its state with clock. Thus, this T input may be used as the enable input for the toggling action. For the circuits shown in Fig. 11.1(b) and (c) the flipflop will always toggle with each negative edge of the clock. This hardware does not provide any enable input.

1 1
T J
PREQ ☐ T PREQ
Ext. CLK
Ext. CLKClockClock
K
Q0 QCLR Q

1 1 ☐ T= Common point of J and K

Fig. 11.1(a) : JK flipflop converted to T flipflop 1 1 1 1
J PREQ
PRE QD PREQ
PREQ
Ext. CLK
Ext. TExt. CLK
Ext. TClockClock ClockClock CLRQ K CLR Q
CLRQKCLR
1 11 1
Fig. 11.1(b) : CLK input of JK flipflops is the Fig. 11.1(c) : D flipflop converted to T flipflop T-input of the equivalent T flipflop.

To get the positive edge triggered T type flipflop we have to replace the negative edge triggered JK or D flipflop by the positive edge triggered version of these flipflop by keeping all other hardwire unchanged.

11.2.1.1 Binary UP Ripple Counters

Fig 11.2(a) and (b) shows two possible circuits for a 3-bit a asynchronous binary up ripple counter. In each of these two, T type flipflop is nothing but either JK or D type negative edge triggered flipflop hardwired as shown in Fig. 11.1(a) to (c). The design procedure of a 3-bit up counter can be extended to N-bit upcounter by using N number of flipflops but keeping the mode of interconnection between flipflops the same.

In the above circuits, the flipflop FF0 receives the clocks from an external clock source but the clock input of each of the following flipflops receive their clocks at their clock input from the Q outputs of the adjacent preceding flipflop. Q0 output of FF0 clocks FF1, the Q1 output of FF1 clocks FF2 and in general in such circuit Qi output of the i-th flipflop will trigger the clock input of the (i+1) th flipflop. It may be noted that all the activelow preset inputs of the flipflops are tied-up together to a common point called PRESET . A common CLEAR input is obtained by connecting all the activelow clear inputs of the flipflops.

Q0 Q1 Q2 PRESET

PRE PRE PRE 1 TQ 1 TQ 1 TQ

FF0
FF1 FF2 External
CLKClockCLK
CLK
CLRQ Q0
CLRQ Q1 CLRQ Q2
CLEAR
Fig. 11.2(a) : 3-bit binary ripple UPcounter using negative edge triggered T type flipflop. The T-input of each flipflop is connected to Logic-1
Q0 Q1 Q2 PRESET
PRE
PRE PRE Q Q Q External
T FF0
T FF1 T FF2Clock
Q Q0
CLRQ Q1 CLRQ Q2CLR
CLEAR
Fig. 11.2(b) : 3-bit binary ripple UPcounter using negative edge
triggered flipflops. T-input is the clock input.

When the counter is in counting mode then these two inputs ( PRESET and CLEAR ) should be connected to Logic-1 and the T input of each flipflop in Fig. 11.2(a) should be connected to Logic-1. For simultaneous resetting (Q0 = Q1 = Q2 = ...... = 0), the CLEAR input should be at Logic-0 and for simultaneous setting (Q0 = Q1 = Q2 = .... = 1), the PRESET input should be made low. Before counting starts from the reset state, the CLEAR input should be made low for a short time for resetting all the flipflops and then the CLEAR input is kept to Logic-1 throughout the count mode but the PRESET input should always be connected to logic-1 as it is not necessary. On the otherhand if the counting has to be started from the preset state (Q0 = Q1 = Q2 = .... = 1) then the PRESET input of the 3-bit counter should be connected to logic-0 for a short time to set all the Q outputs to 1 and then to logic-1 throughout the count cycle. The CLEAR input should be connected to logic-1 always for this counting. The same 3 bit binary nipple UPcounter as shown in Fig. 11.2(b) where T-input is used as negative edge triggered clock input.
As the clock inputs of all the T flipflops of this circuit are negative edge sensitive so the _☐ 1 2 3 4 5 6 7 8 9 10Clock No.

f FrequencyExternal

Clock

0 1 0 1
0 1 0 1 0 1 0f/2( ,, ) Q0
f/4( ,, )0 0 1 1
0 0 1 1 0 0 1 Q1
f/8( ,, )0 0 0 0 1 1 1 1 0 0 0 Q
2
One Cycle
Reycle Fig. 11.3 : Timing diagram of a 3-bit upcounter partaining of Fig. 11.2

output Q0 to FF0 will toggle each time a negative edge of the external clock arrives at its clock input but the other flipflops (FF1 and FF2) will toggle whenever the Q output of their preceding flipflop changes state from 1 to 0. The timing diagram and the count Decimal equivalent of count output = 010

sequence of this 3-bit counter are shown inQ Q1 Q0Fig. 11.3 and Fig. 11.4 respectively. These

0 two figures show how the falling edges (1 to 0 0
0) of the external clock and the Q outputs0 0 1 cause a change of state of FF0, FF1, FF2. In= 1

10
this way one can cascade several flipflops to0 1 0 = 210expand the size of the counter. Fig.11.4

shows that Q0 changes its state with each0 1 1 = 310 falling edge of the clock. Q1 changes with

1 0each transition of 1 to 0 of Q0 and Q2
changes with each transitions of 1 to 0 of 1 0
Q1. All the transitions are marked with the
arrowheaded lines.1 1

0 = 410
1 = 510
0 = 610
1 = 710

The flipflop which receives the external1 1 clock is said to be in the least significant

position and the flipflop whose position is0 0 0 = 010 the furthest is said to be in the most
significant position. Fig. 11.4 : Count sequence We understand from the above
discussions that for an N-bit ripple counter we need N flipflops.
Another important point to be noted in the count sequence of the 3-bit binary upcounter is that the final count of this

counter can reach a value of one less than 23 000Clock = 8 i.e. 7 (☐ 111). In general, for an up

counter implemented using N flipflops the 111 001 counter can count-up to a count whose

value is 2N –1 starting from the reset state.

If the changes in the output of each flip

010 flop is examined then it may be seen that for110

input clock frequency fin, the output Q0 of FF0

changes at a rate of fin/2, the output Q1 of FF1 changes at fin/4. In general, for an N-bit ripple

011 counter the change would be at the rate of101 fin/2 at Q0, fin/4 at Q1, fin/8 at Q2, ..., fin/2N at

100 QN–1. Thus, using this counter circuit, the

frequency of the digital signal can be divided by a power of 2. The rate of a digital signal can

Fig. 11.5 : State diagram of a 3-bit binary be divided by M using N number of flipflops

in a ripple binary counter if M can be expressed as M = 2N where N is an integer. If the input clock applied at the clock input of the 1st flipflop has frequency f then the Q output of the Nth flipflop will produce a digital output at the rate of f/M = f/(2N).

The count sequence table (Fig. 11.4) and the timing diagram (Fig. 11.3) show that the decimal equivalence of the 3-bit binary output (Q2Q1Q0) or state of the counter. These decimal numbers represent the number of clocks which have been applied to this counter to reach the state of the counter. Hence, the name counter is used for this type of circuit. If these 3-bit outputs (Q0 as LSB and Q2 as MSB) are converted into decimal using binary-to-decimal converter and are displayed using display devices then we can visualize the progress of the count with clocks. For a 3-bit binary counter the total number of states are 8 = (23) and this counter can count upto 8 clock pulses. When the 8th external clock pulse is applied then this 3-bit counter circuit goes back to its initial state Q2Q1Q0 = 000 and becomes ready for the next cycle. The state diagram for the 3-bit counter is shown in Fig. 11.5. For this reason the 3-bit binary counter is called a MOD-8 Counter. Also, this counter is called Full Sequence Length Counter because this 3-bit counter passes sequentially through the complete 3-bit binary sequence. This particular counter circuit is also known as–UP Counter because, while counting, the count value increases. For this 3-bit counter the count has started from Q2Q1Q0 = 000 i.e. from the reset state but in general those counters will be called binary UPcounter in which the count starts from a count of N1 sequences through binary sequence and recycles after reaching the count of N2 where N2 > N1.

The timing diagram in Fig. 11.3 does not show how the propagation delays of the flipflops affect the outputs. It is clear from the above discussions that each flipflop is toggled by the change in Q output of the preceding flipflop. So, no flipflop can change its state before the propagation delay of the flipflop which precedes it. This propagation delay accumulates as we use more flipflops in the counter. This kind of operation is responsible for the name “Ripple Counter”. A given flipflop changes state when all the flipflops preceding it change their state. In effect the change of state of a flipflop gradually passes or ripples through the flipflops.

The same effect of UP counting of the binary ripple counter as discussed, can be obtained using the positive edge triggered flipflops. For this design all the flipflops should be in toggle mode as before but the interconnection of two consecutive flipflops should be done Q0 Q1 Q2PRESET
PRE PRE PRE
1 T Q1 T Q 1 T Q CLKExternal FF0
CLK
ClockCLK
FF1 FF2
Q Q CLRQCLR
CLR
Q0 Q1 Q2 RESET
Fig. 11.6 : 3-bit binary ripple upcounter using three positive edgetriggered flipflops.

by connecting Q output of one flipflop to the CLK input of the next flipflop and the outputs of the counter should be taken from the Q outputs to have the Upcounting sequence as shown in Fig. 11.6. In this circuit the FF0 toggles with each positive going edge of the external clock. The change in Q output of any flipflop from 0 to 1 causes the next flipflop to toggle. The timing diagram and the count sequence of the circuit are shown in Fig. 11.7 and Fig. 11.8 respectively. For these two figures we assume that the counter circuit starts from reset state Q2Q1Q0 = 000 or Q Q Q2 1 0 = 111.

1 2 3 4 5 6 7 8 9
Q
0
1 0 1 0 1
0 1 0 1 Q
1
1 1 0 0 1
1 0 0 1 Q2
1 1 1 1 0
0 0 0 0
0 1 0 1 0
1 0 1 0 Q0
0 0 1 1 0
0 1 1 0 Q1
0 0 0 0 1
1 1 1 0Q2
Fig. 11.7 : Timing diagram of a 3-bit binary counter using positive edgetriggered flipflops as shown in Fig. 11.6.

The circuit in Fig. 11.6 is equivalent to the circuit in Fig. 11.2(a). In the circuit of Fig. 11.2(a) the connection between two flipflops is Q to CLK but in this circuit (Fig. 11.6) the connection is between Q to CLK as if the effect of the inversion which is represented by the bubble symbol of the clock input of CLK of any flipflop is shifted to the Q output of the preceding flipflop i.e. to the Q output and the FF0 is triggered by the positive going edge instead of the negative edge of the clock because of the absence of inversion of the clock input. The timing diagram of a 3-bit binary counter designed with 3 positive edge triggered flipflops and the count sequence are shown in Fig. 11.7 and Fig. 11.8 respectively.

Two other possible ways of designing the UPcounter are shown in Fig. 11.9 and Fig. 11. 10. Though, the two circuits have been illustrated using only three T-type flipflops but it is true for N-number of such flipflops as well.

Fig.11.8 : Count Sequence of 3-bit binary counter
Fig. 11.9 : Three-bit Upcounter (Count sequence from Q, clocking Q ☐CLK)
Fig. 11.10 : Three-bit Upcounter (Count sequence from Q, clocking Q ☐ CLK)
11.2.1.2 Binary Ripple Down Counter The binary down ripple counting sequence can be obtained directly from any upcounter circuit without any change in the hardware. The count sequence of a down counter is in descending order i.e., each count sequence is complements of the sequence of the upcounter. For example, the output sequence of a 3-bit down counter is 111 ☐ 110 ☐ 101 ☐ 100 ☐ 011 ☐ 010 ☐ 001 ☐ 000. Each 3-bit output of this sequence can be obtained by complementing the bits of the Upcounter corresponding to the same clock number. For example, the output of a 3-bit Upcounter is 101 starting from 000 after the application of the 5th clock but for a down counter the output would be 010 (☐ 101 ) starting from 111 ( 000 ) after the same number of clocks. Thus, If the Q ( Q) outputs of any counter circuit produces an Upcounting sequence, Q (Q) outputs of the same circuit will produce the down counting sequence. The upcounter circuits which were discussed above can be used as down counters as shown in Fig. 11.11(a), where the outputs for both the Upcounter and Downcounter have been indicated.

Fig. 11.11(a) Here we can also see that the value of the maximum count in a 3-bit Downcounter is 7(☐ 111) and the minimum count is 0(☐ 000). In general for a Downcounter implemented with N-flip-flops the maximum decimal count is 2N—1 and the minimum is 0.

If we use the circuit connections of the Upcounter as shown in Fig. 11.2(a) as a reference then the connection for the other possible Up and Downcounters can be predicted if we remember the following rules : For the circuit in Fig. 11.11(a) for Upcounting the following three features are to be noted (a) The flipflops are all negative edge triggered.
(b) Q output of a flipflop feeds the CLK input of the next one.
(c) The counter outputs are taken from the flipflop Q outputs.

If we change any one of these three features, the circuit will be converted to a Downcounter. Change of any two features will convert the circuit into an Upcounter. Change of all three features will convert the circuit into a Downcounter.

For example, if we change the feature (a) Keeping all other features unchanged i.e. if we replace the negative edge triggered flipflops by the positive edge triggered flipflops then the counter will behave as a down counter [Fig. 11.11(c)] provided we observe the outputs

Fig. 11.11(b)
from Q2, Q1 and Q0. Similarly, if we only change the feature (b) By connecting Q to CLK

keeping all other connections unchanged then the circuit will behave as a Downcounter [Fig.11.11(b)] if we observe the output from Q2, Q1 and Q0. If we change the feature-(c) i.e. if we see the outputs from Q2, Q1 and Q0 then the count sequence will be for Downcounter form [Fig. 11.11(a).]

Fig. 11.11(c)
11.2.1.3 Binary Ripple UP/DOWN Counters On examining the counter circuit in Fig. 11.11(a) we can see that the Q outputs give us the UPcount sequence if a link is set-up between Q output of one flipflop to the CLKinput of the next and from Fig. 11.11(b) we can see that the downcount sequence is obtained Fig. 11.11(d) from the Q outputs if the connection is made between Q to CLK input. Similarly, for the counter circuits shown in Fig. 11.11(c) and Fig. 11.11(d), the Q outputs from the flipflops give us Down or Upcount sequence depending on whether we link Q output of one flipflop to CLK input of next or Q to CLK respectively. The two count sequences can be obtained from a single circuit if a 2-to-1 MUX is used between two flipflops to connect either Q or Q of one flipflop to the clock input of the next flipflop, as per the need. The two circuits using multiplexers are shown in Fig. 11.12(a) and Fig. 11.12(b). This depends on the select input S of the multiplexer. The select input of all the MUX are tied together to a common point and is labelled as UP/DOWN for the circuit in Fig. 11.12 (a) and UP/DOWN

Fig. 11.12(a)
for the circuit in Fig. 11.12(b). For the circuit in Fig. 11.12(a) when UP /DOWN input is HIGH then the link between Q and CLK is established through I1 input of the MUX and

this circuit acts as an Upcounter which becomes equivalent to the circuit in Fig. 11.11(a). When UP/DOWN input is made logic LOW then the link between Q and CLK is established and the same circuit behaves as a down counter as shown in the circuit in Fig 11.11(b). For this circuit we take the output always from Q3, Q2, Q1 and Q0.

Fig. 11.12(b) The circuit shown in Fig.11.12(b) is also One UP/DOWNcounter using all positive edgetriggered flipflops where select inputs of all the 2-to-1 MUXs are tied together and labelled asUP DOWN. When this common select input is made HIGH then the connection between Q and clock is established and this circuit acts as a downcounter as discussed using Fig. 11.11 (c). Similarly for the input UPDOWN = LOW this circuit acts as an UP counter, because Q of one flipflop is connected to the clock input of the next, as it was in Fig. 11.11(d).

In the above UP/DOWN counter circuits the direction of counting is controlled by a single control input UP DOWN or UP DOWN. But in some occasions the circuit designer may need two separate control inputs
for Up and Down counting. For this

purpose we may replace each 2-to-1

MUX by the circuit as shown in

Fig. 11.13(a). In this figure if UP = 1

and DOWN = 0 then Q output of one

flipflop can pass to the clock input of

the next but for UP=0 and DOWN=1

then Q output can pass to the clock

input of the next flipflop. Thus, for

counting in ascending order the two

control inputs should be UP=1,

DOWN=0 and for counting
descending order the control inputs Fig. 11.13(a)
should be UP = 0, DOWN=1. The
circuit of 4-bit UP/DOWN counter having separate control inputs (UP and DOWN) is shown in Fig. 11.13(b).

Another simple way of designing on UP/DOWN counter is shown in Fig. 11.13(c). The figure shows a 4-bit UP/DOWN counter that has the choice of counting UP or counting DOWN. In this figure if UP/DOWN=0 then the exclusive–OR circuit allows the Fig.11.13(b) : 4-bit UP/DOWN counter with separate control for Up and Down counting.
Fig.11.13(c) : UP/DOWN counter using Ex-Or gates between two consecutive T flipflops.

Q output without inversion to the clock input of the next. But for UP/DOWN=1, the Q output in inverted by the Ex-OR gate before it reaches the clock input of the next adjacent flipflop. Therefore, for UP/DOWN=1 the same circuit behaves as a down counter..

11.2.2 Design of Modulo Ripple Counter (or Truncated Counters)

The count sequence of different modulo ripple counters have been discussed in the preceding section with the starting state N1 and the final count N2. This means that whenever the counter tries to go to a state next to the final count N2 i.e. to a count (N2+1), then the counter is forced back to the initial state N1. Therefore, the general principle of designing any ripple truncated counter is to detect the state whose count value is (N2+1) by some suitable decoding logic circuit and to produce either logic HIGH or logic LOW output by which the counter circuit can be reloaded with initial count value N1 so that the counter circuit can start its counting again from N1 with clocks. These type of counters are called N1 to N2 counters.

If the starting state (N1) of the counter is the reset state (i.e. all Q outputs of the counter are 0) then the flipflops are cleared using the output of the decoding logic circuit when the counter reaches next to the desired final count i.e. to the (N2+1) count while counting up. This technique is used for truncated ripple Upcounter i.e. for 0-to-N2 type counters.

Similarly, the truncated down counters return to the set state (all Qs are 1s) after it reaches temporarily to a state next to the desired final count N2 i.e. to (N2+1). A decoding logic circuit generates, either a LOW or HIGH output using the state (N2 + 1). This output from the decoding logic circuit and the preset inputs of the flipflops sets all the Q outputs to 1 i.e. the counter starts from the set state.

We can classify the MOD-N counters mainly into three categories.
(1) MOD-N counter which starts from an initial count N1 = 0, counts upto N2 and recycles back to N1 with N numbers of clocks where N = N2 -N1 +1. This type of counter is known as MOD-N Upcounter.

(2) MOD-N counter which starts from an initial count N1 = 2n - 1 (where n is the number of flipflops in the counter circuit), counts down to N2 and recycles back to N1 with N-number of clocks where N = N2 -N1 +1. This counter is known MOD-N Down counter.

(3) MOD-N counter which starts from a count N1, counts-up to N2 and recycles to N1 with clocks where number of clocks for one complete cycle are N = N2 -N1 +1. Then this counter is called N1-to-N2 counter. In this case N1☐ 0 and N2 ☐ 2n–1.

Following are some illustrations for the above type of counters :
◆ MOD-3 Asynchronous Counter (i) MOD-3 Asynchronous (Ripple) Counter

To design a MOD-3 asynchronous counter we need two flipflops because the MOD number N(=3) is greater than 2(=21) but less than 4(=22). For this design, JK or D-type flipflops can be used but the flipflops should be converted to T-type. Both flipflops are assumed to have activelow clear (CLR ) inputs. Q1 and Q0 are the outputs of the flipflops. Q0 is the output from the flipflop of least significant position and Q1 is the output from the flipflop of next higher significant position.

◆ MOD-3 Asynchronous UPCounter

Two T-flip-flops are connected in the asynchronous mode as shown in Fig. 11.14(a) i.e. Q0 output of FF0, drives the clock input of FF1 and the clock input of FF0 is connected to the external clock. The activelow preset inputs (PRE ) of the flipflops are kept inactive by connecting them to Logic-1 because they will not be used for the design of MOD-3 UPcounter. The two activelow clear inputs (CLR ) of the flipflops are connected together. In the absence of the 2-input NANDgate, the circuit shown in Fig. 11.14(a) would represent a MOD-4 UPcounter having a count sequence Q1Q0=00, 01, 10, 11, 00, 01 ... and so on. But

in case of MOD-3 UPcounter we
have to truncate this count sequence

at Q1Q0 = 10, so that the counter can

come back to the initial state Q1Q0 =

00 from Q1Q0 = 10 when the 3rd

external clock is applied. Therefore,

for a MOD-3 UPCounter the desired

count sequence is—

Fig.11.14(a)
But the transition from the state Q1Q0 = 10 to 00 of the MOD-3 counter will not occur smoothly because when the 3rd clock is applied, the tendency of this counter will be to enter
Fig.11.14(b) Q1Q0 = 11. The count sequence is shown in Fig. 11.14(b) and the state diagram is shown in Fig 11.14(c). Fig. 11.14(a) shows that when the counter enters Q1Q0 = 11, the NANDgate will produce a LOWoutput and this LOWoutput will clear both the flipflops to make Q1 = 0 and Q0 = 0 as the output of the NANDgate is connected to activelow clear (CLR) inputs of the two flipflops. For the other three states (Q1Q0 = 00, 01 and 10) of the counter the output of the NAND remains HIGH and will not affect the clear inputs of the flipflops and the counter will remain in the count mode. The temporary entry of the counter to the state Q1Q0 = 11 will produce a glitch at Q0 because the clearing action will be effective after a delay which is the sum of the propagation delay tPHL of the NANDgate and tp(CLR-to-Q)of flipflop FF0. During this short time the Q0 will temporarily remain HIGH. Therefore, the width of the glitch at Q0 will be ☐t = tPHL(NAND) +tp(CLR-to-Q). The timing diagram is shown in Fig.11.14(d). In this diagram the propagation delay tp(CLK-to-Q) of the flipflops has been neglected for drawing the output Q0 and Q1. Once the flipflops are cleared (Q1 = Q0 = 0), the output of the NANDgate goes HIGH after another delay tPLH(NAND). Thus, all the CLR inputs become inactive again and counting starts from the state Q1Q0 = 00 again.

Fig.11.14(c)
Fig.11.14(d) : Timing diagram oif MOD-3 up asynchronous counter

From the timing diagram Fig. 11.14(d) it can be observed that for every group of 3 clock periods = 3T one positive pulse is obtained at Q1 having width tw=T + tPHL(NAND)+tp(CLR-to-Q) of FF0. If the propagation delays are neglected then tw = T. Therefore, the frequency of the waveform at Q1 is one-third of the clock frequency (f ) of the external clock. Hence, this counter may also be called divide-by-3 counter.

◆ MOD-3 Asynchronous DOWN Counter

The same circuit [Fig. 11.14(a)] can be converted into a MOD-3 downcounter if the Q1 and Q0 of the flipflops are considered as the counter outputs. The count sequence, state diagram and the timing diagram, when this circuit is used as Mod-3 downcounter are shown in Fig. 11.15. In this circuit a negative glitch is observed at Q0 of width t = tPHL(NAND) + tp(CLR-to-Q) .

Fig.11.15(a):Count Sequence of Fig.11.15(b):State disagram of Fig. 11.15(c):Timing diagram of MOD-3 MOD-3 downcounter MOD-3 downcounter downasynchronous(Ripple)counter.

Another way of designing the MOD-3 asynchronous Up or Downcounter is shown in Fig. 11.16. Outputs from Q1 and Q0 gives us the Downcounter sequence and the Upcounter sequence is obtained from Q1and Q0from same circuit. We assume that the flipflops start from the initial SET state i.e. Q1 = Q0 = 1. In this circuit the OR-gate generates a LOW

Fig. 11.16 : MOD-3 Up and downcounter. Fig.11.17 : Timing diagramforthecircuitinFig.12.16.

output only when Q1 = Q0 = 0. This sets the flipflops to Q1 = 1, Q0 = 1 using the activelow PRE inputs of the flipflops. Otherwise the OR-gate output is always at high level. The timing diagram for the circuit in Fig 11.16 is shown in Fig. 11.17.

◆ MOD-5 Asynchronous (Ripple) Counter MOD-5 ripple counter needs 3 flipflops because the MOD number N (=5) of this counter is 4 < N < 8. JK or D flipflops can be used but they should be converted into T-type as discussed earlier. Using 3-flipflops the maximum count length will be 8 (= 23) but in case of MOD-5,the count length is 5. Therefore, we need a feedback arrangement to truncate the count length from 8 to 5.

The count sequence for MOD-5 UP and DOWN counters is shown in Fig. 11.18(a) and (b) respectively. The circuit for the MOD-5 counter is shown in Fig. 11.24 where the feedback is obtained Fig. 11.18 : Count sequence of (a) MOD-5 UP ripple counter (b) MOD-5 DOWN ripple counter.

using a 2-input NANDgate to truncate the count sequence. The inputs to this NANDgate are from Q0 and Q2 and the output of the NANDgate is connected to the activelow clear (CLR) inputs of all the flipflops. The Q0 output of the flipflop FF0 is the least significant bit and the Q2 output of FF2 is the most significant bit of 3-bits of the count

sequence. In this counter circuit we assume that the UPcounting sequence starts from the reset state Q2Q1Q0 = 000 and the DOWNcounting sequence starts from the set state Q2Q1Q0 = 111.

◆ MOD-5 UP Asynchronous (Ripple) Counter Starting from the reset state (Q2Q1Q0 = 000) the UPcounter passes through the count states Q2Q1Q0 = 000 ☐ 001 ☐ 010 ☐ 011 ☐ 100 with clocks and recycles back to the starting state Q2Q1Q0 = 000 from 100 when 5th clock is applied. This is shown in Fig.11.18(a). The circuit for the MOD-5 counter is shown in. Fig. 11.19. To get the UPcount sequence consider the outputs from Q2, Q1 and Q0. Therefore, for Upcounting N1 = 0 and N2 = 4 and the MOD-number of the counter is N = N2-N1 + 1 = 5. For these 5 states (000 through 100) the NANDgate output is always HIGH and the clearing action of the flipflop remains inactive. When the 5th clock is applied this counter does not go directly from the state Q2Q1Q0 = 100 to 000 because the natural tendency of this counter is to enter the state, 101 when the counter receives the 5th clock. But when the counter enters this state the Q0 and Q2 of the flipflops FF0 and FF2 becomes HIGH and the 2-input NANDgate generates a LOW output after a propagation delay tPHL(NAND) and hence these two flipflops will be cleared (Q0 = Q2 = 0) after another delay tp(CLR-to-Q). Thus, the UPcounter returns to the initial state Q2Q1Q0 = 000 after a total delay time☐t1= tPHL(NAND)+tp(CLR-to-Q) measured from the falling edge of the 5th clock.

Fig. 11.19 : MOD-5 asynchronous Up and Down counter Once the counter returns to the state Q2Q1Q0 = 000, the output of the NANDgate again becomes HIGH after a further delay tPLH(NAND). This makes the CLR input of the flipflops inactive again and fresh counting starts from Q2Q1Q0 = 000 with clocks. The total time

spends by this circuit in the

state Q2Q1Q0 = 101 is ☐t =

tPHL(NAND) + tp(CLR-to-Q). So, a

glitch or a narrow spike is

observed at Q0. The timing

diagram in Fig. 11.25 shows the

variation of the outputs Q0, Q1

and Q2 and the NANDgate

during Upcounting. In this

diagram the propagation delay

tp(CLK-to-Q) of the flipflops has

been neglected for simplicity.

This resetting technique

from the state which is next to

the last state of the count

sequence (in MOD-5 Up

counter the last state is 100) of

Fig.11.20 : Timing diagram for MOD-5 UP and DOWNcounter. a MOD-N counter is called state-decoding. For MOD-5 counter the 2-input NANDgate is acting as a decoder to decode the combination of two 1s from the state Q2Q1Q0 = 101 which is just next to the last count Q2Q1Q0 = 100 (☐N2). This two 1s at Q2 and Q0 has not occured anywhere before and this is unique only in the state 101. Thus, a low pulse is generated after decoding this unique combination for clearing all the flipflops simultaneously.

◆ MOD-5 Asynchronous (Ripple) DOWNCounter If the complements of Q2, Q1 and Q0 are considered as the outputs as shown in Fig. 11.21 then the same circuit will give

us the count sequence of the

MOD-5 asynchronous down

counter. The timing diagram of

Fig. 11.20 also shows the

variation of Q2, Q1 and Q0. In

the Downcounter a negative

glitch is observed at Q0 output

of FF0.

Note : In the above circuit

it is seen that the decoding is

done using the two 1s from the

output Q2 and Q0 when the

counter circuit temporarily

MOD-5 Up counting sequence enters the state Q2Q1Q0 = 101. Fig. 11.21 : MOD-5 asynchronous Up and Down counter.

After decoding, a low pulse is generated and this low pulse is applied to the CLR inputs of the three flipflops. But for this particular circuit it is not necessary to apply a low pulse to the CLR input Q1 because it is already in the reset state when it enters the state 101. Therefore, connecting the CLR inputs of FF0 and FF2 to the output of the NANDgate and CLR input of FF1 to Logic-1, the same counting sequence can be obtained.

Another circuitwhich can alsobe used forthe MOD-5 asynchronousUpand DOWNcounter is shown in Fig.11.21. In this circuit the Q outputs of the flipflops provide the downcounting sequence and the Q outputs of the flipflops provide the upcounting sequence. This circuit is assumed to start from a state Q2Q1Q0 = 111 and follow the count sequence of a 3-bit downcounter. The OR-gate connected in the circuit of Fig. 11.21 produces a 0 output only whenthis circuitreaches Q2Q1Q0= 010aftertheapplication ofthe 5thexternalclockand generates 1 at all other times. Thus, this circuit recycles to the initial state Q2Q1Q0=111 after it enters the state 010 momentarily because the 0 output of the OR-gate for this state sets all the flipflops using the activelow preset inputs. In this circuit we may omit the connection of the OR-gate output to the PRE input of FF1 because Q1 is already in the State-1 in the decoded state 010. Thus, for this MOD-5 DOWNcounter the count sequence is 111☐ 110☐ 101☐ 100☐ 011☐ 111☐ ...

◆ MOD-10Asynchronous(Ripple)Counter(orDecadeCounterorBCDCounter): This counter needs 4-flip-flops because the MOD number of this counter is N = 10 which is ☐ 23 but ☐ 24. The count sequence of a MOD-10 asynchronous (ripple) Upcounter is shown in Fig 11.22(a). This counter starts from a state Q3Q2Q1Q0 = 0000 (☐ 010 = N1) reaches a count Fig.11.22(a) : Count sequence
of MOD-10 counter.

Q3Q2Q1Q0 = 1001 (☐ 910 = N2) sequentially with 9 clocks and comes back to the initial count N1 after the application of the 10th clock. If this 4-bit counter is allowed to count normally following the binary sequence then this counter would reach the maximum count Q3Q2Q1Q0 = 1111 after 15 external clocks and would recycle to Q3Q2Q1Q0 = 0000 after the application of the 16th clock. But for the MOD-10 counter all the flipflops are cleared forcibly whenever this counter enters the state Q3Q2Q1Q0 = 1010. This is done by producing a Logic-0 output from an extra logic circuit. This logic circuit decodes the state 1010 and generates a logic-0 output. It may be noted from the count sequence [Fig 11.22(a)] that Q3 and Q1 become Logic-1 only in the 1010 state. Therefore, if a 2-input NANDgate is used with its two inputs from Q3and Q1then 0 will be produced whenever the counter circuit enters the state 1010. The Fig 11.22(b) shows required circuit and Fig. 11.22(c) shows the timing diagram.

A glitch is observed at Q1. This happens when the 10th clock is applied. When 10th clock is applied then, the counter tries to make a transition from a state 1001 to 1010 so that the state of Q1 changes from 0 to 1 but the 0 output of the NANDgate forces Q1 to go to 0 again.
Fig.11.22(b) : Logic circuit of a MOD-10 Counter.

Thus, Q1 remains at 1 for a short time. The width of this glitch at Q1 is the sum of the propagation delay (tPLH) of the NANDgate and the propagation delay tFF(CLR-to-Q)of the flipflop FF1. After the flipflops are cleared (Q3Q2Q1Q0 = 0000), the NANDgate output again jumps to 1 after a propagation delay of tPLH. This renders the clear inputs of the flipflops inactive and allows the circuit to start its counting from Q3Q2Q1Q0 = 0000. The expanded view of the 10th clock is shown in Fig. 11.22(d). From the timing diagram it is clear that for every group of 10 clocks the output Q3 gives one pulse, Q3 goes high at the 8th falling edge and goes low at the 10th falling of the external clock if the effects of the propagation delay is neglected. Thus, the pulse rate at Q3 is one tenth of the external clock rate. So, this counter is also known as a Divide - by - 10 circuit or a BCD counter or a Decade counter since this circuit counts only 10 clocks and generates one pulse at Q3 per 10 clocks. In this circuit the NANDgate output can be connected to the CLR inputs of FF1 and FF3 leaving the CLR inputs of FF0 and FF2-to-Logic-1. The duty cycle of the output Q3 is 20% because Q3 remains low for 8 clock periods and high for 2 clock periods.

Fig. 11.22(c) :
Timing diagram of a MOD-10 asynchrous (ripple) Upcounter.
Fig. 11.22(d):Expanded view on the 10th clock.
11.2.3 Glitch free Resetting of Asynchronous Counters We have seen that the premature termination of the binary sequence for designing different modulo asynchronous counters causes glitches at the Q outputs. There is another resetting technique by which we can have glitch free resetting in MOD-N asynchronous counters.

Following are some illustrations for using this new resetting technique in designing different MOD-N asynchronous counters. This technique uses one extra flipflop. Fig. 11.23(a) shows the MOD-10 asynchronous Upcounter. It is clear from the circuit that the 2-input AND gate produces 1 at its output whenever the counter circuit enters the state Q3Q2Q1Q0 = 1001 after the application of the 9th falling edge of the external clock. For all counts from Q3Q2Q1Q0 = 0000 to 1000, output of this ANDgate remains 0 and hence J input Fig. 11.23(a) : Glitch free MOD-10 asynchronous Upcounter.

of the flipflop FF4 is 0 upto the count of 1000. When the 9th clock is applied the counter output becomes 1001 and ANDgate output goes. HIGH and FF4 enters the toggle mode (J = K = 1). Therefore, upto the 9th clock the output Q4 of FF4 remains 1 but the rising edge (edge ‘a’) next to the 9th clock (falling edge for FF4 because of the inverter) causes FF4 to toggle i.e. Q4 becomes 0. This clears all the four flipflops of the counter and the output of the AND -gate again becomes 0. This is shown in the timing diagram in Fig. 11.23(b). The falling edge (edge ‘b’) next to this rising edge (edge ‘a’) has no effect on the counter (flipflops FF0, FF1, Fig.11.23(b) : Timing diagram for the circuit in Fig. 11.23(a).

FF2, FF3) and the flipflop FF4. The rising edge (Edge ‘c’) next to this, again resets FF4 i.e. Q4 becomes 1 because J input became 0 at the Clock-edge-’a’ and the K input is always at 1. So, the counter comes out of the clear mode and starts counting from the next falling edge (Edge’d’) of the clock. The timing diagram shows that the counter is not allowed to enter the spurious state 1010, so the glitch is absent in the circuit.

Let us consider another truncated counter circuit as shown in Fig 11.24(a). This is a circuit of a MOD-5 counter.

To design the glitch free MOD-5 asynchronous counter we have to check for the 1s in the state Q2Q1Q0 = 100. There is a single 1 in the state Q2Q1Q0 = 100. Therefore, the output Q2 of FF2 can be directly connected to the J input of the resetting flipflop FF3. The K-input

of FF3 is always connected to Logic 1. The timing diagram is shown in Fig.11.24(b). This diagram shows that the Q3 output of FF3 goes low at the next rising edge (Edge-‘a’ ) after Fig. 11.24(a) : Glitch free MOD-5 asynchronous upcounter.

the 4th falling edge of the clock, and therefore all the flipflops are cleared. This happens because at the 4th falling-edge the state of the counter becomes Q2Q1Q0 = 100 and hence J input of FF3 becomes 1 as Q2 is connected to the J input. The 5th falling edge (Edge-‘b’) has no effect on the counter because Q3 is still 0 and the counter flipflop are in the reset state. The rising (Edge-‘c’) causes the flipflop FF3 to toggle (Q3 = 1) as due to resetting the output Q2 is low and hence J is low before this rising edge. The counter now comes out of the clear mode and counting starts from the next falling Edge - ‘d’ as usual.

Fig. 11.24(b) : Timing diagram for the circuit in Fig. 12.24(a).

One important point to be noted for the MOD-N glitch free asynchronous truncated counter (MOD-N) circuit is that we have to AND all 1s of the state (N–1) and the output of the ANDgate should be connected to the J input of the resetting flipflop but for the circuit with NANDgate as the decoding logic circuit for the counter with glitch we have to use the 1s of the state equivalent to the count of N. For example, in case of MOD-10 glitch free counter we have used the AND of 1s of the count of N–1 = 10–1 = 9 (☐1001) and in case of MOD-5 counter we have used 1 of the count (5-1) = 4 ☐ 100 i.e. Q2 directly to the J input of the resetting flipflop.

Design a glitch free MOD-12 ripple counter.

For this problem, the MOD number is N=12. So, we have to use the 1s of the state N-1 = 1110☐ 1011 for ANDing them together and use the output of the ANDgate as the J input of the resetting JK flipflop FF4 as shown in Fig. 11.25. The Q output, of this resetting flipflop is to be connected to the active low clear inputs of the JK flipflops (FF0 to FF3) of the 4-bit ripple counter. The complete circuit for this is shown in Fig. 11.25.

Fig. 11.25 : Glitch free MOD-12 ripple upcounter.
11.3 SYNCHRONOUS COUNTERS

The main differences in the characteristics of an asynchronous and synchronous counters are the connections to the external clock inputs of the flipflops and the control inputs (J and K for JK flipflops, D for D-flip-flops T for T-flip-flops etc.) of the flipflops. In case of asynchronous counter all the flipflops are wired as T flipflop and the states of the flipflops are changed by the changing Q output of the previous stage. But in case of synchronous counters, the flipflops are all clocked simultaneously from a single clock source i.e. synchronously and the J and K inputs of each flipflop are supplied by the outputs of some external combinational logic circuit and the inputs to this external logic circuit are the Q outputs of the flipflops. The structure of a synchronous counter is shown in Fig. 11.26. Thus, the designing of a synchronous counter actually means to find out the combinational circuit, whose outputs are the J and K inputs of the flipflops and the inputs to the combinational circuit are the Q outputs from the flipflops. As we know from the transition table that J and K inputs of a flipflop depend on the present state Q and the next state Q+. Therefore the logic components of the combinational logic circuit can be determined if the present and the next states of the counter are known to the circuit designer.

The glitches in the synchronous counters are avoided since all the flipflops are clocked simultaneously. If the flipflops of a synchronous counter do not have equal propagation delays then all of them will not change their Q outputs at the same time even though they are clocked simultaneously. For this reason, the synchronous counter will also have some temporary unstable state. But fortunately the propagation delays of the flipflops are not additive in case of synchronous counter because the flipflops are clocked simultaneosuly. The propagation delay of the added combinational circuit will not affect the states because the combinational circuit comes into play after a change in Q when the flipflops are already clocked. The glitches can be completely avoided in a synchronous counter if the time gap between two consecutive clock edges is greater than the sum of delay producing next state Q+ from the present state Q of flipflop and the delay of the combinational circuit to produce inputs for the flipflops.

Combinational Logic Circuit
Q0 Q1 Q2
Q3 1
11 1
PRE
PRE PRE PRE J Q J Q J Q J Q Ext
Clock (f)
CLK FF0 CLKFF1 CLKFF2 CLKFF3
K Q
K Q KCLR Q KQCLR
CLR CLR 1
1 1 1
Fig. 11.26 : General Circuit of a Synchronous Counter.
Before going into the synthesis problem of the synchronous counters let us analyze a few synchronous counters to see how it works.
11.3.1 Analysis of a 3-bit Synchronous Binary UP Counters Logic circuit for a 3-Bit synchronous binary Upcounter is shown in Fig. 11.27. Let us analyze the circuit step-by-step to understand how the different J and K inputs for the flipflops are generated for different state transitions with simultaneous external clocking so that this counter can follow the 3-bit binary sequence of an Upcounter.

Q21
Q0 Q1 1 1
J0 PRE
PRE J PRE J Q
J1 J Q2 J QExt. 1
Clock
CLK FF0
CLK FF1 CLK FF2 K0
K1 K QK2 K Q1 K Q
CLR
CLR CLR 1
1 1 Fig.11.27 : Logic circuit of a 3-bit synchronous binary Upcounter. Assume that the counter is initially in the reset state i.e. Q0 = Q1 = Q2 = 0 before the application of any clock. The action of the circuit is described below in Table 11.1.

1. Before the applicationof anyclock : Q0 = 0, Q1 = 0, Q2 = 0
J0 = K0 = 1 (FF0 is in toggle mode)
J1 = K1 = Q0 = 0(FF1 is in nochange mode) J2 = K2 = Q0.Q1 = 0 (FF2 is nochange mode) 3. Before the applicationof2ndclock: Q2Q1Q0 = 001
J0 =K0 = 1, (toggle mode)
J1 = K1 = Q0 = 1, (FF1 is in toggle mode) 2. After the application ofthe 1st clock : Q0 : 0☐ 1 (as FF0 was in toggle mode) Q1 : 0 ☐ 0 (as FF1 was in nochange mode) Q2 : 0 ☐ 0 (as FF2 was in nochange mode) So, Q2Q1Q0 = 001 after the 1st clock 4. Afterthe applicationof the 2nd clock: Q0 : 1☐ 0 (as FF0 was in toggle mode) Q0 : 0☐ 1 (as FF1 was in toggle mode) Q0 : 0 ☐ 0 (as FF2 was in nochange mode) J2 = K2= Q0Q1=1.0 = 0, (FF2 is in nochange mode) So, Q2Q1Q0 = 010 after the 2nd clock 5. Before the applicationof3rdclock: 6. Afterthe applicationof 3rdclock:
Q2Q1Q0 = 010
J0 = K0 = 1, (FF0 is in toggle mode)
J1 = K1 = Q0 = 0,(FF1 is in nochange mode)
J2 = K2 = Q0Q1 = 0.1 = 0, (FF2 is in nochange mode) Q0 : 0 ☐ 1(as FF0 was in toggle mode) Q1 : 1 ☐ 1 (as FF1 was in nochange mode) Q2 : 0 ☐ 0 (as FF2 was in nochange mode) So, Q2Q1Q0 = 011 after the 3rd clock 7. Before the applicationof4thclock:
Q2Q1Q0 = 011
J0 = K0 = 1, (FF0 is in toggle mode)
J1 = K1 = Q0 = 1,(FF1 is in toggle mode)
J2 = K2 = Q0.Q1 = 1.1 = 0, (FF2 is in toggle mode) 8. Afterthe applicationof 4thclock : Q0 : 1☐ 0 (as FF0 was in toggle mode) Q1 : 1☐ 0 (as FF1 was in toggle mode) Q2 : 0☐ 1 (as FF2 was in toggle mode) So, Q2Q1Q0 = 100 after the 4th clock

9. Before the applicationof5thclock: 10. Afterthe applicationof 5thclock : Q2Q1Q0 = 100
J0 = K0 = 1, (FF0 is in toggle mode)
J1 = K1 = Q0 = 0,(FF1 is in nochange mode) J2 = K2 = Q0.Q1 = 0.0 = 0, (FF2 is in nochange mode) Q0 : 0☐ 1 (as FF0 was in toggle mode) Q1 : 0 ☐ 0 (as FF1 was in nochange mode) Q2 : 1 ☐ 1 (as FF2 was in nochange mode) So, Q2Q1Q0 = 101 after the 5th clock 11. Before the applicationof6thclock: 12. Afterthe applicationof 6thclock : Q2Q1Q0 = 101
J0 = K0 = 1, (FF0 is in toggle mode)
J1 = K1 = Q0 = 1,(FF1 is in toggle mode)
J2 = K2 = Q0.Q1 = 1.0 = 0, (FF2 is in nochange mode) Q0 : 1☐ 0 (as FF0 was in toggle mode) Q1 : 0☐ 1 (as FF1 was in toggle mode) Q2 : 1 ☐ 1 (as FF2 was in nochange mode) So, Q2Q1Q0 = 110 after the 6th clock 13. Before the applicationof7thclock: 14. Afterthe applicationof 7thclock : Q2Q1Q0 = 110
J0 = K0 = 1, (FF0 is in toggle mode)
J1 = K1 = Q0 = 0,(FF1 is in nochange mode) J2 = K2 = Q0.Q1 = 0.1 = 0, (FF2 is in nochange mode) Q0 : 0☐ 1 (as FF0 was in toggle mode) Q1 : 1 ☐ 1(as FF1 was in nochange mode) Q2 : 1 ☐ 1 (as FF2 was in nochange mode) So, Q2Q1Q0 = 111 after the 7th clock 15. Before the applicationof8thclock: Q2Q1Q0 = 111
J0= K0 = 1, (FF0 is in toggle mode)
J1= K1 = Q0 = 1,(FF1 is in toggle mode) J2= K2=Q0.Q1= 1.1= 1, (FF2 is in toggle mode) 16. Afterthe applicationof 8thclock : Q0 : 1☐ 0 (as FF0 was in toggle mode) Q1 : 1☐ 0 (as FF1 was in toggle mode) Q2 : 1☐ 0 (as FF2 was in toggle mode) So, Q2Q1Q0=000 initial state after 8th clock
Table 11.1 : Circuit actions for a 3-bit Synchronous Binary Upcounter of full sequence length.
By studying the above, table carefully we can now draw the timing diagram (Fig. 11.28) and a state table (Table 11.2) for the 3-bit Synchronous Binary Upcounter.
1 2 3 4 5 6 7 8 Ext.
Clock
Q
0 1 0
0
1 0 1 0 1 0
Q 0 0
1 1 0 0 1 1 0 1
Q
0
2
0 0 0 1 1 1 1 0
Fig.11.28 : Timing diagram of a Synchronous 3-bit Binary Upcounter.

This table and the timing diagram show that— (i) Q0 toggles with each falling edge of the clock. It happens because FF0 is permanently wired in toggle mode (J0 = K0 = 1).

(ii) Q1 toggles with the falling edge of the clock if and only if Q0 is 1 just before the appearance of the falling edge of the clock to FF1. This happens because the J and K inputs of FF1 are connected to Q0.

(iii) Q2 toggles with the falling edge of the clock if and only if Q0 and Q1 are 1 just before the appearance of the falling edge of the clock to FF2. This happens because the J and K inputs of FF2 are connected to the output of the ANDgate whose inputs are Q0 and Q1.

Q2 Q1 Q0

0 0 0
CLK 1

0
0 1CLK 2 0 1 0CLK 3
0
1 1CLK 4 1 0 0CLK 5 1 0 1

CLK 6 1 1 0
CLK 7

1
1 1CLK 8 0 0 0

Table 11.2 : State table of a synchronous 3-bit binary UpCounter.

There is a simple progression of algebraic expression for J and K inputs of a synchronous binary counter completing the full length of binary sequence. Thus, for a N-bit synchronous binary Upcounter we may write J0 = K0 = 1,
J1 = K1 = Q0
J2 = K2 = Q0Q1
J3 = K3 = Q0Q1Q2

J4 = K4 = Q0Q1Q2Q3,
................................................
JN-1 = KN–1 = Q0Q1Q2Q3 ........ QN–2 ... ... (11.1) The above method of designing the synchronous Binary Upcounter is called the Parallel Method. This is so called because the J and K inputs of i-th flipflop is the output of an ANDgate whose inputs come in parallel from all the Q-outputs of the previous stages (i = 0 to i–1).

A disadvantage of this type of connection is that the number of inputs to the ANDgate increases as the number of stages increases. For example, in a N-stages synchronous binary Upcounter wired using parallel method, the number of inputs to the ANDgate driving J and K inputs of the flipflop of the last stage is (N-1), for N☐ 2. This number of inputs are limited from the consideration of Fan-In of the ANDgate.

To reduce the number of inputs to the ANDgate we can modify the expressions of the J and K input in Eqn (11.1) as follows : J0 = K0 = 1,
J1 = K1 = Q0,
J2 = K2 = Q0Q1 = Output of the 1st ANDgate

J3 = K3 = (Q0Q1)Q2 = (Output of the 1st ANDgate). Q2 = Output of the 2nd ANDgate J4 = K4 = (Q0Q1Q2)Q3 = (Output of the 2nd ANDgate). Q3 = Output of the 3rd ANDgate
.
.
.

JN–1 = KN–1 = (Q0Q1 ... QN–3).Qn–2
= [Output of the (N–3)th ANDgate].QN–2
= Output of the (N–2)th ANDgate ... ... (11.2) Based on the modified expression in Eqn (11.2) we can now draw the circuit for a multibit synchronous Binary UpCounter. Fig.11.29 shows a 5-bit Synchronous Upcounter. This method of connection is called the Serial Method. In the serial method the number of inputs to the ANDgate is always limited to two, irrespective of the number of stage in the counter.

Q0 Q1 Q2 Q3 Q4
Q0Q1 Q0Q1Q3
1 1 11
1
PRE Q0 J1 Q J2 Q J3 Q J4 QExt 1PRE
PRE PRE PRE J0 Q
Clock
CLKFF0
CLK FF1 CLK FF2 CLK FF3 CLK FF4
1 K
K2 QK2 QK3 QK4 Q0 Q
CLR
CLR CLR CLR CLR 1
1 1 1 1
Fig.11.29 : Logic circuit for a 5-bit Synchronous Binary Upcounter using serial method.
11.3.2 Analysis of a 4-bit Synchronous Binary Down Counters Analysis of a 4-bit Synchronous Binary Down Counters bit synchronous downcounter if we observe the outputs Q2, Q1 and Q0 of the three flipflops of the 3-bit synchronous Upcounter. But the down counters can be constructed in almost the same manner as full sequence synchronous Upcounters if we like to observe the down count sequence from the Q-outputs of the flipflops, not from the Q -outputs. The only difference is that the J and K inputs are driven by the output of the ANDgate whose inputs are connected to the Q outputs of the flipflops, rather than the Q-outputs as was done in case of the synchronous full sequence Upcounter. The circuit in Fig. 11.30(a) and (b) represent 4-bit parallel and serial synchronous binary downcounters respectively.

Q0 Q1 Q2 Q3
1
1 11
J0 J PRE
J
1
PRE
J FF1J FF2Q 3 J QExt.
1 FF0 Q Q J2 PRE J PRE
Clock (f)
CLK CLK
CLK CLKFF3
1KK0 K
QQ0 K1 K QQ1 2 K QQ2 K3 K Q CLR
CLR CLR CLR 1 1 1 1 Q0 Q2
1
Fig. 11.30(a) : 4-bit parallel synchronous binary downcounter. From the diagram in Fig. 11.30(a), we can derive the following equations for the J and K inputs of the flipflops :
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q0 Q1 J3 = K3 = Q Q Q2

Q0 Q1 Q2 Q3 1
1 1 1
J0 PRE
J FF0
J PREQ 2 J PREQ J3 J FF3 QExt. 1 Q
J1 J PRE
FF1 FF2Clock (f)
CLK CLK
CLK CLK K
10 K Q
Q0 K1 K Q Q1 K2 K Q Q2 K3 K Q
CLR
CLR CLR CLR 1
1 11
Q0Q1 2
Q
0
Q
Q 1
Fig. 11.30(b) : 4-bit serial synchronous binary downcounter.

Like the synchronous upcounters the expressions of the J and K inputs for the Nbit synchronous DOWNCounter can be written as—
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q0 Q1

.
.
.

JN–1 = KN–1 = Q0 Q0....QN-2

These equations can be used to generate the necessary J and K inputs, for a change from one count-to-another for a down counting. This has been shown in Table 11.3 for a 4-bit synchronous DOWNCounter.

Q Outputs J and K Q Outputs Before clock Pulse Before Clock Pulse After Clock Pulse Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0 Q3 Q2 Q1 Q0

1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0
1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 1
1 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0
1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1
1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 0
1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 1
1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1
0 1 1 1 0 0 0 0 0 0 1 1 0 1 1 0
0 1 1 0 0 0 0 0 1 1 1 1 0 1 0 1
0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0
0 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1
0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Table 11.3 : Partial count sequence of a 4-bit synchronous downcounter. From the above table the following features for the downcounter are observed : (i) Q0 of FF0 toggles with each falling edge of the clock because J0 and K0 inputs of FF0 are permanently connected to Logic-1.
(ii) Q1 of FF1 toggles with the falling edge of the clock if and only if Q0=1 (i.e. Q0=0)
before the falling edge of the clock since Q0 is connected to J1 and K1. (iii) Q2 of FF2 toggles with the falling edge of the clock if and only if Q0 and Q1 are
both 1 (i.e. Q0 = 0 and Q1 = 0) before the falling edge of the clock as since Q Q0 1
is connected to J2 and K2
(iv) Q3 of FF3 toggles with the falling edge of the clock if and only if Q , Q0 1 , and Q2
are all 1 (i.e. Q0 = Q1 = Q2 = 0) before the falling edge of the clock since the
Q Q1.Q2is connected to J3 and K3.

0

Based on the Table 11.3 we can now draw the timing diagram, state table and the state diagram of a 4-bit synchronous DOWNCounter. These are shown in Fig. 11.31(a), (b) and (c) respectively.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 1
Q1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
Q2 1 1
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1
Q3 1 1
1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
Fig.11.31(a) : Timing diagram of a 4-bit synchrounous binary downcounter.

Q3Q2 Q1 Q0 1 1 1 1CLK 1
CLK 2 1 1 1 0 1 1 0 1CLK 3

CLK 4 1 1 0 0

CLK 5 1 0 1 1
CLK 6 1 0 1 0

CLK 7 1 0 0 1
CLK 8 1 0 0 0

CLK 9 0 1 1 1 CLK 10
0 1 1 0

CLK 11 0 1 0 1 CLK 12 0 1 0 0

CLK 13
0 0 1 1

CLK 14 0 0 1 0
CLK 15 0 0 0 1

CLK 16 0 0 0 0
Recycles
1 1 1 1 1111 1110
0000Q ☐
3Q2Q1Q0 1101
0001
1100
0010
1011
0011
1010
0100
1001
0101
1000
0110 0111

Fig.11.31(b) : State table of a 4-bit synchronous binary down counter.

Fig.11.31(c) : State diagram of a 4-bit synchronous binary downcounter
◆ MOD-3 Synchronous Counter : This counter needs 2 flipflops because the MOD number of this counter is less than 22 but greater than 21. The used and the unused states are shown separately in next state table (Table 11.4). The unused to used statetransitions are shown below the dotted line in this table. The state diagrams and the corresponding next state maps are shown in the the Fig. 11.32 These next state maps give us the three next state equations and the J-K

Present Next State(PS) State (NS) Q

1
Q
0
Q
☐Q ☐ 1 0
{

0 0 0 1
0 1 1 0
1 0 0 0

{

1 1 0 0
1 1 1 0
1 1 0 1

Table 11.4 : Next state table for MOD-3 counter. inputs for the three cases of unused to used state transitions.
Q1Q0 Unused Q1Q0 Q1Q0 Unused State11 00
11 State 00 0011
Unused
State
1001 10
0110 01
Q0 0 1
Q0 0 1Q1
Q1
0 1 0
0 0 1 1 0 0
1 0 1 Map for Q0+
Q
0 0 1Q1
Map for Q1+Q0 0 1
Q1
0 0 1
0 1 0 1 0 0
1 0 0 Map for Q1+ Map for Q0+(a) (b)
Q+1=Q0Q+1=Q1Q0 Q+0=Q1Q0Q+0=Q1Q0 Q☐ Q☐ J1=1 =Q0J1= 1 =Q Q
010Q10☐
Q☐ K1=Q1 Q1 1☐ =Q0K1= 1 =1Q1 1
☐
☐ =Q1 0 0=Q1J0=Q0 J0=Q Q ☐
Q0 0☐
Q☐ K0=Q0 Q ☐=1K0= 0 Q =1 0 1
0 1

Q 0 0 1Q1
0 0 1
1 0 0
1+Q Map for Q 0 0 1Q1
0 1 0
1 0 1

Map for Q0+(c)
Q+1=Q1Q0
Q+0=Q1Q0+ Q1Q0
Q
☐
J
1
=
1
Q =Q010
Q
☐
K1=1 =1Q1 1
J
0
=
Q
☐
0 Q ☐ =Q10 0
K
0
=
Q
☐
0 Q0 1=Q1
Fig. 11.32 : State diagram and the next state map for unused to used state transition (a) 11☐00 (b) 11☐10 and (c) 11☐ 01.
The logic circuits are shown in Fig 11.33 for the three cases of transitions. This figure shows three different circuits for the same MOD-3 counter.
Q0 Q1 Q0 Q1 1 1 1 J
Q0 J1 J PRE QQ1 Ext. 0 J PRE QQ0 J1 J PRE QExt.
0 J PRE QJ
Clock
Clock CLK FF0 CLK FF1CLK FF0
CLK FF1
1 K CLR
Q 1QK0
K1 K CLR Q1 1K0 K CLR QK1 K CLR Q 1 1
1 1 (a)
(b)
Q0 Q1
11
J J1 J PRE QQ1
Ext. 0 J PRE QQ0
Clock
CLK FF0 CLK FF1
K0 K CLR Q 1K1
K CLR Q
1 1
(c)
Fig. 11.33 : Logic circuit of MOD-3 synchronous counters for unsused to used state transition (a) 11☐00 (b) 11☐10 and (c) 11☐ 01.
◆ MOD-5 Synchronous Counter :
This counter needs 3 flipflops because the MOD number is less than 23 but greater than 22. The used and the unused states are shown in the next state table [Table 11.5 Present Next State(PS) State (NS) Q
1
Q
1
Q
0
Q
+ Q+ Q+
2 1 0
{

0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 0

{

1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 0 0 0

Table 11. 5(a) : Next state table for Mod-5

(a)]. In this next state table the next state transitions from the 3 unused states to the used state have been assumed arbitrarily as shown in Table 11.5(b).

Using the next state maps we may now get the next state equations for Q+, Q+,2 1
Unused Used State State 101 ☐ 010
110 ☐ 010
111 ☐ 000
Table 11.5(b)

and Q+; corresponding equations for J and K inputs of the 3 flipflops are shown below0
the next state maps of the Fig. 11.34. The logic circuit for the MOD-5 counter based on these J and K inputs is shown in Fig. 11.35.

Q1Q0
Q1Q0 Q1Q0
Q
00
2 01 11 10
Q2 00 01 11 10 Q2 00 01 11 10 0
0 0 1 0
0 0 1 0 1 0 1 00 1
1 0 0 0 0
1 0 1 0 1 1 0 0 0 0
Map for Q2+ Map for Q1+ Map for Q0+
Q+=Q2Q1Q0 Q+1=Q1Q0+Q1Q0 Q+0=Q2Q02
Q☐ Q☐ Q☐ J2=2 Q =Q1Q0 J1=1 Q = Q0 J0=0 Q ☐ =Q22 0 10 0 0
K2=Q☐ Q☐ Q☐2 Q=1 K1=1 Q☐= Q0 K0=0 Q0 1=121 1 1
(a) (b) (c)
Fig. 11.34 : Next state maps and the J-K inputs of MOD-5 synchronous counter.
Q0 Q1 Q2
1 1 1 J
0 Q0 J1 JPRE Q Q1 2 J PREQExt.
J PRE QJ
FF0 FF1 FF2Clock
CLK
CLK CLK
K1 K CLR Q 1K2 KCLR QQ21 K0 K CLR Q
1 1 1
Fig. 11.35 : Logic circuit MOD-5 synchronous counter.

Fig 11.36 shows the timing diagram of the MOD-5 counter where we cannot observe any glitches in contrast to the timing diagram of a MOD-5 asynchronous counter shown in Fig. 11.20. The glitch occurs in case of an asynchronous MOD-5 counter because the circuit was allowed to enter the state Q2Q1Q0 = 101 after the 5th clock and then it was decoded for resetting the counter. But in case of synchronous counter, the J and K inputs of the flipflops, are so generated from the combinational circuit by using the Q outputs of the state Q2Q1Q0 = 100 (before the 5th clock) that the counter makes a smooth transition to the reset state when the 5th clock is applied. In this case J and K inputs are J0=0, K0=1, J1=K1=0, J2=0 and K2=1 before the 5th clock.

1 2 3 4 5
Ext.
Clock
J
1
= K
1
= Q
0 1 0 1 0 0
0
0 0
1 1 0 0Q1
J2=AND gate
output
K 0 0 0
0 1 01=1Q2
J0=Q2
K0=1
Fig.11.36 : Timing diagram of MOD-5 Synchronous counter.
◆ MOD-10 (Decade or BCD) Synchronous Counter :
This counter needs 4 flipflops because the MOD number of this counter is within 24 and 23. This counter is also alternatively called as “Decade” or “BCD” counter because the
U n u s e d s t a t e
000000011111
1110
0010
0011 1101
0100
1100
0101
1011
0110
01111010
10011000
Fig. 11.37 : State diagram of MOD-10 (Decade or BCD) synchronous binary upcounter.
Present Next
State(PS) State (NS)
Q
3
Q
2
Q
1
Q
0
Q
+ Q+ Q+ Q+
3 2 1 0

0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
– – – – – – – – – – – – – – – – – – – – – – – – – – –
1 0 1 0 1 0 1 1
1 0 1 1 0 1 0 0 ☐__ Used state
1 1 0 0 1 1 0 1
1 1 0 1 0 1 0 0 ☐__ Used state
1 1 1 0 1 1 1 1
1 1 1 1 0 0 0 0 ☐__ Used state Table 11.6 : Next table of MOD-10 (Decade or BCD) Synchrnous binary upcounter.

count sequence of this counter recycles every after 10 clocks. The state diagram Fig. 11.37 for the BCD counter shows how this BCD counter moves with clocks from one state to the other. For this counter the initial state and the final state of the normal count sequence are assumed to be Q3Q2Q1Q0 = 0000 and 1001 respectively. The 6 unused states for this counter are 1010, 1011, 1100, 1101, 1110 and 1111. We have arbitrarily assumed the state transitions from the unused states to the states of the desired normal counter sequence as follows : (i) 1010
1011
0100
(ii) 1100
1101
0100
(iii) 1110
1111
0000

These state transitions mean that if by any chance this BCD counter enters into any of the 6 unused states of Non-BCD codes then it will be forced to follow the normal counter sequence with maximum 2 clocks. Any other transitions from the unused to the normal counting states can also be considered. The next state table (Table 11.6) shows the different state transitions for this counter.

The next state K-maps for Q+,Q+,Q+ and Q+ are shown in Fig. 11.38(a), (b), (c) and3 2 1 0
(d) respectively along with the next state equations and the J-K inputs for each flipflop below each next-state map. The logic circuit based on these J-K inputs and the timing diagram for the MOD-10 or Decade counter are shown in Fig. 11.39 and 11.40 respectively.

In this timing diagram Q0 toggles with the falling edge of the clock because J0 and K0 are always at 1. Q1 toggles whenever Q0 = 1 and Q3 = 0 or Q3 = 1 (i.e. when J1 = K1 = 1) and the clock is applied.

Q1Q0 Q3Q
Q3Q

Q1Q0
2 00 0111 10 2 00 01 11 10

00 0 0 1 000 0 0 0 0

01 0 0 1 0
01 1 1 0 1
111 1 0 111 1 0 0 1
10 1 0 0 1
10 0 0 1 0
Map for Q3+Map for Q2+ Q+2=Q2Q1Q0+Q2Q0+Q2Q1Q+3=Q3Q0+Q3Q2Q1Q0 ☐
J
3=3 Q
Q☐ = Q2Q1Q J2=Q2 2 0 =Q1Q0 030
☐ K2=Q☐
K
3
=
Q3 31= Q 2
0 Q21=Q1Q0
(a) (b)
Q
1
Q
0
Q3Q2
Q1Q0
Q3Q2 00 01 11 1000 01 11 10
00 0 1 0 1
00 1 0 0 1
01 0 1 0 1
011 0 0 1
11 0 0 0 1
111 0 0 1 101 0 0 110 0 0 0 1
Map for Q1+ Map for Q0+ Q1+=Q1Q0+Q3Q1Q0 Q1+=Q0
☐ ☐ 1 00 =1J1=Q Q1 10 =Q3Q0 J0=Q Q
☐
☐ K0=Q Q1 01=1K1=Q Q1 11=Q0
(c) (d) Fig.11.38 : Next state maps for (a) Q+ (b) Q+ (c) Q+ and (d) Q+.3 2 1 1
Q0 Q1 Q2 Q3 1 1
1 1 Q1Q0 Q2Q1Q0
J0 J
PRE PRE J PRE J PREQ J1 J Q 2 J Q 3 J QExt. 1
Clock
CLK FF0
CLK FF1 CLK FF2 CLK FF3
K2 K Q3 K QQ31K0 K QK1 K
K Q
CLR
CLR
CLR CLR
1 1
1 1
Fig. 11.39 : Logic circuit of MOD-10 (Decade or BCD) binary synchronous counter.
1 2 3 4 5 6 7 8 9 10 11=1
Q
0 0 1
0 1 0 1 0 1 0 1 0 1
Q
1 0
0 1 1 0 0 1 1 0 0 0 0
Q
2 0
0 0 0 1 1 1 1 0 0 0 0
Q
3 0
0 0 0 0 0 0 0 1 1 0 0

J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1 J0=K0=1
J1=K1=0 J1=K1=1 J1=K1=0 J1=K1=1 J1=K1=1 J1=K1=1 J1=K1=0 J1=K1=1 J1=K1=0 J1=0,K1=1 J2=K2=0 J2=K2=0 J2=K2=0 J2=K2=0 J2=K2=0 J2=K2=0 J2=K2=0 J2=K2=1 J2=K2=0 J2=K2=0
J3=K3=0 J3=0,K3=1 J3=K3=0 J3=0,K3=1 J3=K3=0 J3=0,K3=1J3=K3=0 J3=K3=1 J3=K3=0 J3=0,K3=1

Fig. 11.40 : Timing diagram of MOD-10 (Decade or BCD) synchronous binary up counter.

In MOD-10 synchronous counter Q1 is not allowed to enter temporarily into the state Q3Q2Q1Q0=1010 after the 10th clock as we found in the asynchronous counter. This happens because after the 9th clock the state of the counter becomes Q3Q2Q1Q0 = 1001 and J0,K0,J1,K1,J2,K2,J3 and K3 inputs attain the following logic states : J0 = 1, J1 = Q3.Q0 = 0, J2 = Q1.Q0 = 0. 1 = 0, J3 = Q2.Q1.Q0 = 0.0.1 = 0 K0 = 1, K1 = Q0 = 1, K2 = Q1Q0 = 0.1 = 0, K3 = Q0 = 1.

Therefore, when the 10th clock is applied in the state Q3Q2Q1Q0 = 1001 then Q0 toggles from 1 to 0 as J0 = K0 = 1,
Q1 is not allowed to change from 0 as J1 = 0, K1 = 1
Q2 is not allowed to change from 0 as J2 = K2 = 0
Q3 is reset to 0 as J3 = 0, K3 = 1.
Thus, when the 10th clock is applied the counter goes to the state Q3Q2QQ0 = 0000

Design a synchronous BCD counter using all T flipflops. Assume the unused to used state transitions as 1010☐ 1011 ☐ 0110, 1100☐ 1101☐ 0100 and 1110☐ 1111☐ 0010.
Present State Next State Q
3
Q
2
Q
1
Q
0
Q
+ Q+ Q+ Q+
3 2 1 0

0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 1 0 1 1
1 0 1 1 0 1 1 0
1 1 0 0 1 1 0 1
1 1 0 1 0 1 0 0
1 1 1 0 1 1 1 1
1 1 1 1 0 0 1 0
Table 11.7

The state transition table for the BCD counter is shown in Table 11.7. This table includes the state transition between unused to used states as stated in the problem.

(i) Q0 of FF0 always toggles with clock. So, the T input of FF0 i.e. T0 input should always be connected to 1. So, there is no need to draw the K-map for Q+ .0

(ii) Q1 of FF1 toggles if the present states are Q3Q2Q1Q0 = 0001, 0011, 0101 and 0111. Therefore, for these four present states, T input of FF1 i.e. T1 should be 1 and for other states T1 should be 0. This is plotted in the K-map as shown in Fig. 11.41(a) to get the logic equation for T1.
This map gives T1 = Q3Q0.

Q1Q0 Q1Q0
Q1Q0
Q3Q2
00 01 11 10 00 01 11 1000 01 11 10Q3Q2 Q3Q2
00 0 1 1 0
000 0 1 0 00 0 0 0 0 01 0 1 1 0
01 0 0 1 0 01 0 0 1 0
11 0 0 0 0
11 0 0 1 011 0 1 1 0
10 0 0 00 10 0 0
1 0 10 0 1 1 0 Map for Q1+Map for Q2+ Map for Q3+ T
1
=Q
3
Q
T
0 2=Q1Q0 T3=Q2Q1Q0+Q3Q0 (a)(b) (c) Fig. 11.41 : Next state maps (a) for Q+ , (b) Q+, (c) Q+ .1 2 3

(iii) Q2 of FF2 toggles when the present state are Q3Q2Q1Q0 = 0011, 0111, 1011, 1111. So, T input of FF2 i.e. T2 should be 1 for these four states and 0 for other states. The next state K-map of T2 in Fig. 11.41(b) gives T2 = Q1Q0.

(iv) Q3 of FF3 toggles when the present states are Q3Q2Q1Q0 = 0111, 1001, 1011, 1101, 1111. So, T input of FF3 i.e. T3 should be 1 for these states and 0 for other states. The next map of T3 in Fig. 11.41(c) gives T3 = Q2Q1Q0 + Q3Q0.

The logic circuit based on these logic equations for T0, T1, T2 and T3 is shown in Fig. 11.41.
Q0
1
11 1 E
Ext.1
T1 QQ1
T
0
J
0
J
PRE
J J2 PRET3 3 J PREJQQ Q0 1 J PRET2 J Q Q2 Q3
Clock
CLK FF0 CLK FF1 CLK FF2 CLK FF3 K0
K CLR
K CLRQ K2 K CLRQ K3 K CLRQ Q3Q K1
1 111
Fig. 12.42 : Logic circuit of synchronous BCD counter using T flipflops.

1. Two D flipflops are connected as a synchronous counter that goes through the following QBQA sequence 00☐11☐01☐10☐00☐….. . The connections to the inputs DA and DB are [GATE 2011]

(a) DA = QB, DB = QA ; (b)DA = QA, DB = QB ;
(c) DA = (QAQB + QAQB), DB = QA; (d) DA = (QAQB + QAQB), DB = QB.
2. The mod-5 counter shown below counts through states Q2Q1Q0 = 000, 001, 010, 011, 100. Will the counter lock out in any of its unused state?
(a) will lock out at 101; (b) will lock out at 110; (c) will lock out at 111; (d) will not lock out at any state.
3. In module-6 ripple counter the 2-input gate is [GATE 2004]
(a) a NAND gate; (b) a NOR gate; (c) an OR gate; (d) an AND gate

4. . A 4-bit ripple counter and a 4-bit synchronous counter are made using flipflops having a propagation delay of 10 nS each. The worst case delay in the ripple counter and the synchronous counter be R and S respectively, then (a) R = 10nS, S = 40nS; (c) R = 10nS, S = 30nS; (b) R = 40nS, S = 10nS; (d) R = 30nS, S = 10nS.

5. Two D flipflops as shown below are to be connected as a synchronous counter that goes through the following Q1Q0 sequences [GATE 2006]
The inputs D0 and D1 respectively should be connected as
(a) Q1 and Q0: (b) Q0 and Q1;
(c)
Q Q0 and Q1Q0; (d) Q Q 1 0and Q1Q0.
6. In the following circuit of counter, what sequence is followed by A and Bon rising edge of clock after reset is de-asserted ?
{ISRO 2014]
(a) AB = 10☐11☐00☐10☐11☐…. (b) AB = 10☐01☐00☐11☐10☐…. (c) AB = 10☐00☐01☐10☐00☐…. (d) AB = 11☐01☐00☐10☐11☐….
7. A counter is designed using J-K flipflop as shown in figure. Define it count sequence [ISRO 2016]

(a) 000,001,010,011,100 and repeats;
(b) 100,011,010,001,000, and repeats.
(c) 010,011,100,000,001, and repeats;
(d) 101,110,111,000,001,010,011,100, and repeats 8. Given that the initial state (Q1Q0) is 00, the counting sequence of the counter shown in the following figure is Q1Q0 = [GATE 2006]
(a) 00☐11☐01☐10☐00; (b) 00☐01☐11☐10☐00; (c) 00☐11☐10☐01☐00; (d) 00☐10☐01☐11☐00.

9. Consider the partial implementation of a 2 bit counter using T flipflop following the sequence 0 -2-3-1-0 as shown below. To complete the circuit the input X should be [GATE 2004]

(a) Q2; (b) Q2 + Q1;
(c) (Q1 ☐ Q2); (d) (Q1 ☐ Q2)
10. Consider the circuit given below with initial state Q0 = 1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q2 + 2Q1 + Q0.
Which of the following is the correct state sequence of the circuit?
(a) 1, 3, 4, 6, 7, 5, 2; (b) 1, 2, 5, 3, 7, 6, 4; (c) 1, 2, 7, 3, 5, 6, 4; (d) 1, 6, 5, 7, 2, 3, 4.

11. Considering the following circuit involving three D-type flipflops used in a certain type pf counter configuration. If at some instance prior to the occurrence of the clock edges P, Q and R have the values 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge ? [GATE 2011]

(a) 000; (b) 001; (c) 010; (d) 011

12. In the above circuit if all the flipflops were reset to 0 at power on, what is the total number of distinct output (states) represented by PQR generated by the counter? [GATE 2011]

(a) 3; (b) 4; (c) 5; (d) 6.

13. Five J-K flipflops are cascaded to form the circuit shown in the figure. Clock pulses at a frequency of 1 MHz are applied as shown. The frequency (in KHz) of the waveform at Q3 is [GATE 2014]

(a) 0.5 MHz; (b) 160 KHz; (c) 62.5 KHz; (d) 26.5 KHz.
14. A counter is designed with six stages of flipflops. Determine the output frequency at the last (sixth) stage, when input frequency is 1 MHz. [ISRO 2008] (a) 1 MHz; (b) 166 KHz; (c) 15.625 KHz; (d) zero.
15. In a JK flipflop we have J = Q, K =1. Assuming that the flipflop was initially cleared and clocked for 6 pulses, the sequence at the output Q will be [ISRO 2011]
(a) 01000; (b) 011001; (c) 010010; (d) 010101.
16. In figure below, U1 is a 4 bit binary synchronous counter with synchronous clear Q0 is the LSB and Q3 is the MSB of the output. [DRDO 2009]

The circuit shown in the figure represents a (a) mod 2 counter;
(c) mod 4 counter;
(b) mod 3 counter; (d) mod 5 counter.

17. A counter having 10 FFs is initially at 0, what count will it hold after 2060 pulses [ISRO 2007]
(a) 000 000 1100; (b) 000 001 1100; (c) 000 001 1000; (d) 000 000 1110
18. A 4-bit UP counter has preset input 0101. The preset operation takes place as soon as the counter reaches 1111. The modulus of the counter is [ISRO 2007] (a) 5; (b) 10;
(c) 11; (d) 15
363
12.1 INTRODUCTION

Memories are used in sequential digital circuits as an integral part. Also, combinational circuit can be designed using memories. They are used in computers to store a program which is a sequence of instructions in a coded from or it may store any information and data. The codes are nothing but patterns of the bits 1 and 0. We know that a bit can be stored in a latch or a flipflop. Therefore, a memory unit can be thought of as a collection of huge number of flipflops. Each such flipflop is called a memory cell. The numbers of cells in a memory unit depends on the size of the information and the cell can be so arranged inside the memory unit that one cell or a group of cells can be addressed to write or read bit or bits. Therefore, the cells are provided with some control inputs for addressing the cells or group of cells and to accomplish the Read/Write operation.

Above discussions are for semiconductor memories. Other types of storage medium like magnetic tape or disk can also be used to store the bits using the magnetic properties of the magnetic medium. The magnetic memory is generally used for the storage of bulk amount of date but for the magenetic memory the access time is larger. Hence this type of memory is not used when frequent storing and retrieval of data is required at a fast rate.

Now-a-days, optical disk memories are ussed to store a bulk amount of data like the magnetic disk. This optical disk memory operates on a principle of reflection or scattering of narrow laser beam off the optical surface that has microscopic pits or bubbles on it representing logic 1s. The optical disk has a large capacity of storage. The optical disk memory is useful because of its large storage capacity, relatively low cost, immunity to dust and the access time comparable to the hard disk. Three basic types of optical disk memories are available (i) OROM ( ☐ Optical ROM) (ii) CD-ROM ( ☐ Compact Disc ROM) and (iii) WORM (☐ Write Once Read Memory). The content of CD-ROM and WORM can’t be erased but OROM can be written several times and it is equivalent to a magnetic disk. The surface of OROM is coated with a magnetic film and the magnetic property can be changed with a laser beam.

363

The memories built with semiconducting materials using VLSI technology are much faster. For this reason the semiconductor memory is used for frequent Read/Write operation. The semiconductor memory is available in the form of IC chips and the technology used in the fabrication of the memory cells of these ICs can be based on either bipolar or MOS transistors. In general, bipolar memories are faster compared to MOS memory. Yet the MOS memory is preferred over bipolar type because of lower power consumption and higher packing density. Now-a-days, fabrication technology has advanced to boost-up the speed of MOS memory which is comparable to the bipolar memory.

Computer memory where the program and some useful data are stored during computation is called the main memory. Therefore, the main memory is Random Access memory (RAM) type. A random access memory is one in which the time required for storing (writing) and retrieving (reading) information is independent of the physical position of the memory location within the memory.

In the mid 1960s the first random access memory chip using MOS technology was reported at the International solid state circuits conference. 1024 (1Kb) memory was commercially available in 1974. With the advancement of the VLSI technology, now the storage capacity is increased to 1 million times the original RAMs.

In contrast to the random access memory, there is another class of memory called serial or Sequential Memory such as disc or tape. From this type of memory the data bits and the stored program bits are available in the same sequence in which they were originally stored. Therefore, the access time for the information which is stored first is smaller compared to the time of access for the information stored last. On an average, the access time of a sequential memory is longer than the access time of the random access time. Therefore, the sequential memory is generally used for the storage of data in bulk or the program, say the Operating System (OS), which is not repeatedly required for the computation.

Another classification of the memory is whether it is a Read/Write Memory (or RAM) or it is a Read Only Memory (ROM). The RAM allows us to read from or write into any location at random with equal speed. Therefore, a Read/Write memory may also be called RAM (Random Access Memory). The RAM is volatile in nature because the data remains stored in it so long the power supply is ON and will be lost if the power supply is switched OFF. The RAM is available in the following two types (i) Static RAM (SRAM),
(ii) Dynamic RAM (DRAM) The SRAM uses both Bipolar and MOS technology but DRAM is built using MOS technology. In 1970 the dynamic RAM was intorduced. The disadvantage of requiring several transistors per data cell in SRAM is overcome by using the dynamic RAM configuration. The dynamic RAM requires one transistor and one capacitor per cell. In this

memory the data bit is stored temporarily as a charge on a capacitor and the data must be periodically refreshed in order to prevent information loss. The process of reading the data from most of the DRAMS destroys the information, and the data must be put back into memory or part of the read operation. During this refresh operation, all the memory cells are not available for random access read or write operation. The typical DRAM array is refreshed about once every 1 to 2 msec. As the SRAM cell takes up considerably more area than the DRAM cell, on SRAM memory chip typically has only one fourth the number of bits as a DRAM memory of the same technology. For example, it is possible to fabricate 64 Mb and 15 Mb cells in DRAM and SRAM respectively using the same IC technology.

Read Only Memory (ROM) is a non-volatile memory. It means that the data remains stored in it even if the power supply is switched off. This type of memory is called read only because once the data is written into it, it cannot be modified by further writing but only read operation is allowed. In true sense, this memory is also a random access type. But in digital circuit jargon, the acronym RAM usually refers to Read/Write Memory i.e. RWM, while ROM is used only for read only memory through both are random access type. Three basic types of ROMs are available in integrated circuits.

(a) Mask programmable ROM
(b) Programmable Read Only Memory (PROM)
(c) Erasable Programmable Read Only Memory (EPROM) Again there are two types of EPROM
(i) Electrically Erasable PROM (EEPROM)
(ii) Electrically Alterable PROM (EAPROM) Fig. 12.1 summarizes the technologies used in the manufacture of integrated circuit ROMs and RAMs.
RAM
l
BJT MOSFET
Staticl Static Dynamic Fig. 12.1 (a) : Technology used for the fabrication of Read Only Memory
ROM
l
BJT MOSFET
Staticl Mask PROM Dynamic ROM
Fig. 12.1(b) : Technology used for the fabrication of Random Access Memory
12.2 ORGANIZATION OF STATIC READ/WRITE MEMORY

The memory which retains its data indefinitely with the power ON, but does not require any external refreshing is called Static RAM (SRAM). The basic memory cell in a static memory is similar to that of latch. Like the latch, a SRAM is volatile because the stored data is lost when power to the SRAM is switched OFF. Static RAMs are constructed using bipolar (TTL) and MOS technology.

12.2.1 External Organization

The external organization means logical organization of the memory as we see at the device pins. Knowledge of external pin organization and the function of each pin of the memory device is very useful when the circuit designers use the memory devices as a part of the circuit. Internally each location of a memory may contain. 1, 4 or 8 bits. The number of bits in a location determines the word length of the location. For example, the word length of the memories with 8 bits per location is called one byte and such memories are called byte-wide memories. Similarly, if each location contains 1 bit then that memory is called Bit oriented memory.

(a) Address lines

The address lines of a memory module are those input lines which when activated by using binary inputs, select a particular memory location for writing or reading data. Therefore, the number of address lines depends on the total number of locations within the memory. In computer language the alphabates ‘K’, ‘M’ and ‘G’ are used to measure the total number of locations of the memory. In other engineering branches the alphabet ‘K’ is used for 1,000 (☐ Kilo), M is used for 1,00,0000 (☐ Mega) and G is used for 109 (☐ Giga = Kilo Mega) but for computer science 1K = 210 = 1024, 1M = (1K)2 = 220 = 108576 and 1G = (1K) (1M) = 210.220.=230 = 1073471824. (Note that K, M and G are slightly greater than 103, 106 and 109). The number of address lines ‘I’ of a memory is related to the number m of locations of the memory by the relation I = log2(m).

For example, a memory module with 1024 locations and 8 bits per location may be called 1KB (☐1 Kilo Byte) memory. The number of address lines for this memory is I = log2 (1024) = log2 (210) = 10. In terms of bits we may say that this memory has (1024 ☐ 8) bits = 210☐23 bits = 8 Kb (☐ Kilo bits) or 8192 bits. (Note ‘b’ is used for bit and ‘B’ is used byte).

A memory module contains 8192 bits. How many address lines will be required if the memory is (i) byte oriented and (ii) bit oriented?
(i) For byte oriented memory the number of locations will be 8192/8 =1024 =210. Therefore, the number of address lines will be I = log2(210) = 10. This memoryunit may be called 8Kb or 1KB.

(ii) For bit oriented memory the number of locations will be 8192/1 = 8192. Therefore, the number of address lines will be I = log2(8192) = log2 (213) = 13. This memory unit may be called 213☐ 1 bit = (23)´ (210) bit = 8 Kb.

(b) Data lines

To write data into the location and to read data from the location, any memory needs data lines. The data lines using which data are input to a particular location are called data input lines and the data lines using which the data from a particular location are output are called data output lines.

Address lines
Memory
Data inputs
matrix of Data outputs(M) ☐(N)
Cells
Control lines
Fig.12.2(a) : Separate I/O type Address lines
Memory Data inputs

matrix of (M) ☐(N)

Cells
Control lines
Fig. 12.2(b) : Common I/O type
We can categories the SRAMs into two types depending on the arrangement of data input/output lines. Two models are shown in Fig. 12.2(a) and (b).

In the model of Fig. 12.2(b) same set of data lines are used both for carrying data into the memory and to output data from the memory. The model of Fig. 12.2 (a) on the other hand, has separate sets of data lines for incoming and outgoing data.

With common I/O, the data output lines are internally connected back, through tristate buffers, to their corresponding data input lines as shown in Fig. 12.3 (a) for a memory having 4 common I/O lines. Two sets of tristate buffers are not made active simultaneously. The 4

I/O
In0 Out 0
0
In1 Memory cell arrayOut 1
I/O0
including Address
In2 decoding logic Out 2I/O0
circuit
I/O
In3 Out 3
0
CS ControlWR
RD WR logic
Fig. 12.3 (a) : Logic circuit for a memory with common I/O lines.

tristate buffers connected at the input and output side of the memory cell array are controlled by WR and RD signals generated by the internal control logic which is a part of the memory module. The common I/O lines are used to save the number of external pins. The RD and WR control signals may be active low (RD are WR ) for some memory. Also, another control signal called output enable (OE) is also provided in some memories. This signal is used to enable the tristate buffers present at the output. This is used while we read the memory.

In the second category the separate pins are used for the data input and output as shown in Fig. 12.3(b). Therefore, the number of pins required is larger. To connect such a memory with bidirectional data bus, the external tristate buffers are used if the internal buffers are not present as a part of the output circuit.

Following table (Table 12.1) shows a few examples of SRAM memory ICs with common I/O and seperate I/O.
In0
Out 0
In
Memory cell array
1
including Address Out 1 decoding logic
In2
circuit Out 2
In3
Out 3
CS ControlWR
logic
RDWR
Fig 12.3(b) : Logic circuit for a memory with separate I/O lines.
(c) Control Inputs A few control inputs are used to give command to the memory for read and write operation whenever required by the system. These control signals are
(i) Chip select or chip enable, (ii) Write enable, (iii) Output enable or Output control.
Usually, all the control inputs are active low type i.e. for the above three signals we shall use symbols CS for chip select, WE for write enable and OE for output enable or output control.
Following two schemes are commonly used :
(a) the first scheme uses three active low signals CS , WE and OE and
(b) the second scheme uses only two active low signals CS and WE .
In both the schemes the role of CS control signal is to enable a memory module or to select one memory from many memory modules that are present in the system for read or write operation. As the chip select input is active low, so this control signal should be held low to select a memory module for Read/Write operation. But for CS =1 the memory module will not be selected or enabled and under this condition no one can use this memory module for Read/Write operation.
To write data into the memory cells we need OE = 1, CS = 0 and WR = 0. For OE = 1, CS = 0 WR = 0 the input tristate buffers become active and the data can enter into the addressed memory location but the output tristate buffers go into the high-Z state. The logic circuit which can be used to generate the proper signal to control the tristate buffers is shown is Fig. 12.4. This secheme can be used for the tristate buffers having all active high control inputs as shown in Fig. 12.3.
For the write operation WE acts as a clock under CS = 0 andOE=1. When WE becomes low, the write operation starts and when WE goes high then the write operation is inhibited.
For read operation using the first scheme, we need WE = 1,CS = 0, OE = 0 as evident from the logic circuit shown in Fig. 12.4 and Fig. 12.3. The data from the selected memory cells (selected by address inputs) will come out on the external data pins if OE is pulsed low while CS = 0 and WE = 1.
CSOE WE Mode I/O Pins of operation 1 x x not selected High-Z
0 0 1 Read Data out
0 1 0 Write Date in Table 12.1 : Functional table for a common I/O memory with control signal CS , OE , and WE

Y goes to the control pin of the output tristate buffer WE

X X goes to

the control pin

of the input tristate buffer

CSX=

{1 for Write}

0 for READ Y={1 for READ}

OE
0 for WRITE
Fig. 12.4 : Logic circuit to generate the signal for tristate control (First Scheme).
Y X X goes toY the control pin CS

of the input tristate buffer

Y goes to the control pin of

the output tristate buffer WE

X={1 for Write}

0 for READ Y={1 for READ}0 for WRITE
Fig. 12.5 : Logic circuit to generate the sigal for tristate control (Second Scheme).

The above discussions are summarized in Table 12.1. It may be noted that OE and WE cannot be active simultaneously and for CS = 1 both write and read operation are inhibited.
The second scheme is used for the memory modules without OE control line. In this scheme, the write operation is accompilished if the memory module is selected (CS =0) and WE is low and on the other hand for the read operation the memory should be selected (CS = 0) and WE should be High. In this scheme, one pin of the memory is saved by not using the OE input. The logic circuit which generates the tristate control signal for the input and output buffers is shown in Fig. 12.5.
The Fig. 12.6 (a) shows memory with 15 memory cells arranged in the form of a matrix having 4 rows and 4 memory cells per row. Here, each memory cell can store a bit for logic Row-0 Cell-0 D0 D1 D2 D3
Y
Cell-1
Cell-2 Cell-3
Select
0
A A
1 0
4-bit data bus
Row-1 Cell-4 D0 D1 D2 D3
A1 Y
Cell-5
Cell-6 Cell-7
Select
1 A
A1 0
4-bit data bus
A0
Cell-10 Cell-11
Y
Row-2 Cell-8 DCell-9
0 D1 D2 D3Select
2
A A
1 0 4-bit data bus
Row-3
Select
Cell-12 D0 Cell-13 D1 Cell-14 D2 Cell-15 D3
Y3 A1A0
4-Bit data bus
CS Read/Write 4-Bit data logic and buffer WE Fig. 12.6 (a) : One dimensional word organized (4 x 4) memory. Cell 1

either read or write 4 data bits at a time inRow-1
1 or logic-0. All the 4 cells of a single row of the matrix can be accessed i.e. enabled simultaneously for Read/Write operation by an active high signal called Row select signals generated using a 2-to-4 decoder. Therefore, we may say that the four rows of the (4 × 4) cell matrix have the following addresses Address of the cells (0, 1, 2, 3) of Row-0 is A A1 0 = 00
Address of the cells (4, 5, 6, 7) of Row-1 is A1A0 = 01.
Address of the cells (8, 9, 10, 11) of Row-2 is A1A0 = 10.
Address of the cells (12, 13, 14, 15) of Row-3 is A1A0 = 11.

In general, using the address lines (An–1, ...., A0) to the decoder we can generate 2naddresses and hence a cell-matrix containing 2n rows can be used. This figure shows that only 4 memory cells are present per row but any
number of cells can be placed in a row

Cell depending on the width of the data bus of 0 the memory. In this case the width of the Y
Row-0
0
data bus is 4 because we can simultaneously
(A A1 0)
address 4 cells in a row and hence we can
Y1
a row. The Read/Write logic circuit A1 A1 (A A )1 0 Cellassociated with the cells controls the2-to-4
decoder
Row-2
2
direction of data flow into the cells or out A0 A0 Y2
from it during write or read operation(A A )1 0 Cellrespectively. When the control signal WE= 0
A A1 0 3the four data bits can be entered into theY Row-3
3

addressed cells in a row and when WE = 1(A1A0)
then the data bits can be read from the

addressed four cells. The CS signal used to

CS Read/Write logiccontrol the Read/Write logic circuit. TheWE

and buffer

CS =1 inhibits any Read/Write operation Dataeven if cells in a row are addressed by the

decoder. For read or write operation CS
input should be made logic low. The Fig.12.6(b) : One dimensional bit organized (4☐1) organization of the cells of this type is called
word organized because the read or write operation is performed on a group of cells present in a row simultaneously. In this case the word length is 4 but the word length may be greater than 4.

In a bit organized memory only one cell can be addressed at a time. In this organization the memory cells can be arranged in a column (i.e. in the form of a linear array) as shown in Fig 12.6(b) or in the form of a matrix as shown in Fig. 12.6(c).

To address a memory cell arranged in a column as shown in Fig. 12.6(b) we need one decoder with number of outputs equal to the number of memory cells in the column. This type of addressing is called one dimensional addressing.

To select one cell from a bit organized memory arranged in a matrix we need two decoders as shown in Fig. 12.6(c). One decoder is used to select the row in which the cell to be selected is present in the matrix. This decoder is called the row decoder or X-decoder. The other decoder selects the column on which the same cell is present. This decoder is called the column decoder or Y-decoder. These two decoders jointly address the cell which is present at the cross point of the addressed row and column of the matrix. This type of addressing is also called X–Y addressing, or two dimensional addressing.

A3 A2
Column decoder
Col-0 Col-1 Col-2 Col-3
Cell Cell
Cell Cell
0-0 1-0
2-0 3-0
Row-0
Y0
Cell
Cell Cell Cell
0-1
1-1 2-1 3-1
Row-1
A
Y
11
A0 Cell
Cell Cell Cell
0-2 1-2
2-2 3-2
Row-2
Y
2
Cell
Cell Cell Cell
0-3
1-3 2-3 3-3
Row-3
Y3

Read/Write

CS control logic

and buffer WE
Data Fig. 12.6(c) : Two dimension bit organized (15☐1) memory.

In a bit organized two dimensional memory the address of each memory cell is determined by the simultaneous inputs to the two decoders (row and column decoders). For example to address a cell positioned at the cross point of Col-3 and Row-2 we have to use A1A0 = 10 and

A3A2 = 11 as the inputs to the two decoders. Thus, the effective 4-Bit address of this cell A3A2A1A0 = 1110. For this 4-Bit address only the cell (3–2) is enabled for its 1-Bit data transfer to the data line of the memory module. Using the combination of the 2-Bit column and 2-Bit row addresses any cell from the (4 ☐ 4) matrix can be selected for data transfer. Each cell is connected to the R W control line which controls the direction of the data flow of the cell during read or write operation. The inputs to the control logic circuit is WE =1 and CS = 0 for read operation from the cell and WE = 0 and CS = 0 for write operation into the cell. To select a memory cell from a matrix using two dimensional decoding, the two decoders use the coincidence decoding technique as shown in Fig. 12.6(d). This circuit selects only one cell out of 4 ☐ 4 cell matrix for ReadWrite operation.

In 2-dimensional word oriented RAM, the memory cells are arranged in the matrix form. But, in this case, at each cross point of A1

a row and a column of the matrix A0there exists a group of cells instead of single cell as it is shown in Fig. 12.6(c). The number of cells in each such group depends on the internal data bus width. All the cells as aA3whole, in one group, present at the cross point of the matrix areA2 selected simultaneously by the row and column decoder and the bit pattern from the selected group are available on the internal data bus Row
decoder A A1 0 A A A Ato cellY 3 2 1 0
0 A A
(0-0)Y 1 0
1 A A
A A A A
Y
2
1 0 3 2 1 0 to cell A1A0
(0-1)Y3

Col.
decoderA A3 2

YA3A2A1A0 to cell0 A3A2

(3-1)Y1 A3A2

A3A2A1A0 to cellY2 A3A2
(3-3)Y3
Fig. 12.6 (d) : Coincident decoding circuit during read operation and during write operation the data word from the data bus can be entered into it. The direction of data flow is controlled by READ/WRITE logic provided the memory module is enabled using active low CS signal. The technique of coincident selection is also applied for the selection of a group of cells from the matrix.

12.3 RAM CELLS

In this section we shall see how a basic memory cell can either store 1 or 0. The circuit for the basic cell can be fabricated using bipolar technology or by MOS technology. We shall also see how this basic cell responds to the READ/WRITE control inputs and address inputs. The bipolar RAM cells are all static in nature but MOS cell may be static or dynamic. The MOS cell requires smaller space compared to the bipolar cells. In general, the speed of the MOS memory is smaller compared to the bipolar memory. However due to the present day technology it has become possible to fabricate MOS memory with speed comparable to those of bipolar memory.

12.3.1 Bipolar RAM Cell The basic memory cell associated with the READ WRITE logic circuit is shown in Fig. 12.7. The circuit for the bipolar cell, the logic circuit for reading the cell and writing into the cell are separated by the dotted line. In this figure only one cell is shown but many such cells can be connected to the DATA and DATA lines in a similar fashion but the READ WRITE logic circuit is common to all the cells, in a column, having same DATA and DATA lines. This is possible because only one cell is made active at a time to set up a communication link via DATA/DATA line with the READ/WRITE logic.

To other cells To other cells
Vcc
Rc Rc
ED0 Q0 Q1 ED1 Basic Memory Cell EC
R
B
0 EC1ER0 X ER1 RB To otherRow select
X inputs of Y the cell in this rowColumn select
Vcc
R1 R1
Dout Dout Read (or Sense Amplifier) Q2 Q3 B
A
RE
Vcc
Vcc R
D
3 1 C

D D2 R3
V1Q R2
4 +0.5VR2 V2 Write Amplifier Q5
R W E F
G1
CS Control logic
Din G2
Fig. 12.7 : Bipolar Static RAM Cell
Each cell is designed with two multiemitter NPN transistors (Q0 and Q1) connected in the bi-stable (Flipflop) mode.

The emitters ED0 and ED1 of the two transistors Q0 and Q1 are connected to DATA and DATA lines respectively. These two emitters may be called data emitters because these two emitters are used for writing or reading one binary bit of data into a cell with the help of the DATA and DATA lines.

The emitters ER0 and ER1 of the two transistors are connected together to the Row select output of line which is the row decoder and the other two emitters EC0 and EC1 are also connected together to the column select line which is the output of the column decoder. These two pairs of the emitters help the coincidence decoding of one cell.

For most of the commercially available bipolar memories, the supply voltage may range from 3.5v to 5.0v. Therefore, we may then reasonably consider any voltage ☐ 0.3v as logic-0 and any voltage greater than 3.0 as logic-1. A bias voltage of 0.5v is applied through the resistor R2 to the emitters ED0 and ED1. Let the Row Select (X) and the Column Select (Y) inputs to the cell are at logic-0 (☐ 0.3v), R W is at logic-1 and CS input is at logic-0. Under this condition (R W = 1, CS = 0) the transistors Q4 and Q5 are ON with their collector voltage at logic-0. Hence, the diodes D1 and D2 do not conduct. If we assume that the transistor Q0 is ON and Q1 is OFF then the current from the ON transistor Q0 will flow through ER0 and EC0 and no current will flow through ED0 because ED0 is biased to 0.5v through the resistor R2 and this bias voltage is atleast (0.5v– 0.3v) = 0.2v higher than the voltage on ER0 and EC0. The two transistors Q2 and Q3 do not conduct as their base current is zero. Dout terminal is at logic-1 and this level of Dout will persist independent of the state of Q0 and Q1 transistors of the memory cell.

Thus, for read and write operation, the input X and Y to the cell from the Row and Column decoder should be at logic high. This is called addressing a cell. Reading from the cell The cell is addressed by raising the voltage at X and Y on logic-1, R/W = 1 and CS = 0. Assume that the transistor Q0 is ON and Q1 is OFF (1 is stored in the cell).
For this input condition the transistors Q4 and Q5 conduct because their base voltage is high. The diodes D1 and D2 become non-conducting as the collector voltages of the conducting transistors Q4 and Q5 are low. The current flow occurs through ED0 of the ON transistor Q0 of the cell to the DATA line and no current flows to the DATA line from the OFF transistor Q1. This forces the transistor Q2 to become ON and Q3 to OFF and hence Dout terminal (collector of Q3) becomes high as if we have read the stored 1-Bit on Dout by using CS = 0 and R/W = 1.
Similarly, for Q0 OFF and Q1 ON (0 is stored in the cell), the transistors Q2 and Q3 will be OFF and ON respectively and Dout terminal will be low for R/W = 1 and CS = 0, as if the stored bit 0 is available on Dout terminal due to this read operation.

Therefore, we can see that when we read the cell then the Dout follows the logic state of Q1.

Writing into the cell

Let the cell be selected by providing logic-1 voltage to both X and Y from row and column decoder respectively. If CS = 0, R/W = 0 and Din = 1, then the output of the NAND gate G2 and G1 are low and high respectively. Hence, transistor Q4 and Q5 become ON and OFF respectively. The diodes D2 and D1 connected to the collector of Q5 and Q4 becomes conducting and non-conducting respectively because of low and high collector voltage of Q4 and Q5. The conducting diode D2 raises the voltage of emiter ED1 of transistor Q1. Thus, the transistor Q1 becomes cut-off (EC1 and ER1 of Q1 are also high because of logic-1 voltage at X and Y as the cells are selected by the row and column decoder) and its collector voltage reaches logic-1 level which in turn makes the transistor Q0 on.

Col-0 Col-1 Col-M
D D Y D Y
D D
D Y Row-0X X
X
D D
D D Y D Y
D Y Row-1X X
X
D D
D D Y D Y
D Y Row-NX X
X
DATA
Dout Dout
A Read (sense) B
Amplifier

C D

Write

Amplifier

CS
E F
R W Control
D
Logic
in
Fig 12.8 : Black diagram of (M☐N) Bipolar SRAM

On the otherhand if Din = 0, CS = R/W = 0, then the output of the NAND gate G1 becomes low and that of gate G2 becomes high. Therefore, Q5 conducts and Q4 goes to cutoff. The diodes D2 amd D1 connected to the collector Q5 and Q4 become OFF and ON respectively because of low and high collector voltage of conducting and non-conducting transistors Q5 and Q4. The ON-diode D1 makes the emitter ED0 of Q0 high forcing it to the non-conducting state leading to a rise in collector voltage of Q0. Thus, the transistor Q1 conducts and its collector voltage falls to a low value.

From the above discussions we may conclude that the collector of Q1 follows the logic state of Din.
Fig. 12.7 shows a single bipolar cell connected to a sense (Read) amplifier, write amplifier and control logic circuits. This may be extended to a SRAM containing a (M☐ N) array of bipolar cells. The block diagram representation of a bit organized SRAM with array of (M☐ N) bipolar cells is shown in Fig. 12.8. It may be noted that for (M☐ N) SRAM only one sense amplifier, write amplifier and the control logic circuit have been used.

12.3.2 CMOS Static RAM Cell

Fig 12.9 shows the simplified version of the CMOS cell used in the static RAM. Two cross coupled CMOS inverters designed using (Q1, Q2) and (Q3, Q4) form a flipflop which stores the data bit 1 or 0. The transistors Q5, Q6, Q7 and Q8 are the pass transistors. The pass transistors Q5 and Q6 connect the flipflop outputs to DATA and DATA lines. The use of complementry devices reduces the power consumption.

VDD DATADATA
Q1
Q3
Q5
Q6
Q
Q42
X
VDD Q8
Q
(From row decoder output)
7
Y
(From column decoder)DoutR W
D
in
Fig. 12.9 : CMOS static RAM cell.
12.3.3 MOS Static RAM Cell Higher density and low power dissipation are two important features of the static RAM cell. The structure of the basic MOS RAM cell is shown in Fig. 12.10 using 6 MOS transistors. This memory cell can store only one bit. This figure includes the circuit for read/write operation along with the 6-transistor cell. The memory cell has been indicated within a dotted box.

This cell shown in Fig. 12.10 is formed by cross coupling the two inverters. One inverter is designed using Q1 and Q3 and the second inverter is designed using Q2 and Q4. In these two inverters, Q1 and Q2 are the NMOS driver transistors and Q3 and Q4 are the load transistors. The load transistors may be replaced by polysilicon resistor. But this polysilicon resistor requires a larger area in this chip. Q5 and Q6 are NMOS pass transistors and are used to connect the output nodes N1 and N2 of the two inverters to the DATA and DATA lines respectively. These two pass transistors are controlled by the high output of a row decoder. These DATA and DATA lines are connected to every cell present in the same column.

V
To other DD Cells in To other
the same Cells in
column the same
columnQ3
Q4 6 transistor Q5
Q6 MOS N1 N2 memory cell
Q1 Q2
X
(From row decoder output)
Q7
Q8Y
(From column decoder output)
VDDQ11 Q15
Q16 Q12 D outDout
Q13
D in
Q
9
Q14 Q10 Din
Read/Write
Q17 Sense circuitSense circuitR W Read/Write
Fig 12.10 : One MOS static RAM cell along With Read / write logic For the selection of a cell in a particular column and row it is necessary to address that cell by raising the X and Y inputs high by the row and column decoder outputs. Two READ/

WRITE amplifiers are connected to the pass transistors Q7 and Q8 for reading and writing a bit into the cell. In the READ/WRITE sense amplifier, Q17,Q10 and Q12form the one 2-input NAND gate for the right READ/WRITE amplifier and Q17, Q9, and Q11 form the same for the left READ/WRITE sense amplifier.

Write Operation :
In order to write a logic-1 into the cell, the cell is addressed by raising X and Y inputs to logic High, the R /W and Din to VDD (☐ D in = 0). Thus, Q17 and Q10 are ON and Q9 is OFF.. Therefore, the DATA line is grounded through the ON transistors Q8, Q10, and Q17 but DATA is pulled up to VDD through ON transistor Q7 because Q9 of the NAND gate is OFF. Thus, the node N2 and N1 are effectively grounded and pulled-up to VDD respectively. Thus, Q2 is held ON and N2 is maintained at logic-0 and Q1 is held OFF an N1 is at logic-1. When the address is removed then Q5, Q6, Q7 and Q8 are all OFF but Q2 and Q1 remain ON and OFF respectively. Similarly, if logic-0 is to be written then R/W = 1, Din input = 1 (Din = 0) and the cell is addressed by raising X = Y to VDD. Under this condition Q17, Q9, and Q7 are ON but Q10 is OFF. Therefore, the nodes N1 and N2 are effectively grounded and connected to VDD respectively. This forces Q1 ON and Q2 OFF. Thus, we may say that the bit-1 can be written into the cell by making R/W = 1 and Din = 1 (☐ Din= 0) and bit-0 can be written into the cell by making R /W = 1, Din= 1 (☐ Din= 0). The transistor Q1 of the memory cell follows the logic state of the external data bit at Din used for storing.

Read Operation

Assume that the MOS cell has already stored logic-1 i.e. Q1 is OFF (☐ N1 is near to VDD) and Q2 is ON (☐ N2 is near ground) during a read operation. For read operation the cell is addressed by raising X and Y input to VDD and lowering the R /W input low. The low voltage to R /W cuts off Q17 and therefore Q9 and Q10 cannot conduct. Q5, Q6, Q7, and Q8 are ON because X = Y = VDD. The current flows from the supply VDD which is connected to the drain end of the load transistor Q12 through the ON transistors Q8, Q6 and Q2 to ground. This causes the DATA line to be effectively grounded. The transistor Q14 is cut off because it’s gate is connected to DATA line. Thus, the Dout output will go high. This means that the output Dout follows the logic state of the transisor Q1. On the otherhand, no current can flow from DATA line through the ON transistors Q3, Q5 and Q7 becaue Q9 and Q17 are both in non-conduction state, and the node N1 is near to VDD because Q1 is OFF. Therefore, the voltage at the gate of Q13 is high and it becomes ON. The Dout output goes low. This is the complement of the logic state of Q1. We have, therefore, correctly sensed the memory cell which stores logic-1 (Q1 OFF and Q2 ON). If Q1 was ON and Q2 was OFF before reading then we could get the outputs Dout = 0 and Dout =1.

The two dimensional array (64 ☐64) of 6-transistor SRAM MOS cells are shown in Fig. 12.10. Each cell is represented using a box with two outputs D and D and one address input X. This address input X of the cell is connected to the output of the Row decoder. The cells in a row have a common X input. Thus, the output of the row decoder selects the cells

present in a row from the array. The D and D are nothing but the output from the two pass transistors Q6 and Q5 of each cell as shown in Fig. 12.10. The DATA and DATA lines are used separately for each column and the D and D outputs from each cell in a column are connected to the DATA and DATA lines respectively. These two lines DATA and DATA are connected to the drain end of the pass transistors Qi and Qi respectively of each column i as shown in8 7
the Fig. 12.11. The high output from the column decoder makes the pass transistors ON and connects the READ/WRITE logic circuit to communicate through the DATA and DATA lines. But the addressing of the array is 2-dimensional and since only one cell is selected by the row and column decoder and hence this selected cell from the array can communicate with the READ/WRITE logic circuit.

Row-0
X X X
D D D D D D
Row-1
X X X
D D D D D D
Row-63
X X X
D D D D D D
Q07 Q
Y 08 Q17 Q18 Q637 Q638 Y
To read/write
logic circuit
To read/write Col-0 Col-0 Col-63 logic circuit Y0 Y
1Y63
Column decoder
A6 A7 A8 A9 A10A11
Column Address
Fig. 12.11 : The organization of a 4096 words☐ 1 bit MOS SRAM
12.4 SEMICONDUCTOR READ-ONLY MEMORY (ROM) A memory with fixed data at the time of manufacture is called a Read-Only Memory (ROM). A ROM is a combinational circuit that consists of an array of semiconductor devices, such as diodes, bipolar transistors or MOSFETS. Generally, a ROM is used to permanently store fixed constants or some conversion data as a look-up table. Simplest ROM can be designed using an array of diodes, BJTs or MOSFETS. A ROM is basically made up of a decoder and an

encoder as shown is Fig. 12.12.

In this figure the used active devices are diodes, BJTs and MOSFETS as mentioned.
Am–1
DK–1
Am–2
DK–2 Decoder
2m☐K
A1
active deviceD1
A0
D0
Decoder Encoder
Fig. 12.12 : Basic ROM structure The capacity of this ROM is (2m ☐ K), bits where 2m denotes the number of locations which can be addressed one-at-a time by the m address inputs (A0 to Am–1) to the decoder and K denotes the number of bits per location. The stored data (K bits) of any location is available on the output (D0 to DK– 1) and the K-Bit output data is due to a unique combination of the m input variables (Am–1, Am–2..., A1, A0). Thus a ROM may be called a multiple input/multiple output combinational circuit.
(a) Diode ROM array : The circuit shown in Fig. 12.13 is for a ROM constructed using an array of semiconductor diodes. The diodes are arranged in the form of a 4 ☐ 4 matrix. The diodes are placed at the selected cross points of the columns
and the rows. The 4 column wires are

R R R Rpulled down to ground using fourRow-0 Col-0 Col-1 Col-2 Col-3

resistors of equal value R and hence if

no positive voltages are applied to theD1

D 2rows then the four outputs Y3, Y2, Y1 Row-1
and Y0 will be at ground potentials.

When a positive voltage is applied Row-2D3 D4
D5
to i-th row then the diodes connected
to the i-th row will be forward biasedD6 D7
D8

since the anode ends connected to theRow-3

i-th row are pulled up to positive
voltage of the row and the cathodeD9 D10

Y3
ends are connected to the columns
Y2
which are pulled down to ground.
Y1
These resistors are used to avoid the
Y0
short circuit of the voltage sourceFig. 12.13 : ROM array using diodes.applied to the row through the

Row Selected Logic-1 voltage applied

Row–0
Row–1
Row–2
Row–4

Conducting Outputs Diodes Y3 Y2 Y1 Y0

D1, D2 1 0 1 0
D3. D4, D5 1 1 1 0
D6, D7, D8 1 0 1 1
D9, D10 0 1 1 0

Table 12.2 : Outputs of the diode matrix ROM shown in Fig. 12.13

conducting diode and the ground. Table 12.2 shows the outputs on Y3, Y2, Y1 and Y0 when positive voltage (+5v) is applied to different rows. Application of positive voltage to any row positive voltage (+5v) is applied to different rows. Application of positive voltage to any row bit word which are obtained due to the addressing of the rows are fixed and can be used repeatedly. By changing the position of the diodes in the matrix we can obtain different fixed outputs. In this matrix, the presence of a diode at any cross point of any row and column indicates a bit-1 and on the otherhand the absence of a diode indicates a bit-0 stored at that cross point of row and column.

(b) Transistor ROM Array

ROM can be designed using the bipolar transistor in the matrix instead diodes. In this case each transistor is used as a switch at the selected cross point of the row and column. The switching action is initiated by applying positive voltage to the base of the transistor through the row select lines if NPN transistors are used. The emiter of each transistor is grounded and the collector is connected to the column. The Fig 12.14 shows a circuit of ROM using NPN transistors
at the selected cross point of

Content rows and columns. WhenRC RC RC R

C of the
any row is driven by a logic Row-0RB
location
high voltage then the bases of
0010 (Y3Y2Y1Y0)
the transistors connected to
Row-1 R
Q1
Q2 Q3
that row become high andB
0101 (,,)
consequently those
transistors are switched ON.
Q4 Q5
Row-2 R
This figure shows that theB
0100 (,,)
collectors of the transistorsQ6 Q
Q8
are pulled up to V
CC
via the
Row-3 R
7
B
collector resistor RC
1001 (,,) connected to each column.

Y 3When any transistor is

Y 2switched ON then the

Y 1column to which the collector

Q 9 Q10 }of this ON transistor is

Y0
connected is grounded andVCC

the corresponding column Fig 12.14 : ROM using bipolar NPN transistors. output will be at logic low.

For example, if Row-0 line is selected i.e. logic high (+5v) is applied to Row-0 then the transistors Q1, Q2 and Q3 will be switched ON and hence the Col-0, Col-2, and Col-3 will be pulled down to approximately ground voltage. But, as no transistor is present at the cross point of Row-0 and Col-1 therefore Col-1 will carry the voltage Vcc on it. For this reason, due to the application of +5v only to Row-0, the output will be Y3Y2Y1Y0 = 0010. Similarly, we can get the outputs for the selection of the other rows. One important point to be remembered is that the selection of rows should be done one at a time. The selection of a row may also be called addressing of that row. The Table 12.3 shows the different outputs at Y3Y2Y1 and Y0 for the different addressing of rows.

Row Outputs ON
Selected Y3 Y2 Y1 Y0 transistors Row–0 0 0 1 0 Q1, Q2, Q5
Row–1 0 1 0 1 Q4, Q5 Row–2 0 1 0 0 Q6, Q7, Q8
Row–3 1 0 0 1 Q9, Q10

Table 12.3 : Different outputs for the ROM shown in Fig. 12.14 (c) MOSFET ROM Array Fig 12.15 shows a ROM designed with NMOS enhancement mode transitors. The NMOS devices remain OFF when the gate voltage is zero and they are switched ON when the gate voltage is at logic high. In this circuit the ON transistors in any ROW pull down the column to which the drain of the ON transistor is connected. Therefore, the presence of a NMOS across any row and column will output 0V at the column output when that row is selected or

V DD

Content of the

locaion

Col-3Row-0 Col-0 Col-1 Col-2
0001 (Y3Y2Y1Y0)
Row-1Q1 Q2 Q3
(,,) 0100
Row-2Q4 Q5
Q6 (,,) 1010
Row-3Q7 Q8
(,,) 0010
Q9
Q10 Q11

Y2

Y1

Y Y3}Fig. 12.15 : ROM using NMOSFETs.0

addressed using a logic high voltage. In this circuit MOSFET load is used instead of resistor to facilitate the fabrication. If NMOS transistor is absent across a row and a column then logic-1 will be the output on that column when that row is selected. Table 12.4 shows different column outputs for this ROM.

Selected Row
Switched On Outputs of columns NMOSEFT Y1 Y2 Y3 Y0
Row–0 Q1, Q2, Q3 0 0 0 1 Row–1 D4. D5, D6 0 1 0 0 Row–2 D7, D8 1 0 1 0 Row–3 D9, D10, D11 0 0 1 0
Table 12.4 : Output of the ROM using NMOSFETs as shown in Fig. 12.15
12.4.1 ROM cell structure We have seen that a ROM is designed with an array of cells and these cells may be fabricated using BJTs, MOSFETs or simple diodes. The connection of a cell to the row and column lines can be done in the following two ways : (i) Conventional NOR gate type parallel structure
(ii) Serial NAND gate type structure.
We can see in Fig.
12.15 that the MOS D0 D1 D2 D3 VDDtransistors, used as cells,
are connected in parallel
NMOSFET
to the columns. This array Row-0
LOAD

1011 (D3D2D1D0)structure is called NOR

array. Using a positiveRow-1

1101 (,,)logic, a stored “1” is

defined as the absence of
a conducting path to that Row-2

(,,) cell transistor or the

1110

absence of the cellRow-3

0101(,,)transistor. In normal

operation, only one row

is made high. When it is
done, all transistors with
the gates connected to Fig 12.16 : ROM using NAND array structure. that line are turned ON,

so that the columns to which these ON transistors are connected are pulled low since the source of the MOS transistors are grounded. The remaining columns are held high by the pull-up-load transistors. The parallel cell structure has the advantage of high speed but each cell needs larger area. Hence the packing density is low.

Fig. 12.16 shows NAND ROMs of size (4 ☐4) in which the celltransistors are series connected in a column. In this NAND array structure one row is selected by making that row low and the other row lines to logic-1. When a selected row is pulled low, all transistors with gates connected to that line are turned off and columns to which these transistors are connected are pulled high by the pull-up load transistors. The data outputs lines (D3D2D1D0) are taken from the junctions of the source of the load MOSFET and the drain of the top cell MOSFET of each column. For this NAND array, in positive logic, the presence of a transistor indicates a storage of 1 bit and 0 bitcan be stored atany location byshorting the drain and the source terminals of a cell transistor i.e. the absence of a cell transistor indicates a ‘0’ bit. This array structure needs a smaller area.

A combination of serial-parallel ROM array structures has also been implemented for speed and bit density trade-off.
12.5 ADDRESS DECODING AND ROW SELECTION

In the above three illustrations we noted that the outputs depend on the arrangement of the diodes or the transistor (BJT or MOSFET) across the row and column of the matrix and the inputs on the selected (or addressed) row of the matrix. The selection of the rows R R R R
2-to-4Row-0
decoder
Y
A A1 0

0

A 1 A Y A A1 0 Row-1

1

A A

Y
1 0
2 Row-2
A0 B

Y
A

3 1A0
Row-3

D0

D1

D2

D3

Fig. 12.17 : Row addressing using decoder. one at a time can be performed if a decoder of suitable size is used to drive the rows of the ROM-matrix. For example, in a ROM-matrix if there are 15 rows, then we can use a 4-to-15

decoder. The four inputs of the decoder are called the addresses of the ROM. This 4-Bit address determines which one of the 15 rows is to be selected to output data stored in that row. The polarity of the output of the decoder depends on whether the row of the matrix needs active high or low voltage for the selection of a row.

The Fig 12.17 shows how the four outputs of a 2 to 4 decoder with active high outputs are connected to the four rows of 4 ☐ 4 diode matrix ROM. Each row of this matrix has a unique address determined by the two address inputs A1 and A0 of the decoder. The ROW-0 has an address A1A 0 because for A1 = A0 = 0, the output Y0 of the decoder becomes high and the Address Row Outputs
A1 A0 Selected D3 D2 D1 D0
0 0 Row–0 1 1 0 1

remaining outputs (Y1, Y2, Y3) of the decoder remain low. Thus, only ROW-0 of the ROM is selected when A1A0 = 00. Similarly, the addresses for ROW–1, ROW–2, and ROW–3 are A1A0 = 01, 10 and 11

0 1 Row–1 0 1 1 0
1 0 Row–2 0 1 1 1
1 1 Row–4 1 1 0 1
Table 12.5 : ROM output for the fig respectively. In this diode matrix all the forward biased diode will give 1 output. The absence of the diode and the reverse biased diode will give 0 output. The Table 12.5 shows the output from the ROM due to the different address inputs A1 and A0 for the circuit shown in Fig. 12.17.

In general if the ROM has N rows then the size of the decoder should be M-to-N where the minimum value of M should satisfy the relation 2M☐ N. For example, a ROM with 15 rows needs a 4 - to - 15 decoder, a ROM with 1024 (☐☐ to-1024 and a ROM with 4096 (☐ 4K) rows needs 12-to-4096 decoder. Therefore, it may be noted that the decoder size increases rapidly as the number of rows of a ROM increases. Each row of a ROM can be thought of as a location where the bits of information are stored and when a location is addressed then the stored bits of cells (using diodes or transistors) will be available on the outputs.

12.6 TYPES OF PROGRAMMABLE ROMS
There are four types of ROMs
(i) Mask Programmable ROM (this cannot be reprogrammed by the user) (ii) EPROM – Erasable and Programmable ROM
(iii) PROM – Programmable ROM
(iv) EEROM – Electrically Erasable ROM

(i) Mask Programmable ROM

So far we have seen the ROMs where we selectively used the switching elements like semiconductor diodes, BJTs and MOSFETs at the intersections of rows and columns. The presence and the absence of such switching elements at the intersection indicates storage of bit 0 and 1 at the intersection. Such a ROM is called Mask Programmed ROM. The stored data bits become fixed during the manufacture of such type of ROM and can’t be altered by the user at any time. Due to the inflexibility of this type of ROM and the relatively high cost

of development, it is used only for well developed high value applications. However, even though the development cost of a mask programmed ROM is high, volume production is cheaper than for some other type of ROM. A few examples of uses of mask programmed ROM are (a) code conversion
(b) function look up table (table corresponding to binary values of trigonometric, exponential or other functions)
(c) character generator for CRT display from ASCII code generated by the key of the keyboard
(ii) PROM (Programmable ROM) Some ROMs are fabricated by the manufacturers where the active switching devices (like BJTs or MOSFETs) are placed at each intersection of row and column of the matrix unlike at the selected intersection of row and column of the matrix as in Mask Programmed ROM. A fusible link is associated with each active device in series to connect a row and a column. For the BJT this fusible link is placed at the emiter as shown in Fig. 12.18. In MOSFET it is placed at the source. The user
can himself blow out the fusible link Vcc selectively where the connections between aR R R row and a column is not wanted. TheRow-0

blowing out of the fusible links (FL) are done A A1 2

by passing sufficiently large current in a

FL FL FL
pulsed form. This selective blowing of the
Row-1
A1
fusible link means Programming the ROM.A1A0
The ROMs in which this programmingA
FL FL FL

facilities are available are called Program0 Row-2

mable ROM or PROM. To store a bit-1 atA1A0

any crosspoint of the memory matrix we

FL FL FL

have to blow out the fusible link so that theRow-3
connection between the row and the columnA1A0

at that cross point is disrupted permanently.

FL FL FLThe active device used in the PROM with

blown-out fuse is of no use for that cross

D 2 D1 D0point. To store a bit-0 at any crosspoint of the
memory matrix we have to keep the fusibleData Outputs link (FL) intact at the cross point so that byFig. 12.18 : PROM with fusible link (FL) at applying proper address to the row andthe emitter of the transistor. column decoders we can connect the row line and the column line through the active device present at the intersection and the intact fusible link. The selective blowing of the fuse of the EPROM is also called “Burning of the PROM”. Therefore, burning a PROM means selective programming for 1s. Once the PROM is burned then the bit pattern in the memory

matrix becomes fixed and can be used over and over again.

During programming operation, a current in the range of 20mA to 30mA is sent in the pulsed form through the selected active devices in the matrix to blow out the fusible links. For PROM, the BJTs are preferred over MOSFETs because more voltage drops across the MOSFET due to its comparatively high resistance than BJT when the pulsed high current is sent through it during burning of PROM. In some PROM, Schottky type BJT are used for higher speed.

Initially, the material used for the fusible links were nichrome. But the use of nichrome now-a-days is avoided because of the unreliable contacts, corrosion and the reversal of broken links. Therefore, at present the polysilicon fuse technology in used instead of the nichrome. A layer of 0.3☐m of polysilicon is deposited at the cross point. This polysilicon has a low resistance and hence the voltage drop across it is very low. For the Schottky bipolar PROM, titanium tungsten fuses are used as a link instead of polysilicon fuses.

The PROMs are usually available in smaller sizes with TTL compatible output, opencllector or tristate output. But now-a-days large capacity PROMs with electrically fusible polysilicon links have been developed commercially. One point to be noted for the PROM is that once we proramme a PROM for a particular use it can’t be reprogrammed for any other use therefore the burned out active device at the intersection of the row and column of the memory matrix remains useless but consumes large silicon area.

Reprogrammable ROMs have also been developed which will be described next. (iii) Erasable Programmable ROM (EPROM)
A compromise between the performance of ROM and the erasability of ROM system is realized by the use of erasable and programmable ROM or EPROM. As time goes on, fusiblelink PROMs are becoming less popular compared to a different type of PROM, namely Floating gate (First level polysilicon)

Sio2
Control gate Sio2

(Second level polysilicon)

Sio2
Source
Drain n+ n+

p-substrate
Fig.12.19 : EPROM memory cell transistor with a floating erasable and programmable ROM (EPROM), The simplified structure of EPROM is shown in Fig. 12.19. EPROM is fabricated using a special MOSFET as a memory cell. This specially fabricated MOSFET cell has two gates instead of one as we see in the normal MOSFET. The basic MOSFET is enhancement type over which two gates made of polysilicon are fabricated. The gate which is nearer to the channel is called floating gate. It is so called because this gate is electrically isolated, that is, it is left unconnected and floats within the SiO2 medium. Over this floating gate is placed a control gate (select gate) which is electrically coupled to the ROW-select lines coming from the ROWdecoder. This floating gate is used for long time storage of charges.

The operation of the EPROM depends on its ability to store charge on the floating gate.

If the floating gate is chargeless then the control gate behaves as the normal gate. Under this chargeless conditioin of the floating gate, when a positive voltage is applied at the control gate then an electric field is coupled capacitively through the inner gate to the substrate, causing the MOSFET to follow the usual I-V characteristic. The MOSFET with two gate capacitances in series is shown in Fig. 12.20 (a) where CC and CF represent bulk capacitances due to the control gate and the floating gate. The equvalent symbol for the floating gate MOSFET is shown in Fig. 12.20 (b). Due to the capacitive effect the threshold voltage (VT) of the MOSFET with floating gate is slightly larger than without the floating gate.

Cc CF Drain
Drain Gate
Gate
Source Source
Fig. 12.20(a) : Gate capacitance. Fig. 12.20(b) : Symbol of the MOSFET with a floating gate.

If a memory module is fabricated with chargeless floating gate MOSFET as the memory cells using NOR array structure then a logic-0 will be the output when the output from the ROWdecoder is sufficiently higher than the threshold voltage (VT). This happens because the drain of the ON MOSFET pulls the column low to which it is connected. Thus, the presence of a floating gate MOSFET at a cross point of a row and a column outputs a logic-0 when it is selected by the ROWdecoder provided the floating gate of the MOSFET is uncharged. The state of the MOSFET with no charge in the floating gate is called Unprogrammed state. If all the MOSFETs at all the cross points are not programmed then all the column lines will output logic-0 when the ROWdecoder selects the ROWs one by one.

Programming on EPROM means charging the floating gate of the selected MOSFETs in a row of the EPROM module. Before programming EPROM, all the floating gates of the MOSFET cells should be discharged completely. The technique of discharging will be described next. All the MOSFET cells store a logic-0 when they are discharged. To write “1” into the cell, the control gate and the drain are both raised to a high voltage (typically 12V20V between drain and source and about 25V to the control gate) for a short duration of time. An N-type inversion layer is formed at the substrate surface between the source and drain. A large drain current flows through the channel in the normal conduction mode. Fig. 15.39 shows the inversion to be of a tapered shape because of comparatively large drain voltage. The electron flowing to drain with large velocity (electric field between drain and source is about 105 v/cm or higher) gains sufficient kinetic energy to be referred as the hot electron. The electric field established in the insulating oxide due to the large positive voltage on the control gate attracts the hot electrons and accelerates them towards the floating gate. If the hot electrons attracted towards the gate are energized sufficient to overcome the enegy barier of 3.2 ev existing between the silicon substrate and SiO2 then a fraction of electrons traversing the thin oxide, become trapped in the floating gate. This process is self limiting because with the increase of negative charges in the floating gate the electric field strength is reduced in the oxide. The reduced field becomes incapable of accelerating any more of

the hot electrons and ultimately the electons will be repelled. To overcome this repulsion a larger bias will be required on the gate. Thus, the charging of the floating gate is self limiting.

Once the charges are trapped in the floating gate, they remains trapped in this floating gate even if the voltage on the gate and drain are removed. This self limiting process of charging of the floating gate is referred to as Floating Gate Avalanche Injection. This phenomena of charging of the floating gate of the MOSFET of an EPROM is called programming or burning the EPROM. Therefore, in a programmed device, the presence of a logic-1 or 0 in each bit location is determined by the absence or presence of a conducting channel. We know from this discussion that for a programmed cell (floating gate with negative charges) the control gate requires much higher voltage if we need any conduction in the programmed cell. During the read operation the Row-decoder outputs are not sufficient to make the programmed cell conduct and hence the programmed cell outputs a bit-1 and the unprogrammed cell outputs a bit-0.

12.6.1 Erasing the EPROM

Erasing of an EPROM begins to occur upon exposure to light with wavelengths shorter than 4000Å. The commercial EPROM erasures use mercury arc lamps or mercury vapour lamps. These devices emit strong radiation with a wavelength of 2537Å (4.9ev). The typical value of the erasure time is of the order of 15 to 20 minutes. The integrated dose (i.e. UV intensity X exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dose is approximately 15 to 20 minutes using the UV lamp with 12000☐w/cm2 power rating. Due to this radiation the electrons of the floating gate gain enough energy to jump over the inherent potential barier of SiO2-polysilicon and hence the electrons leak away from the floating gate to the substrate.

UV EPROM erasure have three drawbacks :

(i) accidental erasure due to exposure to the fluorescent lamp and incandescent lamps emiting a wavelength of about 3000Å (☐ 4. 1ev). Hence the programmed EPROM must be shielded from long exposure to fluorescent light or sunlight. Typical retention time is many years. They are usually given by the manufacturer of a specific temperature— for example 15 years at 55°c. This assumes that the device will not be exposed for long time to sources of UV radiation. Fluorescent room lighting, for instance, may erase a device within 3 years. Direct sunlight can have the same effect within approximately one week. Device manufacturers provide opaque labels which are placed over the quartz windows to protect them from unintentional erasure. EPROMs are also affected by the Gamma radiation and space environments consisting of protons and other heavy ions.

(ii) they are expensive due to the special ceramic packing and

(iii) they have to be removed from their circuit boards for erasing and reprogramming. For this third drawback, a special socket, called ZIF (Zero Insertion Force) is often used with EPROMs so that they may be easily removed from the circuit for programming : Many EPROMs are available as production EPROMs. The production EPROM are windowless packages. The result is a lower cost “EPROM” that can be programmed once only. Therefore, this EPROM is called OTP (One Time Programmable) EPROM. Such OTP are used in a system that is produced in large quantity and where the data or programmes to be loaded in OTP have been throughly tested. P2764 (8K☐ 8) is an example of production EPROM. The Intel P2764 is one time programmable and has been designed for high volume production. P2764 is highly reliable and fast. Using Intelligent programming algorithm all the 8192 locations (8k locations) can be programmed within 2 minutes. The typical current drawn by the chip is 70mA in the active condition and is only 25mA in the standby mode compared to 100mA and 40mA for 2764; 75mA and 35mA for 2764A.

Furthermore, the EPROMs may contain an identification code (often known as identifier or electronic signature) indicating their manufacturer and type. This code is read by the programming equipment which then choose the appropriate programming algorithm.

12.7 ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM OR E2PROM) A disadvantage of EPROM (UV erasable) is that for any data modification even for a single or a few bytes the EPROM IC needs to be removed from the circuit for erasing with UV radiation and the whole IC has to be reprogrmmed. This requires a long time. A little modification in the structure of the floating gate of MOSFET offers a versatility of in-circuit programming and fast erasing for single byte with electrical pulse. This type of the programmable Read only Memory is called Electrically Erasable and Programmable Read Only Memory (EEPROM or E2PROM). Though, the E2PROM has the advantage of reprogramming over EPROM yet the E2PROM technology has not been able to replace the EPROM except in some applications. Commercially E2PROM ICs are not available with large storage capacity compared to EPROM. The E2PROM takes a longer time for write operation than a typical RAM. The E2PROM is being used today to store the configuration information for such devices like computer terminals, printers and modems. The user can clear the E2PROM and reprogramme it with a new configuration without removing the E2PROM chip.

◆ Structure of FLOTOX cell :

The modified structure of the floating gate used in the E2PROM is called Floating Gate Tunnel Oxide (FLOTOX) cell. Fig. 12.21 (a) shows the simple modification of the floating gate cell. This figure indicates that the floating gate in E2PROM is very close to the n+ drain of the MOS structure. The separation between the n+ drain and the floating gate is of the order of 20 nm. For this small thickness of the SiO2 layer a high electric field of the order of 107 V/cm between n+ drain and the floating gate causes electrons to tunnel either from the n+ drain to the floating gate or from the floating gate to n+ drain depending on the polarity of a high Control gate (polysilicon) Sio2
Floating gate (polysilicon)
n+source
P-Substrate n+drain

Fig.12.21(a) : Structure of a FLOTOX cell of E2PROM Row decoder
output Q1
Programme
FLOTOXLine (P) Q2 Cell
Column Fig.12.21(b) : E2PROM cel voltage of the order of 20V applied between the drain and the control gate. The thin oxide layer through which the electrons tunnel is called tunnel oxide and the MOSFET with this type of structure is known as a FLOTOX (Floating Gate Tunnel Oxide). This reversible tunnelling process is known as Fowler-Nordheim tunnelling. At l each crosspoint of a row and column of the cell matrix of the E2PROM a flotox cell along with a normal MOSFET is used in series as shown in Fig. 12.21(b). The FLOTOX cell Q2 along with the enhancement NMOSFET Q1 is called E2PROM cell.

12.7.1 Erasing, Writing and Reading of E2PROM
0V +20V 0V +20V
Col-0 Col-1 Col-2 Col-3 Row-0 select line0V
0V
VPPline of Row-0
+20V
Row-1 Select line1
1
Q1 Q120V
0
VPPline of Row-1 Q2
Q2
Fig. 12.22(a) : Writing 1 into cells of the cross point (shown within the dotted box) of Row-1, Col-0 and Row-1, Col-2.

Erasing on E2PROM cell (FLOTOX cell in series with enhancement NMOSFET) as shown in Fig. 12.22(a) at any crosspoint of a row-line and a column line means to make FLOTOX cell non-conducting. For erasing, a high voltage VPP of the order of +20V is applied to the control gate with the n+drain grounded. Due to this high voltage, a high electric field in the direction from the floating gate to the n+ drain is established across the tunnel oxide and as a consequence the electrons from the n+ drain enter the floating gate by tunnelling through the tunnel oxide. This process of tunnelling continues until the reverse electric field developed due to the accumulated electrons in the floating gate weakens the electric field from n+drain to the floating gate to a level not sufficient to sustain the tunnelling. The accumulated electrons in the floating gate remain there without any major loss for a long time (10 to 15 years) even after the high voltage at the control gate of the FLOTOX cell is made zero. But the effect of the accumulated electrons of the floating gate is to increase the threshold voltage of the channel of FLOTOX cell. This causes the conduction to be inhibited with a normal +5V at the control gate of this FLOTOX cell. Thus, the FLOTOX cell with negatively charged floating gate cuts off the link between the row-line and the column-line even if the NMOSFET of the E2PROM is selected by the row decoder. No drain current can
flow through the NMOSFET which is connected to the FLOTOX cell to the ground. The absence of the drain current is sensed by the sense amplifier as logic-1 at the data output.

If the polarity of the programming voltage is reversed i.e. n+ drain of the programming FLOTOX cell is +20V more positive than the control gate of this cell, then, by reverse tunnelling the accumulated electrons from the floating gate reach the n+ drain again. This discharge of electrons reduces the threshold voltage of FLOTOX cell and allows the conduction between source and drain with a normal voltage of +5V applied at the control gate of this FLOTOX cell.

0V 20V 20V 0V
0V
Row-0 select line
0V
VPPline of Row-0
20V
Row-1 Select line 0Q 0
1 Q1
0V
Q
2
Q
VPPline of Row-1 2
Fig 12.22(b) : Writing 0 into cells (shown with dotted box) at the cross point of Row-1, Col-2 and Row-1 Column1.

For writing ‘1’ to the cell, the row-decoder output is +20V and the column line is held at 0V for turning the Q1ON and to make the drain of Q2 0V by the ON Q1. The gate of Q2 is pulsed with a positive pulse of amplitude +20V to initiate tunnelling. The floating gate of the FLOTOX cell is charged with electrons and logic-1 is stored in the E2PROM cell. This is shown in Fig. 12.22(a) using dotted box.

For writing ‘0’ to the cell, the row decoder output is made + 20V, the column line is at +20V to make Q1 ON and to bias the drain for Q2 to +20V by the ON Q1. The gate of the FLOTOX cell is held at 0V. This discharges the floating gate of Q2. Then Q2 enters the depletion mode. Logic-0 is stored in the E2PROM cell. This is shown in Fig. 12.22(b).

For reading the E2PROM cell, the gates of Q1 and Q2 are connected to +5V. If Q2 has a stored-1 (floating gate charged) then it will not conduct and E2PROM cell will output ‘1’ on the column line. For a stored 0 (floating gate discharged), Q2 conducts and brings the column line down to logic low. If the row decoder output is low then Q1 will switch OFF and the link between row and column breaks even if the Q2 is ON.

E2PROM cell needs one select transistor connected in series with the FLOTOX cell in order to read the E2PROM cell. The state of the E2PROM cell is determined by sensing the current through the select transistor. Therefore, a typical area of the E2PROM cell is larger than the EPROM. Also, tunnelling mechanism needs gate area several times larger than that required for the avalanche breakdown method in EPROM. Therefore, for same number of bits, the E2PROM needs nearly double area compared to EPROM.

Earlier E2PROM needed +5v and +20v supplies for writing but the next generation E2PROMs need only TTL level voltage. Also the newer E2PROMs automatically perform a byte erase cycle prior to each byte write. Latches are also added on the address and data inputs to hold the information during write cycle unlike the separate erase and write cycle.

The most significant drawback of E2PROM is that the thin tunnel oxide layer is weakened with every write cycle and the data retaintion time gradually decreases. But the other semiconductor devices will last for enormous numbers of cycles and show no evidence of wearing out. For E2PROMs the read cycles are unlimited so these devices may be called “Read Mostly Memories”.

The time for writing into this memory is relatively longer, typically, 1 to 10 msec, because the tunnelling current through the oxide is small, so it takes time to build up sufficient charge on the floating gate. Thus, a special interface (which is usually built into the memroy chip) is required for connection to the relatively fast buses of a microprocessor system.

12.8 DYNAMIC RAM (DRAM) CELL

Due to nearly infinite input resistance of the MOSFET a very low leakage current from the gate region flows which has simplified the temporary data storage. Due to low leakage of current from the gate, the charge can be stored on the gate capacitance and the gate parasite capacitance for a time of milliseconds to tenth of seconds. This storage of charge in the capacitance acts as a memory cell. The advantage of this type of memory cell is that it is very simple and requires a small space. Thus, the cost per dynamic RAM cell is much smaller than

the static RAM cell. But the problem is that the capacitive cell cannot hold its charge for a long time and the capacitor will discharge unless the cell is recharged periodically before the loss of data. This procedure is called Refreshing of cells. This refreshing should be performed even if the memory cells are not used for read/write operation in the circuit. To keep the data in the cell intact we need periodic charging of the cells. Therefore this type of memory is called Dynamic and the memory module fabricated using such cells is called Dynamic memory (DRAM). The circuit for refreshing adds an extra level of complication to the DRAM hardware and also to the timing of the READ and WRITE cycles, since the memory might have to be refreshed between READ and WRITE tasks. Therefore, the DRAM timing cycles are much more complicated than the equivalent SRAM cycle.

RAS
A0/A7
1
2A1/A8
A2/A
9
RowRow
A3/A10
address address Dout A4/A11
latch decoder
A5/A12
A6/A13
128 128 ☐128Din

dynamic

memory

1 array

2 (16,384 bits)

ColumnColumn

address address

latch decoder

128
CAS
CS R W Fig. 12.23 : Black diagram of 15 Kbit dynamic RAM

This inconvenience is offset by the high bit densities of DRAM, which are possible due to the simplicity of the DRAM cell. Upto 4 to 15 megabits of data can be stored on a single 20 pin chip. Already 256 megabits dynamic RAMs are based on 0.25 ☐ m technology and uses 20 to 40pF. capacitor as a memory cell capacitor.

Dynamic RAM is often bit organized. Therefore, read/write operation can be done for one bit at a time and for this reason a DRAM with a large capacity requires more address lines than a static RAM. For example (4Mb☐ 1) DRAM requires 22 address lines (222 = 4196,304). But, in order to save pins, address multiplexing is used to specify the address of each cell. The same pins of the IC package are multiplexed to input the row address and

the column address of a cell. To load these two addresses into the row and column decoder, two strobe signals RAS☐☐ row address select) and CAS☐☐ Column address select) are used externally. Simplified block diagram of a 15 Kbit dynamic RAM is shown in Fig. 12.23.

12.8.1 Four Transistor Dynamic RAM Cell

The Fig 12.24(a) shows the circuit for a dynamic memoy cell using four NMOS transistors. The parasitic capacitors C1 and C2 between the gate and source of the transistors Q1 and Q2 are used to store the information in the form of a bits. The NMOS transistors Q3 and Q4 act as load and are also used for the selection of one cell from a row of cells.

If logic-1 is to be stored then the capacitors C1 is charged to VDD (☐ Q1 ON) and the capacitor C2 is discharged (☐ Q2 OFF). VDD This cell can be selected by making the

input X logic high ( ☐ high output of

Row
row decoder). The charged capacitor
Select
slowly decays if it is not accessed forlive X a time T. The charged capacitor C1 (or
C2) leaks through the reverse biased N+ P junction (drain and substrate) of
Q

3 Q4 Q1 (or Q2). If T is long then 1-state

voltage in a capacior may become small

enough after decay to be

indistinguishable from the logic-0 level

and the actual information will be lost.

For this reason an additional circuit isQ1

Q 2 used to recharge the capacitor to its

C C2 full capacity before the drop in the1

charge of the capacitor becomes

significant. The additional circuit along

with Read/Write logic circuit with the

cell is shown in Fig 12.24(b). This Fig. 12.24(a) : 4 NMOS dynamic cell recharging of refreshing of the capacitor is done by activating the refresh input (R) high simultaneously with row select input (X) high. The transistors Q5 and Q6 as shown in this circuit are in series with Q3 and Q4 rspectively and are also shared by all the cells present in a column. For each column this additional circuit is used separately. To understand the operation of this cell assume that the capacitor C2 is charged to its full value (i.e. Q2 ON) and C1 is in discharged condition (i.e. Q1 OFF). Any charge on C1 will be discharged through the ON transistor Q2. The state of circuit (Q2 ON, Q1 OFF) indicates that the cell has stored logic-0. The voltages on C1 and C2 are V1 (=0V), V2 (=VDD) respectively.

To other cells in this column To other cells
in this column

VDD
This circuit is shared by all the cells Refresh(R) present in one column Q5
Q6
Row
To other cells Select
in this row X(RAS)
Q3
Q4
V1 V2
Q1
Q2
C1 C2
Q7
Q8

Y(CAS)

(To other cells
in this column)

VDD
Q11 Q15
Q16 Q12
A B
Q13
Q14
(write ‘0’)Q
Q10 WWD 9
in
(write ‘1’) Din
Read/writeRead/write R/W Q
amplifier for 1amplifier for 0
17
Fig. 12.24 (b) : 4-transistor dynamic RAM cell with road/write logic
398

But due to leakage of charge, V2 will gradually fall. To overcome this loss of charge, the cell is addressed using the X input (RAS) while the refresh input (R) is high. This process will refresh, all the cells in a row simultaneously because the RAS and R input are common to all the cells in a row. During this refreshing, Q3 in series with Q5, and Q4 in series with Q6 are ON. The capacitor C2 is charged towards VDD through Q5 and Q3. But, Q1 is OFF and C1 will not be charged through Q6 and Q4 as Q2 is ON. Thus, any loss of charge in C2 can be overcome by periodic refreshing and the state of logic-0 can be restored. If the refreshing is done with Q2 OFF and Q1 ON (storing logic-1 in the cell) then the capacitor C1 will be charged near VDD through the ON transistor Q6 and Q4 but the capacitor C2 cannot get its charging current because of the ON transistor Q1 which bypasses the current flowing through ON transistors Q5 and Q3.

For writing 0 into the cell, R /W = 1, D in = 1 and RAS = CAS = 1. For this reason Q9 and Q10 are OFF and ON respectively. The left Read/Write amplifier produces a logic-1 on DATA line and the right Read/Write amplifier produces a logic-0 on DATA line and therefore the capacitor C2 will be charged through the ON transistor Q3 and DATA line and Q2 will be ON. Any charge accumulated on C1 will be discharged through ON transistor Q2.

Similarly, to write 1 into the cell R /W = 1, Din = 1 and RAS = CAS = 1. For this reason Q9 and Q10 are ON and OFF respectively. Thus, the two Read/Write amplifiers make the DATA and DATA logic-0 and logic-1 respectively. The voltage corresponding to logic-1 on DATA line charges the capacitor C1 through ON transistor Q4 towards VDD. Therefore, Q1 will be ON and any charge previously accumulated on C2 will be discharged through VDD RVDD R
RefreshQ5, Q6
Q5, Q6 Circuit Row-0
(X0)
X
X
D D
D D
(0, 0) (0, 1) Memory Row-1
Cells(X0)
X
D D
X
D D
(1, 0)
(1, 1)
Q7 Q8
Q7 Q8
To read/write
Col-1amplifierCol-0
(Y1) To read/write (Y0) amplifier
Fig. 12.24(c) : A dynamic memory with 4 cells.
the ON transistor Q1.

To read the cell, the R /W input should be at logic-0 and the input RAS and CAS should at logic-1. The transistor Q17 will be OFF and Q3, Q4, Q7, and Q8 all become ON. The DATA and DATAlines will attain the voltage of V1 and V2 respectively. For the cell storing logic-0 (i.e. V2 = VDD and V1 = 0V) the DATA and DATA will be at logic-0 and logic-1. The transistors Q14 and Q13 will be OFF and ON respectively and therefore, output A will be at logic-0 and output B will be at logic-1. Similarly, the cell storing logic-1 (V2 = 0V and V1 = VDD) will give us voltage corrresponding to logic-1 and logic-0 on the output A and B respectively when R /W = 0 and CAS = RAS = 1. Because, under this condition the DATA andDATA lines are of logic-1 and logic-0 through the ON transistors Q4 and Q3. Therefore, the transistors Q14and Q13are ON and OFF respectively. The gate of Q14is connected to DATA line and the gate of Q13 is connected to DATA line. This leads to the ouput A going high and B going low. Thus, the output A follows the logic state of the cell and the output B follows the inverse of the state of the cell. The block diagram of a (4☐ 1) dynamic memory with four cell arranged in 2☐2 matrix is shown in Fig. 12.24(c).

12.8.2 Three Transistor Dynamic RAM Cell

The basic dynamic RAM cell using three NMOS transistors is shown in Fig. 12.25. In this configuration crosscoupled flipflop is not used to store the information of bit. The capacitor C (this capacitor is the parasitic capicitor between gate and the source of Q2 but not fabricated) between the gate and the source of Q2 is used to store the information of a bit. The fully charged capacitor representsReadlogic-1 and completely discharged (R) capacitor represents logic-0.Write

If the capacitor is charged sufficiently(w)

Q 3 Doutso that the voltage V exceeds the

threshold voltage of the transistor Q

2
D
in
Q
V
1

Q 2then Q2becomes ON and if the capacitor
is uncharged then Q2 becomes OFF. ForC

read operation, the READ input (R) is

high and Q3 conducts. Thus, for the cell Fig.12.25 : Basic dynamic RAM cell using 3 NMOS transistorssorting logic-1 both Q2 and Q3 are ON

and Dout will output a vooltage corresponding to logic-0 as the source end of the conducting Q2 is grounded. On the otherhand, if the cell is initially stored with logic-0 then D out will output a voltage corresponding to logic-1 because Q2 is open for this case. The logic state of the output is inverse of the logic state of the stored bit therefore the output is labelled as Dout .

For write operation, the write line (W) is made high. If Din = 1 with write line high the capacitor C will be charged through the ON transistor Q1 if the capacitor is initially uncharged. Otherwise no charging will occur if the capacitor is already fully charged. This is called writing of 1 into the cell. If Din= 0, the capacitor C will be discharged through Q1 if C was 400

initially charged (storing-1) and no further discharging will occur if the capacitor is initially unchanged (storing-0).
12.8.3 One Transistor Dynamic RAM Cell Further reduction in the number of active device is achieved in the one transistor DRAM cell. Like three transistor cell, the one transistor cell also uses the parasitic capacitor for the storage of charge to represent logic-1 or logic-0. The one transistor cell is very much popular and widely used in the high density DRAM. The basic structure of this one transistor DRAM cell is shown in Fig. 12.26. The transistor Q1 acts as a switch which connects the storage X
Row line
capacitor C1 to the data bit line. As with the RAMs, one cell in the memory is selected at a given time
Q1
C1
C2
Y Q2
to R/W
amplifier
Fig. 12.26 : One transistor DRAM cell depending upon X and Y addresses. To write a bit in the cell i.e. in the capacitor C1, the data bit line is switched on to the capacitor C1through the transistor Q1. Similarly, the reading is done by sensing the capacitor voltage level by the sense amplifier after connecting the bit line to the capacitor C1. But this reading process is destructive in nature. This occurs because the selected storage capacitor C1 comes in parallel with the stray capacitor C2 of the bit line. If V1 is the initial voltage of the capacitor C1 due to the storage of charge in C1 and the capacitor C2 is completely discharged then the readout voltage VR will be VR = C1V1/ (C1+ C2). The value of C2 is much larger than C1 because many cells are connected to the same column line and therefore, VR < V1. For this reason, the capacitor voltage should be restored to V1 after each read operation. When a cell is read, the data bit line is precharged to a high voltage (=3.3V) before reading. After this, the data bit line is connected to the data bit. If the cell is initially at logic-1 (i.e.) fully charged then the data bit line voltage will not change when the cell capacitor is connected to the bit line but on the other hand if the cell is initially at logic-0 (i.e. capacitor C1 is discharged) then the data bit line is discharged to a slightly smaller voltage when the storage capacitor is connected to the data bit line. The difference between these voltages is detected by the sense amplifier. This situation is improved by increasing the ratio C1/C2 using n-channel two layer polysilicon gate technology.

The read operation is destructive because after each read operation the cell is charged to a voltage very close to the precharge voltage (=3V) of the data bit and irrespective of the state of the storage capacitor C1, it will be charged close to logic-1. Thus, to restore the correct initial content the cell must be rewritten by either keeping the data bit high if logic-1 was stored in C1 or by pulling the data bit line to around 0V if logic-0 was the initial content.

INDEX

2-level AND-OR(OR-AND) Implementation 163
2-LEVEL LOGIC CIRCUIT IMPLEMENTATION USING ONLY NOR GATES 173
4-Bit Magnitude Comparator 232
4-to-10 Decoders 225
4-to-16 Decoder/Demultiplexers 226
7-Segment Diaplay Driver 251
7-Segment Display 248
9.5 D-Latch 285
A
ACTIVE LEVELS OF A LOGIC SIGNAL 80
ADDRESS DECODING AND ROW SELECTION 385
Adjacency Theorem 94
Adsorption Theorem 94
Algorithm for binary addition using FullAdder 26
Analysis of 2-input NAND Gate Circuit 190
Analysis of a 3-bit Synchronous Binary UP Counters 340
Analysis of a 4-bit Synchronous Binary Down Counters 343
AND-OR (OR-AND) Implementation of Logiccircuit 162
AND and OR Gate 77
AND gate 66
ARITHMETIC OPERATION WITH NON-DECIMAL NUMBERS 22 ASCII Code 54
Associative Theorem 95
Asynchronous Binary Ripple Counters 314
ASYNCHRONOUS COUNTERS 314
B
Basic Logic Gates And their Properties 65
BASIC MEMORY DEVICES - LATCHES AND FLIPFLOPS 265
BASIC TTL NAND GATE CIRCUIT 189
BCD-to-Binary Code Converter 240
BCD-to XS-3 and XS-3 to -BCD Code Converter 236
BCD-to XS-3 and XS-3 to -BCD Code Converter 238
BCD Additions of two Negative BCD numbers 46
Bidirectional Shift Registers 307
Bidirectional Registers 299
Binary-to-BCD Code Converter 238
Binary-to-Decimal Number Conversion 9
Binary-to-Gray Code Conversion 50
Binary Addition 22
Binary Addition and Subtraction 22
Binary Number System 8
Binary Ripple Down Counter 322

401

Binary Ripple UP/DOWN Counters 324
Binary Subtraction 27
Binary UP Ripple Counters 316
Bipolar RAM Cell 374
Biquinary Code 58
Block Parity 60
Boolean Swithing Algebra and Its Applications 89
Boundaries Theorem or Closure of Identity Elements 91
C
CANNONICAL FORMS OF SWITCHING FUNCTIONS 102 Cascading of Decoders/Demultiplexers 227
Characteristic Table of SR Latch 267
CMOS Static RAM Cell 377
CODE CONVERTERS 234
Combination Logic Circuit Implementation with SSI And MSI 215 Commercially Available Priority Encoder 260
COMPLEMENTARY MOS LOGIC 212
Complement Theorem 93
Computer Codes 45
Consensus Theorem 94
Counters 313
D
Data lines 367
Decimal-to-BCD Encoder 255
Decimal-to-Octal Number Conversion 14
Decimal to Hexadecimal Number Conversion 18
DECODER 219
Decoder Design 221
Definition -2 : Prime Implicant (or Prime Implicate) 128
Definition-3 : Essential Prime Implicant (or Essential Prime Implicate) 129 Definition-4 : Distinguished Minterm (Maxterm) 129
Definition-5 : Optional Prime Implicant (Implicate) 130
Definition-6 : Redundant Prime Implicant (or Implicate) (RPI) 130 Definition-7 : Minimal Cover 130
Definition –1 : Implicant and Implicate 127
DeMorgan’s Theorem 97
Demultiplexer 224
Design of 4-to-1 Multiplexer 217
Design of Modulo Ripple Counter (or Truncated Counters) 326 Determination of Prime Implicants 140
Diode ROM array 381
DISPLAY AND DISPLAY DRIVER 244
Duality 91
DUAL PROPERTY OF THE CIRCUIT 181
DYNAMIC RAM (DRAM) CELL 394

E
Edge Triggered FlipFlops 280
Effect of Glitches in Master-Slave JK FlipFlop 279
ELECTRICAL CHARACTERISTICS OF LOGIC GATES 195
ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM OR E2PROM) 391
ENABLE AND INHIBIT PROPERTIES OF LOGIC GATES 77
Encoders and Priority Encoders 254
Equality Theorem 92
Erasable Programmable ROM (EPROM) 388
Erasing, Writing and Reading of E2PROM 392
Erasing the EPROM 390
ERROR DETECTING AND CORRECTION CODES 56
Essential Prime Implicants 151
Excess-3 Gray Code 54
Exclusive-OR gate (EX-OR or XOR-gate) 73
EXOR and XNOR Gate 79
External Organization 366
External Pull-UP Resistor (Rext) for the Open Collector Output 202
F
Fan-In 200
Fan-out 199
FLIP FLOPS 274
Forbidden Combination Check Code 57
FORMATION OF KARNAUGH MAP FOR SWITCHING FUNCTIONS 109 Four-variable Karnaugh Map (Fourth order K-map) 117
Four Transistor Dynamic RAM Cell 396
Functional Behaviour of Logic Gates 65
G
Gated D-Latch 286
Gated D-Latch with Multiplexer 289
Gated SR-Latch 268
Glitch free Resetting of Asynchronous Counters 335
Gray-to-Binary and Binary -to-Gray Code Converter 235
Gray-to-Binary code conversion 52
Gray Code 49
Grouping of Minterms 139
H
Hamming Code 61
Hexadecimal-to-Decimal Number Conversion 18
Hexadecimal Addition 32
Hexadecimal Addition and Subtraction 32
Hexadecimal Number System16
Hexadecimal Subtraction 33

I
Idempotent Theorem 91
Implementation of Combination Logic Circuit with Basic Logic Gates 161 INCOMPLETELY SPECIFIED FUNCTIONS (DON’T CARES) 133 Input/Output Current and Voltage Parameters 197
Involution Theorem 93
L
LATCH 265
LED Display 244
LEVEL LOGIC CIRCUIT IMPLEMENTATION USING ONLY NAND GATES 168 Logic Familes 187
LOGIC GATE DUALITY 82
LOGIC GATES TYPES 66
LOGIC GATES USING N-CHANNEL MOSFET (NMOS) 209
M
M-out-of-N codes 57
MAP FACTORING METHOD 176
Mapping of Incompletely Specified Functions in a K-map 135
Mask Programmable ROM 386
Master-Slave FlipFlop 276
Master-Slave JK-Flip-Flop 278
Memories 363
Minimisation of Incompletely Specified Function using K-map. 136 MOD-10 (Decade or BCD) Synchronous Counter 350
MOD-10 Asynchronous (Ripple) Counter (or Decade Counter or BCD Counter):333 MOD-3 Asynchronous Counter 327
MOD-3 Asynchronous DOWN Counter 329
MOD-3 Asynchronous UPCounter 327
MOD-3 Synchronous Counter 347
MOD-5 Asynchronous (Ripple) Counter 330
MOD-5 Asynchronous (Ripple) DOWNCounter 332
MOD-5 Synchronous Counter 348
MOD-5 UP Asynchronous (Ripple) Counter 331
Modified Totem Pole Output Stage 195
MOSFET ROM Array 383
MOS LOGIC FAMILY 204
MOS Static RAM Cell 378
Multibit Binary Addition 24
Multilevel AND-OR (OR-AND) Implementation 166
MULTIPLEXERS 215
Multiplication of Unsigned Binary Numbers 34
Multiplication starting with L.S.B of the multiplier bits 35
N
NANDgate 70
NAND and NOR Gate 78
NMOS INVERTER 207
NOR-gate 72
NOT-gate 69
Number System and Computer Codes 2
Number Systems 6
O
Octal-to-Binary Encoder 256
Octal-to-Decimal Number Conversion 14
Octal 15
Octal Addition 29
Octal Addition and Subtraction 29
Octal Subtraction 31
One Transistor Dynamic RAM Cell 400
One Variable Karnaugh map (First order K-map) 109
OPEN COLLECTOR TYPE LOGIC GATES 200
OR-gate 68
ORGANIZATION OF STATIC READ/WRITE MEMORY 366
P
Parallel-In-Parallel-Out (PIPO) Shift Register 305
Parallel-In-SerialOut (PISO) Shift Register 304
PARALLEL REGISTERS 295
Parity 58
Parity Generator/Checker Circuit 230
PARITY GENERATORS AND CHECKERS 229
POSTULATES OF SWITCHING ALGEBRA 89
Power Dissipation 198
Priority Encoder 257
PROM (Programmable ROM) 387
Propagation Delay 196
Pulse Triggered FlipFlop 276
Q
QUINE MCCLUSKEY METHOD OF MINIMISATION 138
QUINE MCCLUSKY SIMPLIFICATION OF FUNCTIONS CONTAINING DON’T CARE TERMS 153
R
RAM CELLS 373
Reading from the cell 375
Read Operation 379
Registers and SHift Registers 295
Repeated Division Method for the conversion of Decimal Integer to
Repeated Multiplication Method for the Conversion of Decimal Fraction to Octal 15 ROM cell structure 384
S
SEMICONDUCTOR READ-ONLY MEMORY (ROM) 380
Sequential Logic Circuits and Bistable Devices 265
Serial-In-Parallel-Out (SIPO) Shift Register 303
Serial-In-SerialOut (SISO) Shift Register 301
SHIFT REGISTERS 300
Sign-Magnitude Representation 36
SIGNED MULTIPLICATION 39
SIGNED NUMBER REPRESENTATION 36
Simplification of 2-variable Function Using a Second-Order K-map 120
Simplification of 3-variable Function Using Third-order K-map 123
SIMPLIFICATION OF 4-VARIABLE FUNCTION USING FOURTH-ORDER K-MAP 131 Simplification of Boolean Expression 109
SIMPLIFICATION OF SWITCHING FUNCTIONS USING KARNAUGH MAPS 119 Simplification theorem or Elimination Theorem 95
SOME DEFINITIONS 127
SRlatch with Preset and Clear 272
Structure and Operation MOSFET 205
Structure of FLOTOX cell 391
SYNCHRONOUS COUNTERS 339
T
T FLIPFLOP 282
THEOREMS OF THE SWITCHING ALGEBRA 91
The POS Representation 104
The SOP Representation 102
Three-Variable Karnaugh Map (Third order K-map) 114
Three Transistor Dynamic RAM Cell 399
Transformation of a SOP Expression into an Expression Containing XOR and AND Gates Only 182 TRANSISTOR AS AN INVERTER 187
Transistor ROM Array 382
TRISTATE LOGIC GATES (TSL GATES) 203
Two-variable Karnaugh map (Second order K-map) 111
Type of FlipFlops 275
TYPES OF PROGRAMMABLE ROMS 386
U
Universal Shift Register 309
Upper Bound of Error Due to Truncation 12
Upper Bound of Error Due to Truncation 13
W
Weighted Positional Number System 6
Weighted Sum Method 14
Write Operation 379
Writing into the cell 376
X
xclusive -NOR gate (EX-NOR or XNOR gate 75
XOR IMPLEMENTATION OF THE LOGIC CIRCUITS 182